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[LSD] Readded the directory now with the necessary directories only

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TiagoRG 2023-03-29 00:15:35 +01:00
parent b90732d034
commit 60947591ac
100 changed files with 11953 additions and 0 deletions
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# Laboratórios de Sistemas Digitais
## Trabalho prático 01
### Tópico principal da aula: Introdução às FPGAs
* [Slides](https://github.com/TiagoRG/uaveiro-leci/blob/master/1ano/2semestre/lsd/slides/LSD_2022-23_AulaTP01.pdf)
* [Guião](https://github.com/TiagoRG/uaveiro-leci/blob/master/1ano/2semestre/lsd/pratica01/LSD_2022-23_TrabPrat01-2.pdf)
---
*Pode conter erros, caso encontre algum, crie um* [*ticket*](https://github.com/TiagoRG/uaveiro-leci/issues/new)

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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "graphic" (version "1.4"))
(pin
(input)
(rect 344 240 512 256)
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
(text "SW[0]" (rect 5 0 39 13)(font "Intel Clear" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
)
(pin
(input)
(rect 344 256 512 272)
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
(text "SW[1]" (rect 5 0 39 13)(font "Intel Clear" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
)
(pin
(output)
(rect 592 248 768 264)
(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
(text "LEDR[0]" (rect 90 0 132 11)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
(line (pt 52 4)(pt 78 4))
(line (pt 52 12)(pt 78 12))
(line (pt 52 12)(pt 52 4))
(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
)
(symbol
(rect 520 232 584 280)
(text "AND2" (rect 1 0 29 10)(font "Arial" (font_size 6)))
(text "inst" (rect 3 37 21 48)(font "Arial" ))
(port
(pt 0 16)
(input)
(text "IN1" (rect 2 7 23 18)(font "Courier New" (bold))(invisible))
(text "IN1" (rect 2 7 23 18)(font "Courier New" (bold))(invisible))
(line (pt 0 16)(pt 14 16))
)
(port
(pt 0 32)
(input)
(text "IN2" (rect 2 23 23 34)(font "Courier New" (bold))(invisible))
(text "IN2" (rect 2 23 23 34)(font "Courier New" (bold))(invisible))
(line (pt 0 32)(pt 14 32))
)
(port
(pt 64 24)
(output)
(text "OUT" (rect 48 15 69 26)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 69 26)(font "Courier New" (bold))(invisible))
(line (pt 42 24)(pt 64 24))
)
(drawing
(line (pt 14 12)(pt 30 12))
(line (pt 14 37)(pt 31 37))
(line (pt 14 12)(pt 14 37))
(arc (pt 31 37)(pt 30 12)(rect 18 12 43 37))
)
)
(connector
(pt 512 248)
(pt 520 248)
)
(connector
(pt 512 264)
(pt 520 264)
)
(connector
(pt 584 256)
(pt 592 256)
)

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/*<simulation_settings>
<ftestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off GateDemo -c GateDemo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/GateDemo.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/simulation/qsim/GateDemo.vwf.vht"</ftestbench_cmd>
<ttestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off GateDemo -c GateDemo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/GateDemo.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/simulation/qsim/GateDemo.vwf.vht"</ttestbench_cmd>
<fnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/simulation/qsim/" GateDemo -c GateDemo</fnetlist_cmd>
<tnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/simulation/qsim/" GateDemo -c GateDemo</tnetlist_cmd>
<modelsim_script>onerror {exit -code 1}
vlib work
vcom -work work GateDemo.vho
vcom -work work GateDemo.vwf.vht
vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.GateDemo_vhd_vec_tst
vcd file -direction GateDemo.msim.vcd
vcd add -internal GateDemo_vhd_vec_tst/*
vcd add -internal GateDemo_vhd_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script>
<modelsim_script_timing>onerror {exit -code 1}
vlib work
vcom -work work GateDemo.vho
vcom -work work GateDemo.vwf.vht
vsim -novopt -c -t 1ps -sdfmax GateDemo_vhd_vec_tst/i1=GateDemo_vhd.sdo -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.GateDemo_vhd_vec_tst
vcd file -direction GateDemo.msim.vcd
vcd add -internal GateDemo_vhd_vec_tst/*
vcd add -internal GateDemo_vhd_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script_timing>
<hdl_lang>vhdl</hdl_lang>
</simulation_settings>*/
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
HEADER
{
VERSION = 1;
TIME_UNIT = ns;
DATA_OFFSET = 0.0;
DATA_DURATION = 1000.0;
SIMULATION_TIME = 0.0;
GRID_PHASE = 0.0;
GRID_PERIOD = 10.0;
GRID_DUTY_CYCLE = 50;
}
SIGNAL("LEDR[0]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("SW[0]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("SW[1]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
TRANSITION_LIST("LEDR[0]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("SW[0]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 80.0;
LEVEL 1 FOR 100.0;
LEVEL 0 FOR 240.0;
LEVEL 1 FOR 200.0;
LEVEL 0 FOR 40.0;
LEVEL 1 FOR 60.0;
LEVEL 0 FOR 80.0;
LEVEL 1 FOR 100.0;
LEVEL 0 FOR 100.0;
}
}
TRANSITION_LIST("SW[1]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 240.0;
LEVEL 1 FOR 100.0;
LEVEL 0 FOR 140.0;
LEVEL 1 FOR 80.0;
LEVEL 0 FOR 100.0;
LEVEL 1 FOR 60.0;
LEVEL 0 FOR 40.0;
LEVEL 1 FOR 200.0;
LEVEL 0 FOR 40.0;
}
}
DISPLAY_LINE
{
CHANNEL = "SW[0]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 0;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "SW[1]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 1;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "LEDR[0]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 2;
TREE_LEVEL = 0;
}
TIME_BAR
{
TIME = 0;
MASTER = TRUE;
}
;

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1ano/2semestre/lsd/pratica01/part1/output_files/GateDemo.sof Normal file
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1ano/2semestre/lsd/pratica01/part2/AND2Gate.bsf Normal file
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 176 96)
(text "AND2Gate" (rect 5 0 51 12)(font "Arial" ))
(text "inst" (rect 8 64 20 76)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "inPort0" (rect 0 0 27 12)(font "Arial" ))
(text "inPort0" (rect 21 27 48 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
(pt 0 48)
(input)
(text "inPort1" (rect 0 0 25 12)(font "Arial" ))
(text "inPort1" (rect 21 43 46 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48)(line_width 1))
)
(port
(pt 160 32)
(output)
(text "outPort" (rect 0 0 28 12)(font "Arial" ))
(text "outPort" (rect 111 27 139 39)(font "Arial" ))
(line (pt 160 32)(pt 144 32)(line_width 1))
)
(drawing
(rectangle (rect 16 16 144 64)(line_width 1))
)
)

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1ano/2semestre/lsd/pratica01/part2/AND2Gate.vhd Normal file
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-- Bibliotecas
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Interface (portos)
entity AND2Gate is
port(
inPort0 : in std_logic;
inPort1 : in std_logic;
outPort : out std_logic
);
end AND2Gate;
-- Implementação (descrição do funcionalidade)
architecture Behavioral of AND2Gate is begin
outPort <= inPort0 and inPort1;
end Behavioral;

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1ano/2semestre/lsd/pratica01/part2/AND2Gate.vwf Normal file
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/*<simulation_settings>
<ftestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off VHDLDemo -c AND2Gate --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/AND2Gate.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/simulation/qsim/AND2Gate.vwf.vht"</ftestbench_cmd>
<ttestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off VHDLDemo -c AND2Gate --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/AND2Gate.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/simulation/qsim/AND2Gate.vwf.vht"</ttestbench_cmd>
<fnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/simulation/qsim/" VHDLDemo -c AND2Gate</fnetlist_cmd>
<tnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/simulation/qsim/" VHDLDemo -c AND2Gate</tnetlist_cmd>
<modelsim_script>onerror {exit -code 1}
vlib work
vcom -work work AND2Gate.vho
vcom -work work AND2Gate.vwf.vht
vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.AND2Gate_vhd_vec_tst
vcd file -direction VHDLDemo.msim.vcd
vcd add -internal AND2Gate_vhd_vec_tst/*
vcd add -internal AND2Gate_vhd_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script>
<modelsim_script_timing>onerror {exit -code 1}
vlib work
vcom -work work AND2Gate.vho
vcom -work work AND2Gate.vwf.vht
vsim -novopt -c -t 1ps -sdfmax AND2Gate_vhd_vec_tst/i1=AND2Gate_vhd.sdo -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.AND2Gate_vhd_vec_tst
vcd file -direction VHDLDemo.msim.vcd
vcd add -internal AND2Gate_vhd_vec_tst/*
vcd add -internal AND2Gate_vhd_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script_timing>
<hdl_lang>vhdl</hdl_lang>
</simulation_settings>*/
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
HEADER
{
VERSION = 1;
TIME_UNIT = ns;
DATA_OFFSET = 0.0;
DATA_DURATION = 1000.0;
SIMULATION_TIME = 0.0;
GRID_PHASE = 0.0;
GRID_PERIOD = 10.0;
GRID_DUTY_CYCLE = 50;
}
SIGNAL("inPort0")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("inPort1")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("outPort")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
TRANSITION_LIST("inPort0")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 40.0;
LEVEL 1 FOR 180.0;
LEVEL 0 FOR 220.0;
LEVEL 1 FOR 220.0;
LEVEL 0 FOR 120.0;
LEVEL 1 FOR 120.0;
LEVEL 0 FOR 100.0;
}
}
TRANSITION_LIST("inPort1")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 280.0;
LEVEL 1 FOR 80.0;
LEVEL 0 FOR 140.0;
LEVEL 1 FOR 120.0;
LEVEL 0 FOR 100.0;
LEVEL 1 FOR 220.0;
LEVEL 0 FOR 60.0;
}
}
TRANSITION_LIST("outPort")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
DISPLAY_LINE
{
CHANNEL = "inPort0";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 0;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "inPort1";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 1;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "outPort";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 2;
TREE_LEVEL = 0;
}
TIME_BAR
{
TIME = 0;
MASTER = TRUE;
}
;

19
1ano/2semestre/lsd/pratica01/part2/GateDemo.vhd Normal file
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library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity GateDemo is
port (
SW : in std_logic_vector(1 downto 0);
LEDR : out std_logic_vector(1 downto 0)
);
end GateDemo;
architecture Shell of GateDemo is
begin
system_core: entity work.NAND2Gate(Structural)
port map(
inPort0 => SW(0),
inPort1 => SW(1),
outPort => LEDR(0)
);
end Shell;

137
1ano/2semestre/lsd/pratica01/part2/NAND2Block.bdf Normal file
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "graphic" (version "1.4"))
(pin
(input)
(rect 200 232 368 248)
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
(text "inPort0" (rect 5 0 44 13)(font "Intel Clear" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
)
(pin
(input)
(rect 200 248 368 264)
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
(text "inPort1" (rect 5 0 43 13)(font "Intel Clear" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
)
(pin
(output)
(rect 704 232 880 248)
(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
(text "outPort" (rect 90 0 127 11)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
(line (pt 52 4)(pt 78 4))
(line (pt 52 12)(pt 78 12))
(line (pt 52 12)(pt 52 4))
(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
)
(symbol
(rect 376 208 536 288)
(text "AND2Gate" (rect 5 0 60 11)(font "Arial" ))
(text "inst" (rect 8 64 26 75)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "inPort0" (rect 0 0 36 11)(font "Arial" ))
(text "inPort0" (rect 21 27 57 38)(font "Arial" ))
(line (pt 0 32)(pt 16 32))
)
(port
(pt 0 48)
(input)
(text "inPort1" (rect 0 0 36 11)(font "Arial" ))
(text "inPort1" (rect 21 43 57 54)(font "Arial" ))
(line (pt 0 48)(pt 16 48))
)
(port
(pt 160 32)
(output)
(text "outPort" (rect 0 0 37 11)(font "Arial" ))
(text "outPort" (rect 108 27 145 38)(font "Arial" ))
(line (pt 160 32)(pt 144 32))
)
(drawing
(rectangle (rect 16 16 144 64))
)
)
(symbol
(rect 544 208 696 288)
(text "NOTGate" (rect 5 0 53 11)(font "Arial" ))
(text "inst1" (rect 8 64 32 77)(font "Intel Clear" ))
(port
(pt 0 32)
(input)
(text "inPort" (rect 0 0 30 11)(font "Arial" ))
(text "inPort" (rect 21 27 51 38)(font "Arial" ))
(line (pt 0 32)(pt 16 32))
)
(port
(pt 152 32)
(output)
(text "outPort" (rect 0 0 37 11)(font "Arial" ))
(text "outPort" (rect 100 27 137 38)(font "Arial" ))
(line (pt 152 32)(pt 136 32))
)
(drawing
(rectangle (rect 16 16 136 64))
)
)
(connector
(pt 704 240)
(pt 696 240)
)
(connector
(pt 544 240)
(pt 536 240)
)
(connector
(pt 368 240)
(pt 376 240)
)
(connector
(pt 368 256)
(pt 376 256)
)

27
1ano/2semestre/lsd/pratica01/part2/NAND2Gate.vhd Normal file
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@ -0,0 +1,27 @@
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity NAND2Gate is
port (
inPort0 : in std_logic;
inPort1 : in std_logic;
outPort : out std_logic
);
end NAND2Gate;
architecture Structural of NAND2Gate is
signal s_andOut : std_logic;
begin
and_gate : entity work.AND2Gate(Behavioral)
port map(
inPort0 => inPort0,
inPort1 => inPort1,
outPort => s_andOut
);
not_gate : entity work.NOTGate(Behavioral)
port map(
inPort => s_andOut,
outPort => outPort
);
end Structural;

44
1ano/2semestre/lsd/pratica01/part2/NOTGate.bsf Normal file
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@ -0,0 +1,44 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 168 96)
(text "NOTGate" (rect 5 0 43 12)(font "Arial" ))
(text "inst" (rect 8 64 20 76)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "inPort" (rect 0 0 22 12)(font "Arial" ))
(text "inPort" (rect 21 27 43 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
(pt 152 32)
(output)
(text "outPort" (rect 0 0 28 12)(font "Arial" ))
(text "outPort" (rect 103 27 131 39)(font "Arial" ))
(line (pt 152 32)(pt 136 32)(line_width 1))
)
(drawing
(rectangle (rect 16 16 136 64)(line_width 1))
)
)

14
1ano/2semestre/lsd/pratica01/part2/NOTGate.vhd Normal file
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@ -0,0 +1,14 @@
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity NOTGate is
port (
inPort : in std_logic;
outPort : out std_logic
);
end NOTGate;
architecture Behavioral of NOTGate is
begin
outPort <= not inPort;
end Behavioral;

BIN
1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.sof Normal file
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Binary file not shown.

246
1ano/2semestre/lsd/pratica01/part3/LogicTop.bdf Normal file
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@ -0,0 +1,246 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "graphic" (version "1.4"))
(pin
(input)
(rect 264 208 432 224)
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
(text "SW[0]" (rect 5 0 39 13)(font "Intel Clear" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
)
(pin
(input)
(rect 264 224 432 240)
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
(text "SW[1]" (rect 5 0 39 13)(font "Intel Clear" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
)
(pin
(output)
(rect 608 224 784 240)
(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
(text "LEDR[1]" (rect 90 0 132 13)(font "Intel Clear" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
(line (pt 52 4)(pt 78 4))
(line (pt 52 12)(pt 78 12))
(line (pt 52 12)(pt 52 4))
(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
)
(pin
(output)
(rect 608 240 784 256)
(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
(text "LEDR[2]" (rect 90 0 132 13)(font "Intel Clear" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
(line (pt 52 4)(pt 78 4))
(line (pt 52 12)(pt 78 12))
(line (pt 52 12)(pt 52 4))
(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
)
(pin
(output)
(rect 608 208 784 224)
(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
(text "LEDR[0]" (rect 90 0 132 11)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
(line (pt 52 4)(pt 78 4))
(line (pt 52 12)(pt 78 12))
(line (pt 52 12)(pt 52 4))
(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
)
(pin
(output)
(rect 608 256 784 272)
(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
(text "LEDR[3]" (rect 90 0 132 13)(font "Intel Clear" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
(line (pt 52 4)(pt 78 4))
(line (pt 52 12)(pt 78 12))
(line (pt 52 12)(pt 52 4))
(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
)
(pin
(output)
(rect 608 272 784 288)
(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
(text "LEDR[4]" (rect 90 0 132 13)(font "Intel Clear" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
(line (pt 52 4)(pt 78 4))
(line (pt 52 12)(pt 78 12))
(line (pt 52 12)(pt 52 4))
(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
)
(pin
(output)
(rect 608 288 784 304)
(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
(text "LEDR[5]" (rect 90 0 132 13)(font "Intel Clear" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
(line (pt 52 4)(pt 78 4))
(line (pt 52 12)(pt 78 12))
(line (pt 52 12)(pt 52 4))
(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
)
(symbol
(rect 440 184 600 328)
(text "LogicUnit" (rect 5 0 52 11)(font "Arial" ))
(text "inst" (rect 8 128 26 139)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "input0" (rect 0 0 31 11)(font "Arial" ))
(text "input0" (rect 21 27 52 38)(font "Arial" ))
(line (pt 0 32)(pt 16 32))
)
(port
(pt 0 48)
(input)
(text "input1" (rect 0 0 31 11)(font "Arial" ))
(text "input1" (rect 21 43 52 54)(font "Arial" ))
(line (pt 0 48)(pt 16 48))
)
(port
(pt 160 32)
(output)
(text "invOut" (rect 0 0 33 11)(font "Arial" ))
(text "invOut" (rect 112 27 145 38)(font "Arial" ))
(line (pt 160 32)(pt 144 32))
)
(port
(pt 160 48)
(output)
(text "andOut" (rect 0 0 37 11)(font "Arial" ))
(text "andOut" (rect 108 43 145 54)(font "Arial" ))
(line (pt 160 48)(pt 144 48))
)
(port
(pt 160 64)
(output)
(text "orOut" (rect 0 0 29 11)(font "Arial" ))
(text "orOut" (rect 115 59 144 70)(font "Arial" ))
(line (pt 160 64)(pt 144 64))
)
(port
(pt 160 80)
(output)
(text "xorOut" (rect 0 0 34 11)(font "Arial" ))
(text "xorOut" (rect 111 75 145 86)(font "Arial" ))
(line (pt 160 80)(pt 144 80))
)
(port
(pt 160 96)
(output)
(text "nandOut" (rect 0 0 43 11)(font "Arial" ))
(text "nandOut" (rect 103 91 146 102)(font "Arial" ))
(line (pt 160 96)(pt 144 96))
)
(port
(pt 160 112)
(output)
(text "norOut" (rect 0 0 35 11)(font "Arial" ))
(text "norOut" (rect 110 107 145 118)(font "Arial" ))
(line (pt 160 112)(pt 144 112))
)
(drawing
(rectangle (rect 16 16 144 128))
)
)
(connector
(pt 432 216)
(pt 440 216)
)
(connector
(pt 432 232)
(pt 440 232)
)
(connector
(pt 600 216)
(pt 608 216)
)
(connector
(pt 600 232)
(pt 608 232)
)
(connector
(pt 600 248)
(pt 608 248)
)
(connector
(pt 600 264)
(pt 608 264)
)
(connector
(pt 600 280)
(pt 608 280)
)
(connector
(pt 600 296)
(pt 608 296)
)

86
1ano/2semestre/lsd/pratica01/part3/LogicUnit.bsf Normal file
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@ -0,0 +1,86 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 176 160)
(text "LogicUnit" (rect 5 0 41 12)(font "Arial" ))
(text "inst" (rect 8 128 20 140)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "input0" (rect 0 0 22 12)(font "Arial" ))
(text "input0" (rect 21 27 43 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
(pt 0 48)
(input)
(text "input1" (rect 0 0 21 12)(font "Arial" ))
(text "input1" (rect 21 43 42 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48)(line_width 1))
)
(port
(pt 160 32)
(output)
(text "invOut" (rect 0 0 25 12)(font "Arial" ))
(text "invOut" (rect 114 27 139 39)(font "Arial" ))
(line (pt 160 32)(pt 144 32)(line_width 1))
)
(port
(pt 160 48)
(output)
(text "andOut" (rect 0 0 28 12)(font "Arial" ))
(text "andOut" (rect 111 43 139 55)(font "Arial" ))
(line (pt 160 48)(pt 144 48)(line_width 1))
)
(port
(pt 160 64)
(output)
(text "orOut" (rect 0 0 22 12)(font "Arial" ))
(text "orOut" (rect 117 59 139 71)(font "Arial" ))
(line (pt 160 64)(pt 144 64)(line_width 1))
)
(port
(pt 160 80)
(output)
(text "xorOut" (rect 0 0 27 12)(font "Arial" ))
(text "xorOut" (rect 112 75 139 87)(font "Arial" ))
(line (pt 160 80)(pt 144 80)(line_width 1))
)
(port
(pt 160 96)
(output)
(text "nandOut" (rect 0 0 33 12)(font "Arial" ))
(text "nandOut" (rect 106 91 139 103)(font "Arial" ))
(line (pt 160 96)(pt 144 96)(line_width 1))
)
(port
(pt 160 112)
(output)
(text "norOut" (rect 0 0 27 12)(font "Arial" ))
(text "norOut" (rect 112 107 139 119)(font "Arial" ))
(line (pt 160 112)(pt 144 112)(line_width 1))
)
(drawing
(rectangle (rect 16 16 144 128)(line_width 1))
)
)

26
1ano/2semestre/lsd/pratica01/part3/LogicUnit.vhd Normal file
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@ -0,0 +1,26 @@
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity LogicUnit is
port
(
input0 : in std_logic;
input1 : in std_logic;
invOut : out std_logic;
andOut : out std_logic;
orOut : out std_logic;
xorOut : out std_logic;
nandOut : out std_logic;
norOut : out std_logic
);
end LogicUnit;
architecture Behavioral of LogicUnit is
begin
invOut <= not input0;
andOut <= input0 and input1;
orOut <= input0 or input1;
xorOut <= input0 xor input1;
nandOut <= input0 nand input1;
norOut <= input0 nor input1;
end Behavioral;

368
1ano/2semestre/lsd/pratica01/part3/LogicUnit.vwf Normal file
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@ -0,0 +1,368 @@
/*<simulation_settings>
<ftestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off LogicDemo -c LogicTop --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/LogicUnit.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicUnit.vwf.vht"</ftestbench_cmd>
<ttestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off LogicDemo -c LogicTop --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/LogicUnit.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicUnit.vwf.vht"</ttestbench_cmd>
<fnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/" LogicDemo -c LogicTop</fnetlist_cmd>
<tnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/" LogicDemo -c LogicTop</tnetlist_cmd>
<modelsim_script>onerror {exit -code 1}
vlib work
vcom -work work LogicTop.vho
vcom -work work LogicUnit.vwf.vht
vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.LogicTop_vhd_vec_tst
vcd file -direction LogicDemo.msim.vcd
vcd add -internal LogicTop_vhd_vec_tst/*
vcd add -internal LogicTop_vhd_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script>
<modelsim_script_timing>onerror {exit -code 1}
vlib work
vcom -work work LogicTop.vho
vcom -work work LogicUnit.vwf.vht
vsim -novopt -c -t 1ps -sdfmax LogicTop_vhd_vec_tst/i1=LogicTop_vhd.sdo -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.LogicTop_vhd_vec_tst
vcd file -direction LogicDemo.msim.vcd
vcd add -internal LogicTop_vhd_vec_tst/*
vcd add -internal LogicTop_vhd_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script_timing>
<hdl_lang>vhdl</hdl_lang>
</simulation_settings>*/
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
HEADER
{
VERSION = 1;
TIME_UNIT = ns;
DATA_OFFSET = 0.0;
DATA_DURATION = 1000.0;
SIMULATION_TIME = 0.0;
GRID_PHASE = 0.0;
GRID_PERIOD = 10.0;
GRID_DUTY_CYCLE = 50;
}
SIGNAL("LEDR")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = BUS;
WIDTH = 6;
LSB_INDEX = 0;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("LEDR[5]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "LEDR";
}
SIGNAL("LEDR[4]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "LEDR";
}
SIGNAL("LEDR[3]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "LEDR";
}
SIGNAL("LEDR[2]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "LEDR";
}
SIGNAL("LEDR[1]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "LEDR";
}
SIGNAL("LEDR[0]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "LEDR";
}
SIGNAL("SW")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = BUS;
WIDTH = 2;
LSB_INDEX = 0;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("SW[1]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "SW";
}
SIGNAL("SW[0]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "SW";
}
TRANSITION_LIST("LEDR[5]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("LEDR[4]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("LEDR[3]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("LEDR[2]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("LEDR[1]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("LEDR[0]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("SW[1]")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 1;
LEVEL 0 FOR 400.0;
LEVEL 1 FOR 400.0;
}
LEVEL 0 FOR 200.0;
}
}
TRANSITION_LIST("SW[0]")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 2;
LEVEL 0 FOR 200.0;
LEVEL 1 FOR 200.0;
}
LEVEL 0 FOR 200.0;
}
}
DISPLAY_LINE
{
CHANNEL = "SW";
EXPAND_STATUS = EXPANDED;
RADIX = Binary;
TREE_INDEX = 0;
TREE_LEVEL = 0;
CHILDREN = 1, 2;
}
DISPLAY_LINE
{
CHANNEL = "SW[1]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 1;
TREE_LEVEL = 1;
PARENT = 0;
}
DISPLAY_LINE
{
CHANNEL = "SW[0]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 2;
TREE_LEVEL = 1;
PARENT = 0;
}
DISPLAY_LINE
{
CHANNEL = "LEDR";
EXPAND_STATUS = EXPANDED;
RADIX = Binary;
TREE_INDEX = 3;
TREE_LEVEL = 0;
CHILDREN = 4, 5, 6, 7, 8, 9;
}
DISPLAY_LINE
{
CHANNEL = "LEDR[5]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 4;
TREE_LEVEL = 1;
PARENT = 3;
}
DISPLAY_LINE
{
CHANNEL = "LEDR[4]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 5;
TREE_LEVEL = 1;
PARENT = 3;
}
DISPLAY_LINE
{
CHANNEL = "LEDR[3]";
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PARENT = 3;
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TREE_INDEX = 7;
TREE_LEVEL = 1;
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}
DISPLAY_LINE
{
CHANNEL = "LEDR[1]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 8;
TREE_LEVEL = 1;
PARENT = 3;
}
DISPLAY_LINE
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CHANNEL = "LEDR[0]";
EXPAND_STATUS = COLLAPSED;
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TREE_INDEX = 9;
TREE_LEVEL = 1;
PARENT = 3;
}
TIME_BAR
{
TIME = 0;
MASTER = TRUE;
}
;

BIN
1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.sof Normal file
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383
1ano/2semestre/lsd/pratica01/part4/EqCmp4.bdf Normal file
View File

@ -0,0 +1,383 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
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(rect 600 296 776 312)
(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
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(symbol
(rect 424 184 472 248)
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(text "xnor_1" (rect 2 1 15 36)(font "Intel Clear" )(vertical))
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(text "IN1" (rect 2 8 23 19)(font "Courier New" (bold))(invisible))
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(line (pt 32 0)(pt 32 11))
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(text "IN2" (rect 2 23 23 34)(font "Courier New" (bold))(invisible))
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(port
(pt 24 64)
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(text "OUT" (rect 48 15 69 26)(font "Courier New" (bold))(invisible))
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(line (pt 24 56)(pt 24 64))
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(drawing
(line (pt 35 14)(pt 35 25))
(line (pt 12 14)(pt 12 25))
(arc (pt 19 7)(pt 29 7)(rect 7 -14 40 19))
(arc (pt 24 49)(pt 35 25)(rect -28 -6 35 57))
(arc (pt 19 2)(pt 29 2)(rect 7 -19 40 14))
(arc (pt 13 25)(pt 24 49)(rect 12 -6 75 57))
(circle (rect 20 48 28 56))
)
(rotate270)
)
(symbol
(rect 360 184 408 248)
(text "XNOR" (rect 38 1 48 30)(font "Arial" (font_size 6))(vertical))
(text "xnor_2" (rect 2 1 15 36)(font "Intel Clear" )(vertical))
(port
(pt 32 0)
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(text "IN1" (rect 2 8 23 19)(font "Courier New" (bold))(invisible))
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(line (pt 32 0)(pt 32 11))
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(pt 16 0)
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(text "IN2" (rect 2 23 23 34)(font "Courier New" (bold))(invisible))
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(line (pt 16 0)(pt 16 11))
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(port
(pt 24 64)
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(text "OUT" (rect 48 15 69 26)(font "Courier New" (bold))(invisible))
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(drawing
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)
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(pt 504 184)
(pt 504 160)
)
(connector
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(pt 520 136)
(bus)
)
(connector
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(pt 456 136)
(bus)
)
(connector
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(pt 328 136)
(bus)
)
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(bus)
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(pt 520 184)
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)
(junction (pt 312 160))
(junction (pt 376 160))
(junction (pt 440 160))
(junction (pt 456 136))
(junction (pt 392 136))
(junction (pt 328 136))

51
1ano/2semestre/lsd/pratica01/part4/EqCmp4.bsf Normal file
View File

@ -0,0 +1,51 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "symbol" (version "1.2"))
(symbol
(rect 16 16 184 112)
(text "EqCmp4" (rect 5 0 55 15)(font "Intel Clear" (font_size 8)))
(text "inst" (rect 8 79 28 92)(font "Intel Clear" ))
(port
(pt 0 32)
(input)
(text "input0[3..0]" (rect 0 0 67 15)(font "Intel Clear" (font_size 8)))
(text "input0[3..0]" (rect 21 27 88 42)(font "Intel Clear" (font_size 8)))
(line (pt 0 32)(pt 16 32)(line_width 3))
)
(port
(pt 0 48)
(input)
(text "input1[3..0]" (rect 0 0 67 15)(font "Intel Clear" (font_size 8)))
(text "input1[3..0]" (rect 21 43 88 58)(font "Intel Clear" (font_size 8)))
(line (pt 0 48)(pt 16 48)(line_width 3))
)
(port
(pt 168 32)
(output)
(text "cmpOut" (rect 0 0 47 15)(font "Intel Clear" (font_size 8)))
(text "cmpOut" (rect 100 27 147 42)(font "Intel Clear" (font_size 8)))
(line (pt 168 32)(pt 152 32))
)
(drawing
(rectangle (rect 16 16 152 80))
)
)

435
1ano/2semestre/lsd/pratica01/part4/EqCmp4.vwf Normal file
View File

@ -0,0 +1,435 @@
/*<simulation_settings>
<ftestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off EqCmpDemo -c EqCmpDemo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmp4.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmp4.vwf.vht"</ftestbench_cmd>
<ttestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off EqCmpDemo -c EqCmpDemo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmp4.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmp4.vwf.vht"</ttestbench_cmd>
<fnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/" EqCmpDemo -c EqCmpDemo</fnetlist_cmd>
<tnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/" EqCmpDemo -c EqCmpDemo</tnetlist_cmd>
<modelsim_script>onerror {exit -code 1}
vlib work
vcom -work work EqCmpDemo.vho
vcom -work work EqCmp4.vwf.vht
vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.EqCmpDemo_vhd_vec_tst
vcd file -direction EqCmpDemo.msim.vcd
vcd add -internal EqCmpDemo_vhd_vec_tst/*
vcd add -internal EqCmpDemo_vhd_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script>
<modelsim_script_timing>onerror {exit -code 1}
vlib work
vcom -work work EqCmpDemo.vho
vcom -work work EqCmp4.vwf.vht
vsim -novopt -c -t 1ps -sdfmax EqCmpDemo_vhd_vec_tst/i1=EqCmpDemo_vhd.sdo -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.EqCmpDemo_vhd_vec_tst
vcd file -direction EqCmpDemo.msim.vcd
vcd add -internal EqCmpDemo_vhd_vec_tst/*
vcd add -internal EqCmpDemo_vhd_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script_timing>
<hdl_lang>vhdl</hdl_lang>
</simulation_settings>*/
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
HEADER
{
VERSION = 1;
TIME_UNIT = ns;
DATA_OFFSET = 0.0;
DATA_DURATION = 1000.0;
SIMULATION_TIME = 0.0;
GRID_PHASE = 0.0;
GRID_PERIOD = 10.0;
GRID_DUTY_CYCLE = 50;
}
SIGNAL("LEDG")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("LEDG[0]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("SW")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = BUS;
WIDTH = 8;
LSB_INDEX = 0;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("SW[7]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "SW";
}
SIGNAL("SW[6]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "SW";
}
SIGNAL("SW[5]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "SW";
}
SIGNAL("SW[4]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "SW";
}
SIGNAL("SW[3]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "SW";
}
SIGNAL("SW[2]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "SW";
}
SIGNAL("SW[1]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "SW";
}
SIGNAL("SW[0]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "SW";
}
TRANSITION_LIST("LEDG")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("LEDG[0]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("SW[7]")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 1;
LEVEL 0 FOR 400.0;
LEVEL 1 FOR 400.0;
}
LEVEL 0 FOR 200.0;
}
}
TRANSITION_LIST("SW[6]")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 2;
LEVEL 0 FOR 200.0;
LEVEL 1 FOR 200.0;
}
LEVEL 0 FOR 200.0;
}
}
TRANSITION_LIST("SW[5]")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 5;
LEVEL 0 FOR 100.0;
LEVEL 1 FOR 100.0;
}
}
}
TRANSITION_LIST("SW[4]")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 10;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
}
}
}
TRANSITION_LIST("SW[3]")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 20;
LEVEL 0 FOR 25.0;
LEVEL 1 FOR 25.0;
}
}
}
TRANSITION_LIST("SW[2]")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 40;
LEVEL 0 FOR 12.5;
LEVEL 1 FOR 12.5;
}
}
}
TRANSITION_LIST("SW[1]")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 80;
LEVEL 0 FOR 6.25;
LEVEL 1 FOR 6.25;
}
}
}
TRANSITION_LIST("SW[0]")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 148;
LEVEL 0 FOR 3.375;
LEVEL 1 FOR 3.375;
}
LEVEL 0 FOR 1.0;
}
}
DISPLAY_LINE
{
CHANNEL = "SW";
EXPAND_STATUS = EXPANDED;
RADIX = Binary;
TREE_INDEX = 0;
TREE_LEVEL = 0;
CHILDREN = 1, 2, 3, 4, 5, 6, 7, 8;
}
DISPLAY_LINE
{
CHANNEL = "SW[7]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 1;
TREE_LEVEL = 1;
PARENT = 0;
}
DISPLAY_LINE
{
CHANNEL = "SW[6]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 2;
TREE_LEVEL = 1;
PARENT = 0;
}
DISPLAY_LINE
{
CHANNEL = "SW[5]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 3;
TREE_LEVEL = 1;
PARENT = 0;
}
DISPLAY_LINE
{
CHANNEL = "SW[4]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 4;
TREE_LEVEL = 1;
PARENT = 0;
}
DISPLAY_LINE
{
CHANNEL = "SW[3]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 5;
TREE_LEVEL = 1;
PARENT = 0;
}
DISPLAY_LINE
{
CHANNEL = "SW[2]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 6;
TREE_LEVEL = 1;
PARENT = 0;
}
DISPLAY_LINE
{
CHANNEL = "SW[1]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 7;
TREE_LEVEL = 1;
PARENT = 0;
}
DISPLAY_LINE
{
CHANNEL = "SW[0]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 8;
TREE_LEVEL = 1;
PARENT = 0;
}
DISPLAY_LINE
{
CHANNEL = "LEDG";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 9;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "LEDG[0]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 10;
TREE_LEVEL = 0;
}
TIME_BAR
{
TIME = 0;
MASTER = TRUE;
}
;

51
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@ -0,0 +1,51 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 192 96)
(text "EqCmp8" (rect 5 0 41 12)(font "Arial" ))
(text "inst" (rect 8 64 20 76)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "input0[7..0]" (rect 0 0 42 12)(font "Arial" ))
(text "input0[7..0]" (rect 21 27 63 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 3))
)
(port
(pt 0 48)
(input)
(text "input1[7..0]" (rect 0 0 41 12)(font "Arial" ))
(text "input1[7..0]" (rect 21 43 62 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48)(line_width 3))
)
(port
(pt 176 32)
(output)
(text "cmpOut" (rect 0 0 31 12)(font "Arial" ))
(text "cmpOut" (rect 124 27 155 39)(font "Arial" ))
(line (pt 176 32)(pt 160 32)(line_width 1))
)
(drawing
(rectangle (rect 16 16 160 64)(line_width 1))
)
)

16
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@ -0,0 +1,16 @@
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity EqCmp8 is
port
(
input0 : in std_logic_vector(7 downto 0);
input1 : in std_logic_vector(7 downto 0);
cmpOut : out std_logic
);
end EqCmp8;
architecture Behavioral of EqCmp8 is
begin
cmpOut <= '1' when (input0 = input1) else '0';
end Behavioral;

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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "graphic" (version "1.4"))
(pin
(input)
(rect 296 200 464 216)
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
(text "SW[3..0]" (rect 5 0 49 13)(font "Intel Clear" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
(annotation_block (location)(rect 232 216 296 232))
)
(pin
(input)
(rect 296 216 464 232)
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
(text "SW[7..4]" (rect 5 0 49 13)(font "Intel Clear" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
(annotation_block (location)(rect 232 232 296 248))
)
(pin
(output)
(rect 656 200 832 216)
(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
(text "LEDG[0]" (rect 90 0 132 11)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
(line (pt 52 4)(pt 78 4))
(line (pt 52 12)(pt 78 12))
(line (pt 52 12)(pt 52 4))
(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
(annotation_block (location)(rect 832 216 888 232))
)
(symbol
(rect 472 176 640 272)
(text "EqCmp4" (rect 5 0 55 15)(font "Intel Clear" (font_size 8)))
(text "inst1" (rect 8 79 32 92)(font "Intel Clear" ))
(port
(pt 0 32)
(input)
(text "input0[3..0]" (rect 0 0 67 15)(font "Intel Clear" (font_size 8)))
(text "input0[3..0]" (rect 21 27 88 42)(font "Intel Clear" (font_size 8)))
(line (pt 0 32)(pt 16 32)(line_width 3))
)
(port
(pt 0 48)
(input)
(text "input1[3..0]" (rect 0 0 67 15)(font "Intel Clear" (font_size 8)))
(text "input1[3..0]" (rect 21 43 88 58)(font "Intel Clear" (font_size 8)))
(line (pt 0 48)(pt 16 48)(line_width 3))
)
(port
(pt 168 32)
(output)
(text "cmpOut" (rect 0 0 47 15)(font "Intel Clear" (font_size 8)))
(text "cmpOut" (rect 100 27 147 42)(font "Intel Clear" (font_size 8)))
(line (pt 168 32)(pt 152 32))
)
(drawing
(rectangle (rect 16 16 152 80))
)
)
(connector
(pt 464 208)
(pt 472 208)
(bus)
)
(connector
(pt 464 224)
(pt 472 224)
(bus)
)
(connector
(pt 656 208)
(pt 640 208)
)

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1ano/2semestre/lsd/pratica02/DisplayDemo/Bin7SegDecoder.bsf Normal file
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@ -0,0 +1,51 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 224 96)
(text "Bin7SegDecoder" (rect 5 0 71 12)(font "Arial" ))
(text "inst" (rect 8 64 20 76)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "binInput[3..0]" (rect 0 0 49 12)(font "Arial" ))
(text "binInput[3..0]" (rect 21 27 70 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 3))
)
(port
(pt 0 48)
(input)
(text "enable" (rect 0 0 24 12)(font "Arial" ))
(text "enable" (rect 21 43 45 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48)(line_width 1))
)
(port
(pt 208 32)
(output)
(text "decOut_n[6..0]" (rect 0 0 59 12)(font "Arial" ))
(text "decOut_n[6..0]" (rect 128 27 187 39)(font "Arial" ))
(line (pt 208 32)(pt 192 32)(line_width 3))
)
(drawing
(rectangle (rect 16 16 192 64)(line_width 1))
)
)

32
1ano/2semestre/lsd/pratica02/DisplayDemo/Bin7SegDecoder.vhd Normal file
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library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Bin7SegDecoder is
port
(
binInput : in std_logic_vector(3 downto 0);
enable : in std_logic;
decOut_n : out std_logic_vector(6 downto 0)
);
end Bin7SegDecoder;
architecture Behavioral of Bin7SegDecoder is
begin
decOut_n <= "1111111" when (enable = '1') else --disabled by default
"1111001" when (binInput = "0001") else --1
"0100100" when (binInput = "0010") else --2
"0110000" when (binInput = "0011") else --3
"0011001" when (binInput = "0100") else --4
"0010010" when (binInput = "0101") else --5
"0000010" when (binInput = "0110") else --6
"1111000" when (binInput = "0111") else --7
"0000000" when (binInput = "1000") else --8
"0010000" when (binInput = "1001") else --9
"0001000" when (binInput = "1010") else --A
"0000011" when (binInput = "1011") else --b
"1000110" when (binInput = "1100") else --C
"0100001" when (binInput = "1101") else --d
"0000110" when (binInput = "1110") else --E
"0001110" when (binInput = "1111") else --F
"1000000"; --0
end Behavioral;

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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "graphic" (version "1.4"))
(pin
(input)
(rect 360 304 528 320)
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
(text "SW[3..0]" (rect 5 0 48 11)(font "Arial" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
(annotation_block (location)(rect 296 320 360 336))
)
(pin
(input)
(rect 360 320 528 336)
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
(text "KEY[0]" (rect 5 0 40 11)(font "Arial" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
(annotation_block (location)(rect 296 336 360 352))
)
(pin
(output)
(rect 544 264 720 280)
(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
(text "LEDG[3..0]" (rect 90 0 145 11)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
(line (pt 52 4)(pt 78 4))
(line (pt 52 12)(pt 78 12))
(line (pt 52 12)(pt 52 4))
(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
(annotation_block (location)(rect 720 280 776 296))
)
(pin
(output)
(rect 768 312 944 328)
(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
(text "LEDR[6..0]" (rect 90 0 143 13)(font "Intel Clear" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
(line (pt 52 4)(pt 78 4))
(line (pt 52 12)(pt 78 12))
(line (pt 52 12)(pt 52 4))
(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
(annotation_block (location)(rect 944 328 1008 344))
)
(pin
(output)
(rect 768 296 944 312)
(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
(text "HEX0[6..0]" (rect 90 0 144 13)(font "Intel Clear" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
(line (pt 52 4)(pt 78 4))
(line (pt 52 12)(pt 78 12))
(line (pt 52 12)(pt 52 4))
(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
(annotation_block (location)(rect 944 312 1008 328))
)
(symbol
(rect 544 280 752 360)
(text "Bin7SegDecoder" (rect 5 0 89 11)(font "Arial" ))
(text "inst" (rect 8 64 26 75)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "binInput[3..0]" (rect 0 0 63 11)(font "Arial" ))
(text "binInput[3..0]" (rect 21 27 84 38)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 3))
)
(port
(pt 0 48)
(input)
(text "enable" (rect 0 0 34 11)(font "Arial" ))
(text "enable" (rect 21 43 55 54)(font "Arial" ))
(line (pt 0 48)(pt 16 48))
)
(port
(pt 208 32)
(output)
(text "decOut_n[6..0]" (rect 0 0 73 11)(font "Arial" ))
(text "decOut_n[6..0]" (rect 126 27 199 38)(font "Arial" ))
(line (pt 208 32)(pt 192 32)(line_width 3))
)
(drawing
(rectangle (rect 16 16 192 64))
)
)
(connector
(pt 768 320)
(pt 760 320)
(bus)
)
(connector
(pt 760 304)
(pt 768 304)
(bus)
)
(connector
(pt 752 312)
(pt 760 312)
(bus)
)
(connector
(pt 760 320)
(pt 760 312)
(bus)
)
(connector
(pt 760 312)
(pt 760 304)
(bus)
)
(connector
(pt 536 272)
(pt 544 272)
(bus)
)
(connector
(pt 536 312)
(pt 536 272)
(bus)
)
(connector
(pt 528 312)
(pt 536 312)
(bus)
)
(connector
(pt 536 312)
(pt 544 312)
(bus)
)
(connector
(pt 544 328)
(pt 528 328)
)
(junction (pt 760 312))
(junction (pt 536 312))

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1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/Bin7SegDecoder.vhd Normal file
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library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Bin7SegDecoder is
port
(
binInput : in std_logic_vector(3 downto 0);
enable : in std_logic;
decOut_n : out std_logic_vector(6 downto 0)
);
end Bin7SegDecoder;
architecture Behavioral of Bin7SegDecoder is
begin
decOut_n <= "1111111" when (enable = '1') else --disabled by default
"1111001" when (binInput = "0001") else --1
"0100100" when (binInput = "0010") else --2
"0110000" when (binInput = "0011") else --3
"0011001" when (binInput = "0100") else --4
"0010010" when (binInput = "0101") else --5
"0000010" when (binInput = "0110") else --6
"1111000" when (binInput = "0111") else --7
"0000000" when (binInput = "1000") else --8
"0010000" when (binInput = "1001") else --9
"0001000" when (binInput = "1010") else --A
"0000011" when (binInput = "1011") else --b
"1000110" when (binInput = "1100") else --C
"0100001" when (binInput = "1101") else --d
"0000110" when (binInput = "1110") else --E
"0001110" when (binInput = "1111") else --F
"1000000"; --0
end Behavioral;

28
1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/DisplayDemoVHDL.vhd Normal file
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library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity DisplayDemoVHDL is
port
(
SW : in std_logic_vector(3 downto 0);
KEY : in std_logic_vector(1 downto 0);
LEDG : out std_logic_vector(3 downto 0);
LEDR : out std_logic_vector(6 downto 0);
HEX0 : out std_logic_vector(6 downto 0)
);
end DisplayDemoVHDL;
architecture Shell of DisplayDemoVHDL is
signal s_decOut : std_logic_vector(6 downto 0);
begin
system_core : entity work.Bin7SegDecoder(Behavioral)
port map
(
binInput => SW,
enable => KEY(0),
decOut_n => s_decOut
);
HEX0 <= s_decOut;
LEDR <= s_decOut;
LEDG <= SW;
end Shell;

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1ano/2semestre/lsd/pratica02/LSD_2022-22_TrabPrat02.pdf Normal file
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1ano/2semestre/lsd/pratica02/Mux2_1Demo/Mux2_1.bsf Normal file
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 176 128)
(text "Mux2_1" (rect 5 0 36 12)(font "Arial" ))
(text "inst" (rect 8 96 20 108)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "dataIn0" (rect 0 0 28 12)(font "Arial" ))
(text "dataIn0" (rect 21 27 49 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
(pt 0 48)
(input)
(text "dataIn1" (rect 0 0 27 12)(font "Arial" ))
(text "dataIn1" (rect 21 43 48 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48)(line_width 1))
)
(port
(pt 0 64)
(input)
(text "sel" (rect 0 0 10 12)(font "Arial" ))
(text "sel" (rect 21 59 31 71)(font "Arial" ))
(line (pt 0 64)(pt 16 64)(line_width 1))
)
(port
(pt 160 32)
(output)
(text "dataOut" (rect 0 0 30 12)(font "Arial" ))
(text "dataOut" (rect 109 27 139 39)(font "Arial" ))
(line (pt 160 32)(pt 144 32)(line_width 1))
)
(drawing
(rectangle (rect 16 16 144 96)(line_width 1))
)
)

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1ano/2semestre/lsd/pratica02/Mux2_1Demo/Mux2_1.vhd Normal file
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library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Mux2_1 is
port
(
dataIn0 : in std_logic;
dataIn1 : in std_logic;
sel : in std_logic;
dataOut : out std_logic
);
end Mux2_1;
architecture Behavioral of Mux2_1 is
begin
process(dataIn0, dataIn1, sel)
begin
if (sel = '0') then
dataOut <= dataIn0;
else
dataOut <= dataIn1;
end if;
end process;
end Behavioral;

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/*<simulation_settings>
<ftestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off Mux2_1Demo -c Mux2_1Demo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/Mux2_1.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/simulation/qsim/Mux2_1.vwf.vht"</ftestbench_cmd>
<ttestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off Mux2_1Demo -c Mux2_1Demo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/Mux2_1.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/simulation/qsim/Mux2_1.vwf.vht"</ttestbench_cmd>
<fnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/simulation/qsim/" Mux2_1Demo -c Mux2_1Demo</fnetlist_cmd>
<tnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/simulation/qsim/" Mux2_1Demo -c Mux2_1Demo</tnetlist_cmd>
<modelsim_script>onerror {exit -code 1}
vlib work
vcom -work work Mux2_1Demo.vho
vcom -work work Mux2_1.vwf.vht
vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.Mux2_1Demo_vhd_vec_tst
vcd file -direction Mux2_1Demo.msim.vcd
vcd add -internal Mux2_1Demo_vhd_vec_tst/*
vcd add -internal Mux2_1Demo_vhd_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script>
<modelsim_script_timing>onerror {exit -code 1}
vlib work
vcom -work work Mux2_1Demo.vho
vcom -work work Mux2_1.vwf.vht
vsim -novopt -c -t 1ps -sdfmax Mux2_1Demo_vhd_vec_tst/i1=Mux2_1Demo_vhd.sdo -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.Mux2_1Demo_vhd_vec_tst
vcd file -direction Mux2_1Demo.msim.vcd
vcd add -internal Mux2_1Demo_vhd_vec_tst/*
vcd add -internal Mux2_1Demo_vhd_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script_timing>
<hdl_lang>vhdl</hdl_lang>
</simulation_settings>*/
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
HEADER
{
VERSION = 1;
TIME_UNIT = ns;
DATA_OFFSET = 0.0;
DATA_DURATION = 1000.0;
SIMULATION_TIME = 0.0;
GRID_PHASE = 0.0;
GRID_PERIOD = 10.0;
GRID_DUTY_CYCLE = 50;
}
SIGNAL("dataIn0")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("dataIn1")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("dataOut")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("sel")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
TRANSITION_LIST("dataIn0")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 2;
LEVEL 0 FOR 200.0;
LEVEL 1 FOR 200.0;
}
LEVEL 0 FOR 200.0;
}
}
TRANSITION_LIST("dataIn1")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 5;
LEVEL 0 FOR 100.0;
LEVEL 1 FOR 100.0;
}
}
}
TRANSITION_LIST("dataOut")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("sel")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 1;
LEVEL 0 FOR 400.0;
LEVEL 1 FOR 400.0;
}
LEVEL 0 FOR 200.0;
}
}
DISPLAY_LINE
{
CHANNEL = "dataIn0";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 0;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "dataIn1";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 1;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "sel";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 2;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "dataOut";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 3;
TREE_LEVEL = 0;
}
TIME_BAR
{
TIME = 0;
MASTER = TRUE;
}
;

138
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@ -0,0 +1,138 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "graphic" (version "1.4"))
(pin
(input)
(rect 304 248 472 264)
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
(text "KEY[0]" (rect 5 0 40 13)(font "Intel Clear" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
)
(pin
(input)
(rect 304 216 472 232)
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
(text "SW[0]" (rect 5 0 39 13)(font "Intel Clear" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
)
(pin
(input)
(rect 304 232 472 248)
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
(text "SW[1]" (rect 5 0 39 13)(font "Intel Clear" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
)
(pin
(output)
(rect 648 216 824 232)
(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
(text "LEDG[0]" (rect 90 0 132 11)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
(line (pt 52 4)(pt 78 4))
(line (pt 52 12)(pt 78 12))
(line (pt 52 12)(pt 52 4))
(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
)
(symbol
(rect 480 192 640 304)
(text "Mux2_1" (rect 5 0 46 11)(font "Arial" ))
(text "inst" (rect 8 96 26 107)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "dataIn0" (rect 0 0 38 11)(font "Arial" ))
(text "dataIn0" (rect 21 27 59 38)(font "Arial" ))
(line (pt 0 32)(pt 16 32))
)
(port
(pt 0 48)
(input)
(text "dataIn1" (rect 0 0 38 11)(font "Arial" ))
(text "dataIn1" (rect 21 43 59 54)(font "Arial" ))
(line (pt 0 48)(pt 16 48))
)
(port
(pt 0 64)
(input)
(text "sel" (rect 0 0 15 11)(font "Arial" ))
(text "sel" (rect 21 59 36 70)(font "Arial" ))
(line (pt 0 64)(pt 16 64))
)
(port
(pt 160 32)
(output)
(text "dataOut" (rect 0 0 41 11)(font "Arial" ))
(text "dataOut" (rect 105 27 146 38)(font "Arial" ))
(line (pt 160 32)(pt 144 32))
)
(drawing
(rectangle (rect 16 16 144 96))
)
)
(connector
(pt 480 224)
(pt 472 224)
)
(connector
(pt 480 240)
(pt 472 240)
)
(connector
(pt 480 256)
(pt 472 256)
)
(connector
(pt 648 224)
(pt 640 224)
)

BIN
1ano/2semestre/lsd/pratica02/Mux2_1Demo/output_files/Mux2_1Demo.sof Normal file
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Binary file not shown.

72
1ano/2semestre/lsd/pratica02/Mux4_1Demo/Mux4_1.bsf Normal file
View File

@ -0,0 +1,72 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 176 160)
(text "Mux4_1" (rect 5 0 38 12)(font "Arial" ))
(text "inst" (rect 8 128 20 140)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "dataIn3" (rect 0 0 28 12)(font "Arial" ))
(text "dataIn3" (rect 21 27 49 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
(pt 0 48)
(input)
(text "dataIn2" (rect 0 0 28 12)(font "Arial" ))
(text "dataIn2" (rect 21 43 49 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48)(line_width 1))
)
(port
(pt 0 64)
(input)
(text "dataIn1" (rect 0 0 27 12)(font "Arial" ))
(text "dataIn1" (rect 21 59 48 71)(font "Arial" ))
(line (pt 0 64)(pt 16 64)(line_width 1))
)
(port
(pt 0 80)
(input)
(text "dataIn0" (rect 0 0 28 12)(font "Arial" ))
(text "dataIn0" (rect 21 75 49 87)(font "Arial" ))
(line (pt 0 80)(pt 16 80)(line_width 1))
)
(port
(pt 0 96)
(input)
(text "sel[1..0]" (rect 0 0 29 12)(font "Arial" ))
(text "sel[1..0]" (rect 21 91 50 103)(font "Arial" ))
(line (pt 0 96)(pt 16 96)(line_width 3))
)
(port
(pt 160 32)
(output)
(text "dataOut" (rect 0 0 30 12)(font "Arial" ))
(text "dataOut" (rect 109 27 139 39)(font "Arial" ))
(line (pt 160 32)(pt 144 32)(line_width 1))
)
(drawing
(rectangle (rect 16 16 144 128)(line_width 1))
)
)

30
1ano/2semestre/lsd/pratica02/Mux4_1Demo/Mux4_1.vhd Normal file
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@ -0,0 +1,30 @@
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Mux4_1 is
port
(
dataIn3 : in std_logic;
dataIn2 : in std_logic;
dataIn1 : in std_logic;
dataIn0 : in std_logic;
sel : in std_logic_vector(1 downto 0);
dataOut : out std_logic
);
end Mux4_1;
architecture Behavioral of Mux4_1 is
begin
process (dataIn0, dataIn1, dataIn2, dataIn3, sel)
begin
if (sel = "00") then
dataOut <= dataIn0;
elsif (sel = "01") then
dataOut <= dataIn1;
elsif (sel = "10") then
dataOut <= dataIn2;
else
dataOut <= dataIn3;
end if;
end process;
end Behavioral;

334
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/*<simulation_settings>
<ftestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off Mux4_1Demo -c Mux4_1Demo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux4_1Demo/Mux4_1.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/qsim/Mux4_1.vwf.vht"</ftestbench_cmd>
<ttestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off Mux4_1Demo -c Mux4_1Demo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux4_1Demo/Mux4_1.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/qsim/Mux4_1.vwf.vht"</ttestbench_cmd>
<fnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/qsim/" Mux4_1Demo -c Mux4_1Demo</fnetlist_cmd>
<tnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux4_1Demo/simulation/qsim/" Mux4_1Demo -c Mux4_1Demo</tnetlist_cmd>
<modelsim_script>onerror {exit -code 1}
vlib work
vcom -work work Mux4_1Demo.vho
vcom -work work Mux4_1.vwf.vht
vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.Mux4_1_vhd_vec_tst
vcd file -direction Mux4_1Demo.msim.vcd
vcd add -internal Mux4_1_vhd_vec_tst/*
vcd add -internal Mux4_1_vhd_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script>
<modelsim_script_timing>onerror {exit -code 1}
vlib work
vcom -work work Mux4_1Demo.vho
vcom -work work Mux4_1.vwf.vht
vsim -novopt -c -t 1ps -sdfmax Mux4_1_vhd_vec_tst/i1=Mux4_1Demo_vhd.sdo -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.Mux4_1_vhd_vec_tst
vcd file -direction Mux4_1Demo.msim.vcd
vcd add -internal Mux4_1_vhd_vec_tst/*
vcd add -internal Mux4_1_vhd_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script_timing>
<hdl_lang>vhdl</hdl_lang>
</simulation_settings>*/
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
HEADER
{
VERSION = 1;
TIME_UNIT = ns;
DATA_OFFSET = 0.0;
DATA_DURATION = 1000.0;
SIMULATION_TIME = 0.0;
GRID_PHASE = 0.0;
GRID_PERIOD = 10.0;
GRID_DUTY_CYCLE = 50;
}
SIGNAL("dataIn0")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("dataIn1")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("dataIn2")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("dataIn3")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("dataOut")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("sel")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = BUS;
WIDTH = 2;
LSB_INDEX = 0;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("sel[1]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "sel";
}
SIGNAL("sel[0]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "sel";
}
TRANSITION_LIST("dataIn0")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 40;
LEVEL 0 FOR 12.5;
LEVEL 1 FOR 12.5;
}
}
}
TRANSITION_LIST("dataIn1")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 20;
LEVEL 0 FOR 25.0;
LEVEL 1 FOR 25.0;
}
}
}
TRANSITION_LIST("dataIn2")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 10;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
}
}
}
TRANSITION_LIST("dataIn3")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 5;
LEVEL 0 FOR 100.0;
LEVEL 1 FOR 100.0;
}
}
}
TRANSITION_LIST("dataOut")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("sel[1]")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 1;
LEVEL 0 FOR 400.0;
LEVEL 1 FOR 400.0;
}
LEVEL 0 FOR 200.0;
}
}
TRANSITION_LIST("sel[0]")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 2;
LEVEL 0 FOR 200.0;
LEVEL 1 FOR 200.0;
}
LEVEL 0 FOR 200.0;
}
}
DISPLAY_LINE
{
CHANNEL = "dataIn3";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 0;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "dataIn2";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 1;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "dataIn1";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 2;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "dataIn0";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 3;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "sel";
EXPAND_STATUS = EXPANDED;
RADIX = Binary;
TREE_INDEX = 4;
TREE_LEVEL = 0;
CHILDREN = 5, 6;
}
DISPLAY_LINE
{
CHANNEL = "sel[1]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 5;
TREE_LEVEL = 1;
PARENT = 4;
}
DISPLAY_LINE
{
CHANNEL = "sel[0]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 6;
TREE_LEVEL = 1;
PARENT = 4;
}
DISPLAY_LINE
{
CHANNEL = "dataOut";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 7;
TREE_LEVEL = 0;
}
TIME_BAR
{
TIME = 0;
MASTER = TRUE;
}
;

193
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "graphic" (version "1.4"))
(pin
(input)
(rect 248 184 416 200)
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
(text "SW[3]" (rect 5 0 39 13)(font "Intel Clear" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
)
(pin
(input)
(rect 248 200 416 216)
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
(text "SW[2]" (rect 5 0 39 13)(font "Intel Clear" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
)
(pin
(input)
(rect 248 216 416 232)
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
(text "SW[1]" (rect 5 0 39 13)(font "Intel Clear" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
)
(pin
(input)
(rect 248 232 416 248)
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
(text "SW[0]" (rect 5 0 39 13)(font "Intel Clear" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
)
(pin
(input)
(rect 248 248 416 264)
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
(text "KEY[1..0]" (rect 5 0 53 13)(font "Intel Clear" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
)
(pin
(output)
(rect 592 184 768 200)
(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
(text "LEDG[0]" (rect 90 0 132 11)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
(line (pt 52 4)(pt 78 4))
(line (pt 52 12)(pt 78 12))
(line (pt 52 12)(pt 52 4))
(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
)
(symbol
(rect 424 160 584 304)
(text "Mux4_1" (rect 5 0 46 11)(font "Arial" ))
(text "inst" (rect 8 128 26 139)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "dataIn3" (rect 0 0 38 11)(font "Arial" ))
(text "dataIn3" (rect 21 27 59 38)(font "Arial" ))
(line (pt 0 32)(pt 16 32))
)
(port
(pt 0 48)
(input)
(text "dataIn2" (rect 0 0 38 11)(font "Arial" ))
(text "dataIn2" (rect 21 43 59 54)(font "Arial" ))
(line (pt 0 48)(pt 16 48))
)
(port
(pt 0 64)
(input)
(text "dataIn1" (rect 0 0 38 11)(font "Arial" ))
(text "dataIn1" (rect 21 59 59 70)(font "Arial" ))
(line (pt 0 64)(pt 16 64))
)
(port
(pt 0 80)
(input)
(text "dataIn0" (rect 0 0 38 11)(font "Arial" ))
(text "dataIn0" (rect 21 75 59 86)(font "Arial" ))
(line (pt 0 80)(pt 16 80))
)
(port
(pt 0 96)
(input)
(text "sel[1..0]" (rect 0 0 38 11)(font "Arial" ))
(text "sel[1..0]" (rect 21 91 59 102)(font "Arial" ))
(line (pt 0 96)(pt 16 96)(line_width 3))
)
(port
(pt 160 32)
(output)
(text "dataOut" (rect 0 0 41 11)(font "Arial" ))
(text "dataOut" (rect 105 27 146 38)(font "Arial" ))
(line (pt 160 32)(pt 144 32))
)
(drawing
(rectangle (rect 16 16 144 128))
)
)
(connector
(pt 592 192)
(pt 584 192)
)
(connector
(pt 424 192)
(pt 416 192)
)
(connector
(pt 424 208)
(pt 416 208)
)
(connector
(pt 424 224)
(pt 416 224)
)
(connector
(pt 424 240)
(pt 416 240)
)
(connector
(pt 416 256)
(pt 424 256)
(bus)
)

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# Laboratórios de Sistemas Digitais
## Trabalho prático 02
### Tópico principal da aula: Modelação em VHDL, simulação e implementação de componentes combinatórios
* [Slides](https://github.com/TiagoRG/uaveiro-leci/blob/master/1ano/2semestre/lsd/slides/LSD_2022-23_AulaTP02.pdf)
* [Guião](https://github.com/TiagoRG/uaveiro-leci/blob/master/1ano/2semestre/lsd/pratica02/LSD_2022-23_TrabPrat02.pdf)
---
*Pode conter erros, caso encontre algum, crie um* [*ticket*](https://github.com/TiagoRG/uaveiro-leci/issues/new)

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1ano/2semestre/lsd/pratica02/part1/Dec2_4En.vhd Normal file
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library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Dec2_4En is
port (
enable : in std_logic;
inputs : in std_logic_vector(1 downto 0);
outputs : out std_logic_vector(3 downto 0)
);
end Dec2_4En;
architecture BehavEquations of Dec2_4En is
begin
outputs(0) <= enable and (not inputs(1)) and (not inputs(0));
outputs(1) <= enable and (not inputs(1)) and ( inputs(0));
outputs(2) <= enable and ( inputs(1)) and (not inputs(0));
outputs(3) <= enable and ( inputs(1)) and ( inputs(0));
end BehavEquations;
architecture BehavAssign of Dec2_4En is
begin
outputs <= "0000" when (enable = '0') else
"0001" when (inputs = "00") else
"0010" when (inputs = "01") else
"0100" when (inputs = "10") else
"1000";
end BehavAssign;
architecture BehavProc of Dec2_4En is
begin
process(enable, inputs)
begin
if (enable = '0') then
outputs <= "0000";
else
if (inputs = "00") then
outputs <= "0001";
elsif (inputs = "01") then
outputs <= "0010";
elsif (inputs = "10") then
outputs <= "0100";
else
outputs <= "1000";
end if;
end if;
end process;
end BehavProc;

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1ano/2semestre/lsd/pratica02/part1/Dec2_4EnDemo.vhd Normal file
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library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Dec2_4EnDemo is
port
(
SW : in std_logic_vector(2 downto 0);
LEDR : out std_logic_vector(3 downto 0)
);
end Dec2_4EnDemo;
architecture Shell of Dec2_4EnDemo is
begin
system_core : entity work.Dec2_4En(BehavProc)
port map(
enable => SW(2),
inputs => SW(1 downto 0),
outputs => LEDR(3 downto 0)
);
end Shell;

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/*<simulation_settings>
<ftestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off Dec2_4EnDemo -c Dec2_4EnDemo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/Dec2_4En_1.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/simulation/qsim/Dec2_4En_1.vwf.vht"</ftestbench_cmd>
<ttestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off Dec2_4EnDemo -c Dec2_4EnDemo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/Dec2_4En_1.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/simulation/qsim/Dec2_4En_1.vwf.vht"</ttestbench_cmd>
<fnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/simulation/qsim/" Dec2_4EnDemo -c Dec2_4EnDemo</fnetlist_cmd>
<tnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/simulation/qsim/" Dec2_4EnDemo -c Dec2_4EnDemo</tnetlist_cmd>
<modelsim_script>onerror {exit -code 1}
vlib work
vcom -work work Dec2_4EnDemo.vho
vcom -work work Dec2_4En_1.vwf.vht
vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.Dec2_4En_vhd_vec_tst
vcd file -direction Dec2_4EnDemo.msim.vcd
vcd add -internal Dec2_4En_vhd_vec_tst/*
vcd add -internal Dec2_4En_vhd_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script>
<modelsim_script_timing>onerror {exit -code 1}
vlib work
vcom -work work Dec2_4EnDemo.vho
vcom -work work Dec2_4En_1.vwf.vht
vsim -novopt -c -t 1ps -sdfmax Dec2_4En_vhd_vec_tst/i1=Dec2_4EnDemo_vhd.sdo -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.Dec2_4En_vhd_vec_tst
vcd file -direction Dec2_4EnDemo.msim.vcd
vcd add -internal Dec2_4En_vhd_vec_tst/*
vcd add -internal Dec2_4En_vhd_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script_timing>
<hdl_lang>vhdl</hdl_lang>
</simulation_settings>*/
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
HEADER
{
VERSION = 1;
TIME_UNIT = ns;
DATA_OFFSET = 0.0;
DATA_DURATION = 1000.0;
SIMULATION_TIME = 0.0;
GRID_PHASE = 0.0;
GRID_PERIOD = 10.0;
GRID_DUTY_CYCLE = 50;
}
SIGNAL("enable")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("inputs")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = BUS;
WIDTH = 2;
LSB_INDEX = 0;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("inputs[1]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "inputs";
}
SIGNAL("inputs[0]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "inputs";
}
SIGNAL("outputs")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = BUS;
WIDTH = 4;
LSB_INDEX = 0;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("outputs[3]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "outputs";
}
SIGNAL("outputs[2]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "outputs";
}
SIGNAL("outputs[1]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "outputs";
}
SIGNAL("outputs[0]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "outputs";
}
TRANSITION_LIST("enable")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 12;
LEVEL 0 FOR 40.0;
LEVEL 1 FOR 40.0;
}
LEVEL 0 FOR 40.0;
}
}
TRANSITION_LIST("inputs[1]")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 25;
LEVEL 0 FOR 20.0;
LEVEL 1 FOR 20.0;
}
}
}
TRANSITION_LIST("inputs[0]")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 50;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 10.0;
}
}
}
TRANSITION_LIST("outputs[3]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("outputs[2]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("outputs[1]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("outputs[0]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
DISPLAY_LINE
{
CHANNEL = "enable";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 0;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "inputs";
EXPAND_STATUS = EXPANDED;
RADIX = Binary;
TREE_INDEX = 1;
TREE_LEVEL = 0;
CHILDREN = 2, 3;
}
DISPLAY_LINE
{
CHANNEL = "inputs[1]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 2;
TREE_LEVEL = 1;
PARENT = 1;
}
DISPLAY_LINE
{
CHANNEL = "inputs[0]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 3;
TREE_LEVEL = 1;
PARENT = 1;
}
DISPLAY_LINE
{
CHANNEL = "outputs";
EXPAND_STATUS = EXPANDED;
RADIX = Binary;
TREE_INDEX = 4;
TREE_LEVEL = 0;
CHILDREN = 5, 6, 7, 8;
}
DISPLAY_LINE
{
CHANNEL = "outputs[3]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 5;
TREE_LEVEL = 1;
PARENT = 4;
}
DISPLAY_LINE
{
CHANNEL = "outputs[2]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 6;
TREE_LEVEL = 1;
PARENT = 4;
}
DISPLAY_LINE
{
CHANNEL = "outputs[1]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 7;
TREE_LEVEL = 1;
PARENT = 4;
}
DISPLAY_LINE
{
CHANNEL = "outputs[0]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 8;
TREE_LEVEL = 1;
PARENT = 4;
}
TIME_BAR
{
TIME = 0;
MASTER = TRUE;
}
;

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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 176 128)
(text "ALU4" (rect 5 0 32 12)(font "Arial" ))
(text "inst" (rect 8 96 20 108)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "a[3..0]" (rect 0 0 24 12)(font "Arial" ))
(text "a[3..0]" (rect 21 27 45 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 3))
)
(port
(pt 0 48)
(input)
(text "b[3..0]" (rect 0 0 24 12)(font "Arial" ))
(text "b[3..0]" (rect 21 43 45 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48)(line_width 3))
)
(port
(pt 0 64)
(input)
(text "op[2..0]" (rect 0 0 29 12)(font "Arial" ))
(text "op[2..0]" (rect 21 59 50 71)(font "Arial" ))
(line (pt 0 64)(pt 16 64)(line_width 3))
)
(port
(pt 160 32)
(output)
(text "r[3..0]" (rect 0 0 23 12)(font "Arial" ))
(text "r[3..0]" (rect 116 27 139 39)(font "Arial" ))
(line (pt 160 32)(pt 144 32)(line_width 3))
)
(port
(pt 160 48)
(output)
(text "m[3..0]" (rect 0 0 28 12)(font "Arial" ))
(text "m[3..0]" (rect 111 43 139 55)(font "Arial" ))
(line (pt 160 48)(pt 144 48)(line_width 3))
)
(drawing
(rectangle (rect 16 16 144 96)(line_width 1))
)
)

35
1ano/2semestre/lsd/pratica03/ALUDemo/ALU4.vhd Normal file
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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity ALU4 is
port
(
a,b : in std_logic_vector(3 downto 0);
op : in std_logic_vector(2 downto 0);
r, m : out std_logic_vector(3 downto 0)
);
end ALU4;
architecture Behavioral of ALU4 is
signal s_a, s_b, s_r : unsigned(3 downto 0);
signal s_m : unsigned(7 downto 0);
begin
s_a <= unsigned(a);
s_b <= unsigned(b);
s_m <= s_a * s_b;
with op select
s_r <= s_a + s_b when "000",
s_a - s_b when "001",
s_m(3 downto 0) when "010",
s_a / s_b when "011",
s_a rem s_b when "100",
s_a and s_b when "101",
s_a or s_b when "110",
s_a xor s_b when "111";
r <= std_logic_vector(s_r);
m <= std_logic_vector(s_m(7 downto 4)) when (op = "010") else (others => '0');
end Behavioral;

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1ano/2semestre/lsd/pratica03/ALUDemo/ALUDemo.bdf Normal file
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "graphic" (version "1.4"))
(pin
(input)
(rect 272 144 440 160)
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
(text "SW[7..4]" (rect 5 0 47 11)(font "Arial" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
(annotation_block (location)(rect 208 160 272 176))
)
(pin
(input)
(rect 272 160 440 176)
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
(text "SW[3..0]" (rect 5 0 48 13)(font "Intel Clear" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
(annotation_block (location)(rect 208 176 272 192))
)
(pin
(input)
(rect 272 176 440 192)
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
(text "SW[10..8]" (rect 5 0 54 11)(font "Arial" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
(annotation_block (location)(rect 208 192 272 208))
)
(pin
(output)
(rect 616 144 792 160)
(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
(text "LEDR[3..0]" (rect 90 0 144 11)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
(line (pt 52 4)(pt 78 4))
(line (pt 52 12)(pt 78 12))
(line (pt 52 12)(pt 52 4))
(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
(annotation_block (location)(rect 792 160 856 176))
)
(pin
(output)
(rect 616 160 792 176)
(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
(text "LEDR[7..4]" (rect 90 0 143 13)(font "Intel Clear" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
(line (pt 52 4)(pt 78 4))
(line (pt 52 12)(pt 78 12))
(line (pt 52 12)(pt 52 4))
(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
(annotation_block (location)(rect 792 176 848 192))
)
(symbol
(rect 448 120 608 232)
(text "ALU4" (rect 5 0 34 11)(font "Arial" ))
(text "inst" (rect 8 96 26 107)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "a[3..0]" (rect 0 0 30 11)(font "Arial" ))
(text "a[3..0]" (rect 21 27 51 38)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 3))
)
(port
(pt 0 48)
(input)
(text "b[3..0]" (rect 0 0 30 11)(font "Arial" ))
(text "b[3..0]" (rect 21 43 51 54)(font "Arial" ))
(line (pt 0 48)(pt 16 48)(line_width 3))
)
(port
(pt 0 64)
(input)
(text "op[2..0]" (rect 0 0 37 11)(font "Arial" ))
(text "op[2..0]" (rect 21 59 58 70)(font "Arial" ))
(line (pt 0 64)(pt 16 64)(line_width 3))
)
(port
(pt 160 32)
(output)
(text "r[3..0]" (rect 0 0 28 11)(font "Arial" ))
(text "r[3..0]" (rect 116 27 144 38)(font "Arial" ))
(line (pt 160 32)(pt 144 32)(line_width 3))
)
(port
(pt 160 48)
(output)
(text "m[3..0]" (rect 0 0 34 11)(font "Arial" ))
(text "m[3..0]" (rect 111 43 145 54)(font "Arial" ))
(line (pt 160 48)(pt 144 48)(line_width 3))
)
(drawing
(rectangle (rect 16 16 144 96))
)
)
(connector
(pt 448 152)
(pt 440 152)
(bus)
)
(connector
(pt 448 168)
(pt 440 168)
(bus)
)
(connector
(pt 448 184)
(pt 440 184)
(bus)
)
(connector
(pt 608 152)
(pt 616 152)
(bus)
)
(connector
(pt 608 168)
(pt 616 168)
(bus)
)

BIN
1ano/2semestre/lsd/pratica03/ALUDemo/output_files/ALUDemo.sof Normal file
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65
1ano/2semestre/lsd/pratica03/AdderDemo/AddSub4.bsf Normal file
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@ -0,0 +1,65 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 168 128)
(text "AddSub4" (rect 5 0 43 12)(font "Arial" ))
(text "inst" (rect 8 96 20 108)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "a[3..0]" (rect 0 0 24 12)(font "Arial" ))
(text "a[3..0]" (rect 21 27 45 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 3))
)
(port
(pt 0 48)
(input)
(text "b[3..0]" (rect 0 0 24 12)(font "Arial" ))
(text "b[3..0]" (rect 21 43 45 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48)(line_width 3))
)
(port
(pt 0 64)
(input)
(text "sub" (rect 0 0 14 12)(font "Arial" ))
(text "sub" (rect 21 59 35 71)(font "Arial" ))
(line (pt 0 64)(pt 16 64)(line_width 1))
)
(port
(pt 152 32)
(output)
(text "s[3..0]" (rect 0 0 24 12)(font "Arial" ))
(text "s[3..0]" (rect 107 27 131 39)(font "Arial" ))
(line (pt 152 32)(pt 136 32)(line_width 3))
)
(port
(pt 152 48)
(output)
(text "cout" (rect 0 0 16 12)(font "Arial" ))
(text "cout" (rect 115 43 131 55)(font "Arial" ))
(line (pt 152 48)(pt 136 48)(line_width 1))
)
(drawing
(rectangle (rect 16 16 136 96)(line_width 1))
)
)

37
1ano/2semestre/lsd/pratica03/AdderDemo/AddSub4.vhd Normal file
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@ -0,0 +1,37 @@
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity AddSub4 is
port
(
a, b : in std_logic_vector(3 downto 0);
sub : in std_logic;
s : out std_logic_vector(3 downto 0);
cout : out std_logic
);
end AddSub4;
--architecture Structural of AddSub4 is
-- signal s_b : std_logic_vector(3 downto 0);
-- signal s_cout : std_logic;
--begin
-- -- Mux
-- sub_mux : s_b <= b when sub='0' else not b;
-- out_mux : cout <= s_cout when sub='0' else not s_cout;
--
-- Adder : entity work.Adder4(Structural) port map
-- (
-- cin => sub, a => a, b => s_b, cout => s_cout, s => s
-- );
--end Structural;
architecture Behavioral of AddSub4 is
signal s_a, s_b, s_s : unsigned(4 downto 0);
begin
s_a <= '0' & unsigned(a);
s_b <= '0' & unsigned(b);
s_s <= (s_a + s_b) when (sub = '0') else (s_a - s_b);
s <= std_logic_vector(s_s(3 downto 0));
cout <= s_s(4);
end Behavioral;

65
1ano/2semestre/lsd/pratica03/AdderDemo/Adder4.bsf Normal file
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@ -0,0 +1,65 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 168 128)
(text "Adder4" (rect 5 0 36 12)(font "Arial" ))
(text "inst" (rect 8 96 20 108)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "a[3..0]" (rect 0 0 24 12)(font "Arial" ))
(text "a[3..0]" (rect 21 27 45 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 3))
)
(port
(pt 0 48)
(input)
(text "b[3..0]" (rect 0 0 24 12)(font "Arial" ))
(text "b[3..0]" (rect 21 43 45 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48)(line_width 3))
)
(port
(pt 0 64)
(input)
(text "cin" (rect 0 0 10 12)(font "Arial" ))
(text "cin" (rect 21 59 31 71)(font "Arial" ))
(line (pt 0 64)(pt 16 64)(line_width 1))
)
(port
(pt 152 32)
(output)
(text "s[3..0]" (rect 0 0 24 12)(font "Arial" ))
(text "s[3..0]" (rect 107 27 131 39)(font "Arial" ))
(line (pt 152 32)(pt 136 32)(line_width 3))
)
(port
(pt 152 48)
(output)
(text "cout" (rect 0 0 16 12)(font "Arial" ))
(text "cout" (rect 115 43 131 55)(font "Arial" ))
(line (pt 152 48)(pt 136 48)(line_width 1))
)
(drawing
(rectangle (rect 16 16 136 96)(line_width 1))
)
)

33
1ano/2semestre/lsd/pratica03/AdderDemo/Adder4.vhd Normal file
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@ -0,0 +1,33 @@
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Adder4 is
port
(
a, b : in std_logic_vector(3 downto 0);
cin : in std_logic;
s : out std_logic_vector(3 downto 0);
cout : out std_logic
);
end Adder4;
architecture Structural of Adder4 is
signal intCarry : std_logic_vector(2 downto 0);
begin
bit0 : entity work.FullAdder(Behavioral) port map
(
a => a(0), b => b(0), cin => cin, s => s(0), cout => intCarry(0)
);
bit1 : entity work.FullAdder(Behavioral) port map
(
a => a(1), b => b(1), cin => intCarry(0), s => s(1), cout => intCarry(1)
);
bit2 : entity work.FullAdder(Behavioral) port map
(
a => a(2), b => b(2), cin => intCarry(1), s => s(2), cout => intCarry(2)
);
bit3 : entity work.FullAdder(Behavioral) port map
(
a => a(3), b => b(3), cin => intCarry(2), s => s(3), cout => cout
);
end Structural;

562
1ano/2semestre/lsd/pratica03/AdderDemo/Adder4.vwf Normal file
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@ -0,0 +1,562 @@
/*<simulation_settings>
<ftestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off AdderDemo -c AdderDemo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/Adder4.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/qsim/Adder4.vwf.vht"</ftestbench_cmd>
<ttestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off AdderDemo -c AdderDemo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/Adder4.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/qsim/Adder4.vwf.vht"</ttestbench_cmd>
<fnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/qsim/" AdderDemo -c AdderDemo</fnetlist_cmd>
<tnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/simulation/qsim/" AdderDemo -c AdderDemo</tnetlist_cmd>
<modelsim_script>onerror {exit -code 1}
vlib work
vcom -work work AdderDemo.vho
vcom -work work Adder4.vwf.vht
vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.Adder4_vhd_vec_tst
vcd file -direction AdderDemo.msim.vcd
vcd add -internal Adder4_vhd_vec_tst/*
vcd add -internal Adder4_vhd_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script>
<modelsim_script_timing>onerror {exit -code 1}
vlib work
vcom -work work AdderDemo.vho
vcom -work work Adder4.vwf.vht
vsim -novopt -c -t 1ps -sdfmax Adder4_vhd_vec_tst/i1=AdderDemo_vhd.sdo -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.Adder4_vhd_vec_tst
vcd file -direction AdderDemo.msim.vcd
vcd add -internal Adder4_vhd_vec_tst/*
vcd add -internal Adder4_vhd_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script_timing>
<hdl_lang>vhdl</hdl_lang>
</simulation_settings>*/
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
HEADER
{
VERSION = 1;
TIME_UNIT = ns;
DATA_OFFSET = 0.0;
DATA_DURATION = 1000.0;
SIMULATION_TIME = 0.0;
GRID_PHASE = 0.0;
GRID_PERIOD = 10.0;
GRID_DUTY_CYCLE = 50;
}
SIGNAL("a")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = BUS;
WIDTH = 4;
LSB_INDEX = 0;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("a[3]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "a";
}
SIGNAL("a[2]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "a";
}
SIGNAL("a[1]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "a";
}
SIGNAL("a[0]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "a";
}
SIGNAL("b")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = BUS;
WIDTH = 4;
LSB_INDEX = 0;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("b[3]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "b";
}
SIGNAL("b[2]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "b";
}
SIGNAL("b[1]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "b";
}
SIGNAL("b[0]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "b";
}
SIGNAL("cin")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("cout")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("s")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = BUS;
WIDTH = 4;
LSB_INDEX = 0;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("s[3]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "s";
}
SIGNAL("s[2]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "s";
}
SIGNAL("s[1]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "s";
}
SIGNAL("s[0]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "s";
}
TRANSITION_LIST("a[3]")
{
NODE
{
REPEAT = 1;
LEVEL 1 FOR 240.0;
LEVEL 0 FOR 760.0;
}
}
TRANSITION_LIST("a[2]")
{
NODE
{
REPEAT = 1;
LEVEL 1 FOR 160.0;
LEVEL 0 FOR 840.0;
}
}
TRANSITION_LIST("a[1]")
{
NODE
{
REPEAT = 1;
LEVEL 1 FOR 240.0;
LEVEL 0 FOR 760.0;
}
}
TRANSITION_LIST("a[0]")
{
NODE
{
REPEAT = 1;
LEVEL 1 FOR 160.0;
LEVEL 0 FOR 840.0;
}
}
TRANSITION_LIST("b[3]")
{
NODE
{
REPEAT = 1;
LEVEL 1 FOR 80.0;
LEVEL 0 FOR 80.0;
LEVEL 1 FOR 80.0;
LEVEL 0 FOR 760.0;
}
}
TRANSITION_LIST("b[2]")
{
NODE
{
REPEAT = 1;
LEVEL 1 FOR 80.0;
LEVEL 0 FOR 80.0;
LEVEL 1 FOR 80.0;
LEVEL 0 FOR 760.0;
}
}
TRANSITION_LIST("b[1]")
{
NODE
{
REPEAT = 1;
LEVEL 1 FOR 80.0;
LEVEL 0 FOR 920.0;
}
}
TRANSITION_LIST("b[0]")
{
NODE
{
REPEAT = 1;
LEVEL 1 FOR 80.0;
LEVEL 0 FOR 920.0;
}
}
TRANSITION_LIST("cin")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 80.0;
LEVEL 1 FOR 80.0;
LEVEL 0 FOR 840.0;
}
}
TRANSITION_LIST("cout")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("s[3]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("s[2]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("s[1]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("s[0]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
DISPLAY_LINE
{
CHANNEL = "a";
EXPAND_STATUS = EXPANDED;
RADIX = Binary;
TREE_INDEX = 0;
TREE_LEVEL = 0;
CHILDREN = 1, 2, 3, 4;
}
DISPLAY_LINE
{
CHANNEL = "a[3]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 1;
TREE_LEVEL = 1;
PARENT = 0;
}
DISPLAY_LINE
{
CHANNEL = "a[2]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 2;
TREE_LEVEL = 1;
PARENT = 0;
}
DISPLAY_LINE
{
CHANNEL = "a[1]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 3;
TREE_LEVEL = 1;
PARENT = 0;
}
DISPLAY_LINE
{
CHANNEL = "a[0]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 4;
TREE_LEVEL = 1;
PARENT = 0;
}
DISPLAY_LINE
{
CHANNEL = "b";
EXPAND_STATUS = EXPANDED;
RADIX = Binary;
TREE_INDEX = 5;
TREE_LEVEL = 0;
CHILDREN = 6, 7, 8, 9;
}
DISPLAY_LINE
{
CHANNEL = "b[3]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 6;
TREE_LEVEL = 1;
PARENT = 5;
}
DISPLAY_LINE
{
CHANNEL = "b[2]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 7;
TREE_LEVEL = 1;
PARENT = 5;
}
DISPLAY_LINE
{
CHANNEL = "b[1]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 8;
TREE_LEVEL = 1;
PARENT = 5;
}
DISPLAY_LINE
{
CHANNEL = "b[0]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 9;
TREE_LEVEL = 1;
PARENT = 5;
}
DISPLAY_LINE
{
CHANNEL = "cin";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 10;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "cout";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 11;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "s";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 12;
TREE_LEVEL = 0;
CHILDREN = 13, 14, 15, 16;
}
DISPLAY_LINE
{
CHANNEL = "s[3]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 13;
TREE_LEVEL = 1;
PARENT = 12;
}
DISPLAY_LINE
{
CHANNEL = "s[2]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 14;
TREE_LEVEL = 1;
PARENT = 12;
}
DISPLAY_LINE
{
CHANNEL = "s[1]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 15;
TREE_LEVEL = 1;
PARENT = 12;
}
DISPLAY_LINE
{
CHANNEL = "s[0]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 16;
TREE_LEVEL = 1;
PARENT = 12;
}
TIME_BAR
{
TIME = 0;
MASTER = TRUE;
}
;

388
1ano/2semestre/lsd/pratica03/AdderDemo/AdderDemo.bdf Normal file
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@ -0,0 +1,388 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "graphic" (version "1.4"))
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(text "SW[3..0]" (rect 5 0 48 13)(font "Intel Clear" ))
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)
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)
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)
(annotation_block (location)(rect 824 400 880 416))
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(rect 648 200 824 216)
(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
(text "LEDR[4]" (rect 90 0 132 13)(font "Intel Clear" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
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(line (pt 52 12)(pt 78 12))
(line (pt 52 12)(pt 52 4))
(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
(annotation_block (location)(rect 824 216 880 232))
)
(pin
(output)
(rect 488 288 664 304)
(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
(text "LEDR[9..5]" (rect 90 0 144 11)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
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(line (pt 52 12)(pt 52 4))
(line (pt 78 4)(pt 82 8))
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(line (pt 78 12)(pt 82 8))
)
(annotation_block (location)(rect 664 304 720 320))
)
(symbol
(rect 488 160 640 272)
(text "Adder4" (rect 5 0 42 11)(font "Arial" ))
(text "Adder4Demo" (rect 8 96 74 107)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "a[3..0]" (rect 0 0 30 11)(font "Arial" ))
(text "a[3..0]" (rect 21 27 51 38)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 3))
)
(port
(pt 0 48)
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(text "b[3..0]" (rect 0 0 30 11)(font "Arial" ))
(text "b[3..0]" (rect 21 43 51 54)(font "Arial" ))
(line (pt 0 48)(pt 16 48)(line_width 3))
)
(port
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(input)
(text "cin" (rect 0 0 15 11)(font "Arial" ))
(text "cin" (rect 21 59 36 70)(font "Arial" ))
(line (pt 0 64)(pt 16 64))
)
(port
(pt 152 32)
(output)
(text "s[3..0]" (rect 0 0 30 11)(font "Arial" ))
(text "s[3..0]" (rect 106 27 136 38)(font "Arial" ))
(line (pt 152 32)(pt 136 32)(line_width 3))
)
(port
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(text "cout" (rect 0 0 22 11)(font "Arial" ))
(text "cout" (rect 113 43 135 54)(font "Arial" ))
(line (pt 152 48)(pt 136 48))
)
(drawing
(rectangle (rect 16 16 136 96))
)
)
(symbol
(rect 488 344 640 456)
(text "AddSub4" (rect 5 0 52 11)(font "Arial" ))
(text "AddSub4Demo" (rect 8 96 84 107)(font "Arial" ))
(port
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(text "a[3..0]" (rect 21 27 51 38)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 3))
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(line (pt 0 48)(pt 16 48)(line_width 3))
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(text "s[3..0]" (rect 106 27 136 38)(font "Arial" ))
(line (pt 152 32)(pt 136 32)(line_width 3))
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(text "1" (rect 18 0 26 11)(font "Courier New" (bold))(invisible))
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(pt 480 296)
)
(connector
(pt 488 296)
(pt 480 296)
(bus)
)

16
1ano/2semestre/lsd/pratica03/AdderDemo/FullAdder.vhd Normal file
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@ -0,0 +1,16 @@
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity FullAdder is
port
(
a, b, cin : in std_logic;
s, cout : out std_logic
);
end FullAdder;
architecture Behavioral of FullAdder is
begin
s <= a xor b xor cin;
cout <= (a and b) or (a and cin) or (b and cin);
end Behavioral;

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1ano/2semestre/lsd/pratica03/AdderDemo/output_files/AdderDemo.sof Normal file
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1ano/2semestre/lsd/pratica03/LSD_2022-23_TrabPrat03-1.pdf Normal file
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1ano/2semestre/lsd/pratica03/README.md Executable file
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# Laboratórios de Sistemas Digitais
## Trabalho prático 03
### Tópico principal da aula: Modelação em VHDL e implementação de circuitos aritméticos
* [Slides](https://github.com/TiagoRG/uaveiro-leci/blob/master/1ano/2semestre/lsd/slides/LSD_2022-23_AulaTP03.pdf)
* [Guião](https://github.com/TiagoRG/uaveiro-leci/blob/master/1ano/2semestre/lsd/pratica03/LSD_2022-23_TrabPrat03-1.pdf)
---
*Pode conter erros, caso encontre algum, crie um* [*ticket*](https://github.com/TiagoRG/uaveiro-leci/issues/new)

44
1ano/2semestre/lsd/pratica04/CounterDemo/Bin7SegDecoder.bsf Normal file
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@ -0,0 +1,44 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 224 96)
(text "Bin7SegDecoder" (rect 5 0 71 12)(font "Arial" ))
(text "inst" (rect 8 64 20 76)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "binInput[3..0]" (rect 0 0 49 12)(font "Arial" ))
(text "binInput[3..0]" (rect 21 27 70 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 3))
)
(port
(pt 208 32)
(output)
(text "decOut_n[6..0]" (rect 0 0 59 12)(font "Arial" ))
(text "decOut_n[6..0]" (rect 128 27 187 39)(font "Arial" ))
(line (pt 208 32)(pt 192 32)(line_width 3))
)
(drawing
(rectangle (rect 16 16 192 64)(line_width 1))
)
)

30
1ano/2semestre/lsd/pratica04/CounterDemo/Bin7SegDecoder.vhd Normal file
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@ -0,0 +1,30 @@
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Bin7SegDecoder is
port
(
binInput : in std_logic_vector(3 downto 0);
decOut_n : out std_logic_vector(6 downto 0)
);
end Bin7SegDecoder;
architecture Behavioral of Bin7SegDecoder is
begin
decOut_n <= "1111001" when (binInput = "0001") else --1
"0100100" when (binInput = "0010") else --2
"0110000" when (binInput = "0011") else --3
"0011001" when (binInput = "0100") else --4
"0010010" when (binInput = "0101") else --5
"0000010" when (binInput = "0110") else --6
"1111000" when (binInput = "0111") else --7
"0000000" when (binInput = "1000") else --8
"0010000" when (binInput = "1001") else --9
"0001000" when (binInput = "1010") else --A
"0000011" when (binInput = "1011") else --b
"1000110" when (binInput = "1100") else --C
"0100001" when (binInput = "1101") else --d
"0000110" when (binInput = "1110") else --E
"0001110" when (binInput = "1111") else --F
"1000000"; --0
end Behavioral;

233
1ano/2semestre/lsd/pratica04/CounterDemo/CounterDemo.bdf Normal file
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@ -0,0 +1,233 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "graphic" (version "1.4"))
(pin
(input)
(rect 256 232 424 248)
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
(text "KEY[1]" (rect 5 0 39 11)(font "Arial" ))
(pt 168 8)
(drawing
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)
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(annotation_block (location)(rect 192 248 256 264))
)
(pin
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(text "NOT" (rect 1 0 22 10)(font "Arial" (font_size 6)))
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(line (pt 0 32)(pt 16 32)(line_width 3))
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)
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)
)
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(text "inst1" (rect 8 64 32 77)(font "Intel Clear" ))
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(output)
(text "clkOut" (rect 0 0 33 11)(font "Arial" ))
(text "clkOut" (rect 96 27 129 38)(font "Arial" ))
(line (pt 144 32)(pt 128 32))
)
(drawing
(rectangle (rect 16 16 128 64))
)
)
(connector
(pt 480 224)
(pt 488 224)
)
(connector
(pt 488 240)
(pt 480 240)
)
(connector
(pt 432 240)
(pt 424 240)
)
(connector
(pt 664 224)
(pt 672 224)
(bus)
)
(connector
(pt 872 224)
(pt 880 224)
(bus)
)
(connector
(pt 424 256)
(pt 488 256)
)
(connector
(pt 480 184)
(pt 472 184)
)
(connector
(pt 480 224)
(pt 480 184)
)
(connector
(pt 328 184)
(pt 320 184)
)

44
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@ -0,0 +1,44 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 176 96)
(text "CounterDown4" (rect 5 0 65 12)(font "Arial" ))
(text "inst" (rect 8 64 20 76)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "clock" (rect 0 0 20 12)(font "Arial" ))
(text "clock" (rect 21 27 41 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
(pt 160 32)
(output)
(text "count[3..0]" (rect 0 0 41 12)(font "Arial" ))
(text "count[3..0]" (rect 98 27 139 39)(font "Arial" ))
(line (pt 160 32)(pt 144 32)(line_width 3))
)
(drawing
(rectangle (rect 16 16 144 64)(line_width 1))
)
)

23
1ano/2semestre/lsd/pratica04/CounterDemo/CounterDown4.vhd Normal file
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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity CounterDown4 is
port
(
clock : in std_logic;
count : out std_logic_vector(3 downto 0)
);
end CounterDown4;
architecture Behavioral of CounterDown4 is
signal s_count : unsigned(3 downto 0);
begin
process(clock)
begin
if (rising_edge(clock)) then
s_count <= s_count - 1;
end if;
end process;
count <= std_logic_vector(s_count);
end Behavioral;

253
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/*<simulation_settings>
<ftestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off CounterDemo -c CounterDemo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDown4.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/qsim/CounterDown4.vwf.vht"</ftestbench_cmd>
<ttestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off CounterDemo -c CounterDemo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDown4.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/qsim/CounterDown4.vwf.vht"</ttestbench_cmd>
<fnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/qsim/" CounterDemo -c CounterDemo</fnetlist_cmd>
<tnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/qsim/" CounterDemo -c CounterDemo</tnetlist_cmd>
<modelsim_script>onerror {exit -code 1}
vlib work
vcom -work work CounterDemo.vho
vcom -work work CounterDown4.vwf.vht
vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.CounterDown4_vhd_vec_tst
vcd file -direction CounterDemo.msim.vcd
vcd add -internal CounterDown4_vhd_vec_tst/*
vcd add -internal CounterDown4_vhd_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script>
<modelsim_script_timing>onerror {exit -code 1}
vlib work
vcom -work work CounterDemo.vho
vcom -work work CounterDown4.vwf.vht
vsim -novopt -c -t 1ps -sdfmax CounterDown4_vhd_vec_tst/i1=CounterDemo_vhd.sdo -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.CounterDown4_vhd_vec_tst
vcd file -direction CounterDemo.msim.vcd
vcd add -internal CounterDown4_vhd_vec_tst/*
vcd add -internal CounterDown4_vhd_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script_timing>
<hdl_lang>vhdl</hdl_lang>
</simulation_settings>*/
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
HEADER
{
VERSION = 1;
TIME_UNIT = ns;
DATA_OFFSET = 0.0;
DATA_DURATION = 1000.0;
SIMULATION_TIME = 0.0;
GRID_PHASE = 0.0;
GRID_PERIOD = 10.0;
GRID_DUTY_CYCLE = 50;
}
SIGNAL("clk")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("count")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = BUS;
WIDTH = 4;
LSB_INDEX = 0;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("count[3]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "count";
}
SIGNAL("count[2]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "count";
}
SIGNAL("count[1]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "count";
}
SIGNAL("count[0]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "count";
}
TRANSITION_LIST("clk")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 25;
LEVEL 0 FOR 20.0;
LEVEL 1 FOR 20.0;
}
}
}
TRANSITION_LIST("count[3]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("count[2]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("count[1]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("count[0]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
DISPLAY_LINE
{
CHANNEL = "clk";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 0;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "count";
EXPAND_STATUS = EXPANDED;
RADIX = Binary;
TREE_INDEX = 1;
TREE_LEVEL = 0;
CHILDREN = 2, 3, 4, 5;
}
DISPLAY_LINE
{
CHANNEL = "count[3]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 2;
TREE_LEVEL = 1;
PARENT = 1;
}
DISPLAY_LINE
{
CHANNEL = "count[2]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 3;
TREE_LEVEL = 1;
PARENT = 1;
}
DISPLAY_LINE
{
CHANNEL = "count[1]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 4;
TREE_LEVEL = 1;
PARENT = 1;
}
DISPLAY_LINE
{
CHANNEL = "count[0]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 5;
TREE_LEVEL = 1;
PARENT = 1;
}
TIME_BAR
{
TIME = 0;
MASTER = TRUE;
}
;

58
1ano/2semestre/lsd/pratica04/CounterDemo/CounterUpDown4.bsf Normal file
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@ -0,0 +1,58 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 192 128)
(text "CounterUpDown4" (rect 5 0 76 12)(font "Arial" ))
(text "inst" (rect 8 96 20 108)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "clock" (rect 0 0 20 12)(font "Arial" ))
(text "clock" (rect 21 27 41 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
(pt 0 48)
(input)
(text "reset" (rect 0 0 20 12)(font "Arial" ))
(text "reset" (rect 21 43 41 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48)(line_width 1))
)
(port
(pt 0 64)
(input)
(text "upDown" (rect 0 0 31 12)(font "Arial" ))
(text "upDown" (rect 21 59 52 71)(font "Arial" ))
(line (pt 0 64)(pt 16 64)(line_width 1))
)
(port
(pt 176 32)
(output)
(text "count[3..0]" (rect 0 0 41 12)(font "Arial" ))
(text "count[3..0]" (rect 114 27 155 39)(font "Arial" ))
(line (pt 176 32)(pt 160 32)(line_width 3))
)
(drawing
(rectangle (rect 16 16 160 96)(line_width 1))
)
)

31
1ano/2semestre/lsd/pratica04/CounterDemo/CounterUpDown4.vhd Normal file
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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity CounterUpDown4 is
port
(
clock : in std_logic;
reset : in std_logic;
upDown : in std_logic;
count : out std_logic_vector(3 downto 0)
);
end CounterUpDown4;
architecture Behavioral of CounterUpDown4 is
signal s_count : unsigned(3 downto 0);
begin
process(clock, reset, upDown)
begin
if (reset = '1') then
s_count <= to_unsigned(0, 4);
elsif (rising_edge(clock)) then
if (upDown = '1') then
s_count <= s_count - 1;
else
s_count <= s_count + 1;
end if;
end if;
end process;
count <= std_logic_vector(s_count);
end Behavioral;

44
1ano/2semestre/lsd/pratica04/CounterDemo/FreqDivider.bsf Normal file
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@ -0,0 +1,44 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 160 96)
(text "FreqDivider" (rect 5 0 52 12)(font "Arial" ))
(text "inst" (rect 8 64 20 76)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "clkIn" (rect 0 0 17 12)(font "Arial" ))
(text "clkIn" (rect 21 27 38 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
(pt 144 32)
(output)
(text "clkOut" (rect 0 0 24 12)(font "Arial" ))
(text "clkOut" (rect 99 27 123 39)(font "Arial" ))
(line (pt 144 32)(pt 128 32)(line_width 1))
)
(drawing
(rectangle (rect 16 16 128 64)(line_width 1))
)
)

33
1ano/2semestre/lsd/pratica04/CounterDemo/FreqDivider.vhd Normal file
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@ -0,0 +1,33 @@
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity FreqDivider is
port (clkIn : in std_logic;
clkOut : out std_logic
);
end FreqDivider;
architecture Behavioral of FreqDivider is
signal s_counter : unsigned(31 downto 0);
signal s_halfWay : unsigned(31 downto 0);
signal k : std_logic_vector(31 downto 0);
begin
k <= x"017D7840";
s_halfWay <= unsigned(k);
process(clkIn)
begin
if (rising_edge(clkIn)) then
if (s_counter = s_halfWay - 1) then
clkOut <= '0';
s_counter <= (others => '0');
else
if (s_counter = s_halfWay/2 - 1) then
clkOut <= '1';
end if;
s_counter <= s_counter + 1;
end if;
end if;
end process;
end Behavioral;

BIN
1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.sof Normal file
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Binary file not shown.

43
1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD.vhd Normal file
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@ -0,0 +1,43 @@
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity FlipFlopD is
port
(
clk : in std_logic;
d : in std_logic;
set : in std_logic;
rst : in std_logic;
q : out std_logic
);
end FlipFlopD;
architecture BehavS of FlipFlopD is
begin
process (clk)
begin
if (rising_edge(clk)) then
if (rst = '1') then
q <= '0';
elsif (set = '1') then
q <= '1';
else
q <= d;
end if;
end if;
end process;
end BehavS;
architecture BehavAs of FlipFlopD is
begin
process (clk, set, rst)
begin
if (rst = '1') then
q <= '0';
elsif (set = '1') then
q <= '1';
elsif (rising_edge(clk)) then
q <= d;
end if;
end process;
end BehavAs;

347
1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD.vwf Normal file
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@ -0,0 +1,347 @@
/*<simulation_settings>
<ftestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off FlipFlopD_Demo -c FlipFlopD_Demo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/qsim/FlipFlopD.vwf.vht"</ftestbench_cmd>
<ttestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off FlipFlopD_Demo -c FlipFlopD_Demo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/qsim/FlipFlopD.vwf.vht"</ttestbench_cmd>
<fnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/qsim/" FlipFlopD_Demo -c FlipFlopD_Demo</fnetlist_cmd>
<tnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/simulation/qsim/" FlipFlopD_Demo -c FlipFlopD_Demo</tnetlist_cmd>
<modelsim_script>onerror {exit -code 1}
vlib work
vcom -work work FlipFlopD_Demo.vho
vcom -work work FlipFlopD.vwf.vht
vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.FlipFlopD_vhd_vec_tst
vcd file -direction FlipFlopD_Demo.msim.vcd
vcd add -internal FlipFlopD_vhd_vec_tst/*
vcd add -internal FlipFlopD_vhd_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script>
<modelsim_script_timing>onerror {exit -code 1}
vlib work
vcom -work work FlipFlopD_Demo.vho
vcom -work work FlipFlopD.vwf.vht
vsim -novopt -c -t 1ps -sdfmax FlipFlopD_vhd_vec_tst/i1=FlipFlopD_Demo_vhd.sdo -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.FlipFlopD_vhd_vec_tst
vcd file -direction FlipFlopD_Demo.msim.vcd
vcd add -internal FlipFlopD_vhd_vec_tst/*
vcd add -internal FlipFlopD_vhd_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script_timing>
<hdl_lang>vhdl</hdl_lang>
</simulation_settings>*/
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
HEADER
{
VERSION = 1;
TIME_UNIT = ns;
DATA_OFFSET = 0.0;
DATA_DURATION = 1000.0;
SIMULATION_TIME = 0.0;
GRID_PHASE = 0.0;
GRID_PERIOD = 10.0;
GRID_DUTY_CYCLE = 50;
}
SIGNAL("clk")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("d")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("q")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("rst")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("set")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
TRANSITION_LIST("clk")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 25;
LEVEL 0 FOR 20.0;
LEVEL 1 FOR 20.0;
}
}
}
TRANSITION_LIST("d")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 20.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 15.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 20.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 15.0;
LEVEL 1 FOR 15.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 15.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 15.0;
LEVEL 1 FOR 15.0;
LEVEL 0 FOR 20.0;
LEVEL 1 FOR 20.0;
LEVEL 0 FOR 30.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 20.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 15.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 15.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 20.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 20.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 25.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 15.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 20.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 20.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 15.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 20.0;
LEVEL 1 FOR 15.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 20.0;
LEVEL 0 FOR 5.0;
}
}
TRANSITION_LIST("q")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("rst")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 70.0;
LEVEL 0 FOR 310.0;
LEVEL 1 FOR 120.0;
LEVEL 0 FOR 450.0;
}
}
TRANSITION_LIST("set")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 200.0;
LEVEL 1 FOR 90.0;
LEVEL 0 FOR 140.0;
LEVEL 1 FOR 120.0;
LEVEL 0 FOR 450.0;
}
}
DISPLAY_LINE
{
CHANNEL = "clk";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 0;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "rst";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 1;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "set";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 2;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "d";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 3;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "q";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 4;
TREE_LEVEL = 0;
}
TIME_BAR
{
TIME = 0;
MASTER = TRUE;
}
;

22
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library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity FlipFlopD_Demo is
port(
SW : in std_logic_vector(2 downto 0);
KEY : in std_logic_vector(1 downto 0);
LEDR : out std_logic_vector(1 downto 0)
);
end FlipFlopD_Demo;
architecture Shell of FlipFlopD_Demo is
begin
ff_d : entity work.FlipFlopD(BehavS)
port map(
clk => not KEY(0),
d => SW(0),
set => SW(1),
rst => SW(2),
q => LEDR(0)
);
end Shell;

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1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/output_files/FlipFlopD_Demo.sof Normal file
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BIN
1ano/2semestre/lsd/pratica04/LSD_2022-23_TrabPrat04.pdf Normal file
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1ano/2semestre/lsd/pratica04/RegisterDemo/Register8.bsf Normal file
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 208 128)
(text "Register8" (rect 5 0 43 12)(font "Arial" ))
(text "inst" (rect 8 96 20 108)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "dataIn[7..0]" (rect 0 0 43 12)(font "Arial" ))
(text "dataIn[7..0]" (rect 21 27 64 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 3))
)
(port
(pt 0 48)
(input)
(text "clk" (rect 0 0 10 12)(font "Arial" ))
(text "clk" (rect 21 43 31 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48)(line_width 1))
)
(port
(pt 0 64)
(input)
(text "wrEn" (rect 0 0 21 12)(font "Arial" ))
(text "wrEn" (rect 21 59 42 71)(font "Arial" ))
(line (pt 0 64)(pt 16 64)(line_width 1))
)
(port
(pt 192 32)
(output)
(text "dataOut[7..0]" (rect 0 0 50 12)(font "Arial" ))
(text "dataOut[7..0]" (rect 121 27 171 39)(font "Arial" ))
(line (pt 192 32)(pt 176 32)(line_width 3))
)
(drawing
(rectangle (rect 16 16 176 96)(line_width 1))
)
)

24
1ano/2semestre/lsd/pratica04/RegisterDemo/Register8.vhd Normal file
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@ -0,0 +1,24 @@
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Register8 is
port
(
dataIn : in std_logic_vector(7 downto 0);
clk : in std_logic;
wrEn : in std_logic;
dataOut : out std_logic_vector(7 downto 0)
);
end Register8;
architecture Behavioral of Register8 is
begin
process (clk)
begin
if (rising_edge(clk)) then
if (wrEn = '1') then
dataOut <= dataIn;
end if;
end if;
end process;
end Behavioral;

760
1ano/2semestre/lsd/pratica04/RegisterDemo/Register8.vwf Normal file
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@ -0,0 +1,760 @@
/*<simulation_settings>
<ftestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off RegisterDemo -c RegisterDemo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/Register8.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/Register8.vwf.vht"</ftestbench_cmd>
<ttestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off RegisterDemo -c RegisterDemo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/Register8.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/Register8.vwf.vht"</ttestbench_cmd>
<fnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/" RegisterDemo -c RegisterDemo</fnetlist_cmd>
<tnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/" RegisterDemo -c RegisterDemo</tnetlist_cmd>
<modelsim_script>onerror {exit -code 1}
vlib work
vcom -work work RegisterDemo.vho
vcom -work work Register8.vwf.vht
vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.Register8_vhd_vec_tst
vcd file -direction RegisterDemo.msim.vcd
vcd add -internal Register8_vhd_vec_tst/*
vcd add -internal Register8_vhd_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script>
<modelsim_script_timing>onerror {exit -code 1}
vlib work
vcom -work work RegisterDemo.vho
vcom -work work Register8.vwf.vht
vsim -novopt -c -t 1ps -sdfmax Register8_vhd_vec_tst/i1=RegisterDemo_vhd.sdo -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.Register8_vhd_vec_tst
vcd file -direction RegisterDemo.msim.vcd
vcd add -internal Register8_vhd_vec_tst/*
vcd add -internal Register8_vhd_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script_timing>
<hdl_lang>vhdl</hdl_lang>
</simulation_settings>*/
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
HEADER
{
VERSION = 1;
TIME_UNIT = ns;
DATA_OFFSET = 0.0;
DATA_DURATION = 1000.0;
SIMULATION_TIME = 0.0;
GRID_PHASE = 0.0;
GRID_PERIOD = 10.0;
GRID_DUTY_CYCLE = 50;
}
SIGNAL("clk")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("dataIn")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = BUS;
WIDTH = 8;
LSB_INDEX = 0;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("dataIn[7]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "dataIn";
}
SIGNAL("dataIn[6]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "dataIn";
}
SIGNAL("dataIn[5]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "dataIn";
}
SIGNAL("dataIn[4]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "dataIn";
}
SIGNAL("dataIn[3]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "dataIn";
}
SIGNAL("dataIn[2]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "dataIn";
}
SIGNAL("dataIn[1]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "dataIn";
}
SIGNAL("dataIn[0]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "dataIn";
}
SIGNAL("dataOut")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = BUS;
WIDTH = 8;
LSB_INDEX = 0;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("dataOut[7]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "dataOut";
}
SIGNAL("dataOut[6]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "dataOut";
}
SIGNAL("dataOut[5]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "dataOut";
}
SIGNAL("dataOut[4]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "dataOut";
}
SIGNAL("dataOut[3]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "dataOut";
}
SIGNAL("dataOut[2]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "dataOut";
}
SIGNAL("dataOut[1]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "dataOut";
}
SIGNAL("dataOut[0]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "dataOut";
}
SIGNAL("wrEn")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
TRANSITION_LIST("clk")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 25;
LEVEL 0 FOR 20.0;
LEVEL 1 FOR 20.0;
}
}
}
TRANSITION_LIST("dataIn[7]")
{
NODE
{
REPEAT = 1;
LEVEL 1 FOR 200.0;
LEVEL 0 FOR 40.0;
LEVEL 1 FOR 120.0;
LEVEL 0 FOR 40.0;
LEVEL 1 FOR 40.0;
LEVEL 0 FOR 120.0;
LEVEL 1 FOR 40.0;
LEVEL 0 FOR 40.0;
LEVEL 1 FOR 40.0;
LEVEL 0 FOR 40.0;
LEVEL 1 FOR 40.0;
LEVEL 0 FOR 40.0;
LEVEL 1 FOR 40.0;
LEVEL 0 FOR 120.0;
LEVEL 1 FOR 40.0;
}
}
TRANSITION_LIST("dataIn[6]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 80.0;
LEVEL 1 FOR 80.0;
LEVEL 0 FOR 40.0;
LEVEL 1 FOR 40.0;
LEVEL 0 FOR 40.0;
LEVEL 1 FOR 40.0;
LEVEL 0 FOR 120.0;
LEVEL 1 FOR 120.0;
LEVEL 0 FOR 40.0;
LEVEL 1 FOR 80.0;
LEVEL 0 FOR 120.0;
LEVEL 1 FOR 40.0;
LEVEL 0 FOR 120.0;
LEVEL 1 FOR 40.0;
}
}
TRANSITION_LIST("dataIn[5]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 80.0;
LEVEL 1 FOR 40.0;
LEVEL 0 FOR 120.0;
LEVEL 1 FOR 40.0;
LEVEL 0 FOR 80.0;
LEVEL 1 FOR 40.0;
LEVEL 0 FOR 80.0;
LEVEL 1 FOR 80.0;
LEVEL 0 FOR 120.0;
LEVEL 1 FOR 40.0;
LEVEL 0 FOR 40.0;
LEVEL 1 FOR 80.0;
LEVEL 0 FOR 40.0;
LEVEL 1 FOR 40.0;
LEVEL 0 FOR 40.0;
LEVEL 1 FOR 40.0;
}
}
TRANSITION_LIST("dataIn[4]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 200.0;
LEVEL 1 FOR 160.0;
LEVEL 0 FOR 40.0;
LEVEL 1 FOR 320.0;
LEVEL 0 FOR 160.0;
LEVEL 1 FOR 40.0;
LEVEL 0 FOR 80.0;
}
}
TRANSITION_LIST("dataIn[3]")
{
NODE
{
REPEAT = 1;
LEVEL 1 FOR 160.0;
LEVEL 0 FOR 40.0;
LEVEL 1 FOR 120.0;
LEVEL 0 FOR 40.0;
LEVEL 1 FOR 80.0;
LEVEL 0 FOR 80.0;
LEVEL 1 FOR 40.0;
LEVEL 0 FOR 40.0;
LEVEL 1 FOR 160.0;
LEVEL 0 FOR 40.0;
LEVEL 1 FOR 120.0;
LEVEL 0 FOR 80.0;
}
}
TRANSITION_LIST("dataIn[2]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 80.0;
LEVEL 1 FOR 40.0;
LEVEL 0 FOR 120.0;
LEVEL 1 FOR 40.0;
LEVEL 0 FOR 40.0;
LEVEL 1 FOR 40.0;
LEVEL 0 FOR 120.0;
LEVEL 1 FOR 40.0;
LEVEL 0 FOR 40.0;
LEVEL 1 FOR 80.0;
LEVEL 0 FOR 40.0;
LEVEL 1 FOR 40.0;
LEVEL 0 FOR 40.0;
LEVEL 1 FOR 80.0;
LEVEL 0 FOR 80.0;
LEVEL 1 FOR 80.0;
}
}
TRANSITION_LIST("dataIn[1]")
{
NODE
{
REPEAT = 1;
LEVEL 1 FOR 80.0;
LEVEL 0 FOR 80.0;
LEVEL 1 FOR 80.0;
LEVEL 0 FOR 80.0;
LEVEL 1 FOR 40.0;
LEVEL 0 FOR 40.0;
LEVEL 1 FOR 40.0;
LEVEL 0 FOR 80.0;
LEVEL 1 FOR 40.0;
LEVEL 0 FOR 120.0;
LEVEL 1 FOR 40.0;
LEVEL 0 FOR 40.0;
LEVEL 1 FOR 40.0;
LEVEL 0 FOR 40.0;
LEVEL 1 FOR 40.0;
LEVEL 0 FOR 40.0;
LEVEL 1 FOR 40.0;
LEVEL 0 FOR 40.0;
}
}
TRANSITION_LIST("dataIn[0]")
{
NODE
{
REPEAT = 1;
LEVEL 1 FOR 160.0;
LEVEL 0 FOR 40.0;
LEVEL 1 FOR 120.0;
LEVEL 0 FOR 40.0;
LEVEL 1 FOR 40.0;
LEVEL 0 FOR 40.0;
LEVEL 1 FOR 40.0;
LEVEL 0 FOR 40.0;
LEVEL 1 FOR 40.0;
LEVEL 0 FOR 160.0;
LEVEL 1 FOR 40.0;
LEVEL 0 FOR 80.0;
LEVEL 1 FOR 80.0;
LEVEL 0 FOR 40.0;
LEVEL 1 FOR 40.0;
}
}
TRANSITION_LIST("dataOut[7]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("dataOut[6]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("dataOut[5]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("dataOut[4]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("dataOut[3]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("dataOut[2]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("dataOut[1]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("dataOut[0]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("wrEn")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 1;
LEVEL 0 FOR 400.0;
LEVEL 1 FOR 400.0;
}
LEVEL 0 FOR 200.0;
}
}
DISPLAY_LINE
{
CHANNEL = "wrEn";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 0;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "clk";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 1;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "dataIn";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 2;
TREE_LEVEL = 0;
CHILDREN = 3, 4, 5, 6, 7, 8, 9, 10;
}
DISPLAY_LINE
{
CHANNEL = "dataIn[7]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 3;
TREE_LEVEL = 1;
PARENT = 2;
}
DISPLAY_LINE
{
CHANNEL = "dataIn[6]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 4;
TREE_LEVEL = 1;
PARENT = 2;
}
DISPLAY_LINE
{
CHANNEL = "dataIn[5]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 5;
TREE_LEVEL = 1;
PARENT = 2;
}
DISPLAY_LINE
{
CHANNEL = "dataIn[4]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 6;
TREE_LEVEL = 1;
PARENT = 2;
}
DISPLAY_LINE
{
CHANNEL = "dataIn[3]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 7;
TREE_LEVEL = 1;
PARENT = 2;
}
DISPLAY_LINE
{
CHANNEL = "dataIn[2]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 8;
TREE_LEVEL = 1;
PARENT = 2;
}
DISPLAY_LINE
{
CHANNEL = "dataIn[1]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 9;
TREE_LEVEL = 1;
PARENT = 2;
}
DISPLAY_LINE
{
CHANNEL = "dataIn[0]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 10;
TREE_LEVEL = 1;
PARENT = 2;
}
DISPLAY_LINE
{
CHANNEL = "dataOut";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 11;
TREE_LEVEL = 0;
CHILDREN = 12, 13, 14, 15, 16, 17, 18, 19;
}
DISPLAY_LINE
{
CHANNEL = "dataOut[7]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 12;
TREE_LEVEL = 1;
PARENT = 11;
}
DISPLAY_LINE
{
CHANNEL = "dataOut[6]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 13;
TREE_LEVEL = 1;
PARENT = 11;
}
DISPLAY_LINE
{
CHANNEL = "dataOut[5]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 14;
TREE_LEVEL = 1;
PARENT = 11;
}
DISPLAY_LINE
{
CHANNEL = "dataOut[4]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 15;
TREE_LEVEL = 1;
PARENT = 11;
}
DISPLAY_LINE
{
CHANNEL = "dataOut[3]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 16;
TREE_LEVEL = 1;
PARENT = 11;
}
DISPLAY_LINE
{
CHANNEL = "dataOut[2]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 17;
TREE_LEVEL = 1;
PARENT = 11;
}
DISPLAY_LINE
{
CHANNEL = "dataOut[1]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 18;
TREE_LEVEL = 1;
PARENT = 11;
}
DISPLAY_LINE
{
CHANNEL = "dataOut[0]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 19;
TREE_LEVEL = 1;
PARENT = 11;
}
TIME_BAR
{
TIME = 0;
MASTER = TRUE;
}
;

140
1ano/2semestre/lsd/pratica04/RegisterDemo/RegisterDemo.bdf Normal file
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@ -0,0 +1,140 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "graphic" (version "1.4"))
(pin
(input)
(rect 232 208 400 224)
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
(text "SW[7..0]" (rect 5 0 48 11)(font "Arial" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
)
(pin
(input)
(rect 232 224 400 240)
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
(text "KEY[0]" (rect 5 0 41 13)(font "Intel Clear" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
)
(pin
(input)
(rect 232 240 400 256)
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
(text "SW[8]" (rect 5 0 39 13)(font "Intel Clear" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
)
(pin
(output)
(rect 608 208 784 224)
(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
(text "LEDR[7..0]" (rect 90 0 144 11)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
(line (pt 52 4)(pt 78 4))
(line (pt 52 12)(pt 78 12))
(line (pt 52 12)(pt 52 4))
(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
)
(symbol
(rect 408 184 600 296)
(text "Register8" (rect 5 0 53 11)(font "Arial" ))
(text "inst" (rect 8 96 26 107)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "dataIn[7..0]" (rect 0 0 55 11)(font "Arial" ))
(text "dataIn[7..0]" (rect 21 27 76 38)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 3))
)
(port
(pt 0 48)
(input)
(text "clk" (rect 0 0 15 11)(font "Arial" ))
(text "clk" (rect 21 43 36 54)(font "Arial" ))
(line (pt 0 48)(pt 16 48))
)
(port
(pt 0 64)
(input)
(text "wrEn" (rect 0 0 27 11)(font "Arial" ))
(text "wrEn" (rect 21 59 48 70)(font "Arial" ))
(line (pt 0 64)(pt 16 64))
)
(port
(pt 192 32)
(output)
(text "dataOut[7..0]" (rect 0 0 63 11)(font "Arial" ))
(text "dataOut[7..0]" (rect 118 27 181 38)(font "Arial" ))
(line (pt 192 32)(pt 176 32)(line_width 3))
)
(drawing
(rectangle (rect 16 16 176 96))
)
)
(connector
(pt 600 216)
(pt 608 216)
(bus)
)
(connector
(pt 408 216)
(pt 400 216)
(bus)
)
(connector
(pt 408 232)
(pt 400 232)
)
(connector
(pt 408 248)
(pt 400 248)
)

BIN
1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.sof Normal file
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Binary file not shown.

71
1ano/2semestre/lsd/pratica05/AccN_Demo/AccN.bsf Normal file
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@ -0,0 +1,71 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 224 128)
(text "AccN" (rect 5 0 29 12)(font "Arial" ))
(text "inst" (rect 8 96 20 108)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "dataIn[n-1..0]" (rect 0 0 49 12)(font "Arial" ))
(text "dataIn[n-1..0]" (rect 21 27 70 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 3))
)
(port
(pt 0 48)
(input)
(text "reset" (rect 0 0 20 12)(font "Arial" ))
(text "reset" (rect 21 43 41 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48)(line_width 1))
)
(port
(pt 0 64)
(input)
(text "enable" (rect 0 0 24 12)(font "Arial" ))
(text "enable" (rect 21 59 45 71)(font "Arial" ))
(line (pt 0 64)(pt 16 64)(line_width 1))
)
(port
(pt 0 80)
(input)
(text "clk" (rect 0 0 10 12)(font "Arial" ))
(text "clk" (rect 21 75 31 87)(font "Arial" ))
(line (pt 0 80)(pt 16 80)(line_width 1))
)
(port
(pt 208 32)
(output)
(text "dataOut[n-1..0]" (rect 0 0 56 12)(font "Arial" ))
(text "dataOut[n-1..0]" (rect 131 27 187 39)(font "Arial" ))
(line (pt 208 32)(pt 192 32)(line_width 3))
)
(parameter
"N"
"8"
""
(type "PARAMETER_SIGNED_DEC") )
(drawing
(rectangle (rect 16 16 192 96)(line_width 1))
)
(annotation_block (parameter)(rect 224 -64 324 16))
)

38
1ano/2semestre/lsd/pratica05/AccN_Demo/AccN.vhd Normal file
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@ -0,0 +1,38 @@
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity AccN is
generic ( N : positive := 8 );
port (
dataIn : in std_logic_vector((N-1) downto 0);
reset, enable, clk : std_logic;
dataOut : out std_logic_vector((N-1) downto 0)
);
end AccN;
architecture Behavioral of AccN is
signal s_adderOut : std_logic_vector((N-1) downto 0);
signal s_regOut : std_logic_vector((N-1) downto 0);
begin
adder : entity work.AdderN(Behavioral)
generic map ( N => N )
port map
(
operand1 => dataIn,
operand2 => s_regOut,
result => s_adderOut
);
reg : entity work.RegN(Behavioral)
generic map ( N => N )
port map
(
dataIn => s_adderOut,
reset => reset, enable => enable, clk => clk,
dataOut => s_regOut
);
dataOut <= s_regOut;
end Behavioral;

241
1ano/2semestre/lsd/pratica05/AccN_Demo/AccN_Demo.bdf Normal file
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "graphic" (version "1.4"))
(pin
(input)
(rect 280 256 448 272)
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
(text "KEY[1]" (rect 5 0 40 13)(font "Intel Clear" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
(annotation_block (location)(rect 216 272 280 288))
)
(pin
(input)
(rect 128 312 296 328)
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
(text "CLOCK_50" (rect 5 0 60 13)(font "Intel Clear" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
(annotation_block (location)(rect 216 304 280 320))
)
(pin
(input)
(rect 280 272 448 288)
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
(text "SW[17]" (rect 5 0 43 13)(font "Intel Clear" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
(annotation_block (location)(rect 216 288 280 304))
)
(pin
(input)
(rect 280 240 448 256)
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
(text "SW[16..0]" (rect 5 0 54 11)(font "Arial" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
(annotation_block (location)(rect 216 256 280 272))
)
(pin
(output)
(rect 728 240 904 256)
(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
(text "LEDR[16..0]" (rect 90 0 150 11)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
(line (pt 52 4)(pt 78 4))
(line (pt 52 12)(pt 78 12))
(line (pt 52 12)(pt 52 4))
(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
(annotation_block (location)(rect 904 256 968 272))
)
(symbol
(rect 456 248 504 280)
(text "NOT" (rect 1 0 22 10)(font "Arial" (font_size 6)))
(text "inst1" (rect 3 21 27 34)(font "Intel Clear" ))
(port
(pt 0 16)
(input)
(text "IN" (rect 2 7 16 18)(font "Courier New" (bold))(invisible))
(text "IN" (rect 2 7 16 18)(font "Courier New" (bold))(invisible))
(line (pt 0 16)(pt 13 16))
)
(port
(pt 48 16)
(output)
(text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible))
(line (pt 39 16)(pt 48 16))
)
(drawing
(line (pt 13 25)(pt 13 7))
(line (pt 13 7)(pt 31 16))
(line (pt 13 25)(pt 31 16))
(circle (rect 31 12 39 20))
)
)
(symbol
(rect 512 216 720 328)
(text "AccN" (rect 5 0 32 11)(font "Arial" ))
(text "inst" (rect 8 96 26 107)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "dataIn[n-1..0]" (rect 0 0 64 11)(font "Arial" ))
(text "dataIn[n-1..0]" (rect 21 27 85 38)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 3))
)
(port
(pt 0 48)
(input)
(text "reset" (rect 0 0 25 11)(font "Arial" ))
(text "reset" (rect 21 43 46 54)(font "Arial" ))
(line (pt 0 48)(pt 16 48))
)
(port
(pt 0 64)
(input)
(text "enable" (rect 0 0 34 11)(font "Arial" ))
(text "enable" (rect 21 59 55 70)(font "Arial" ))
(line (pt 0 64)(pt 16 64))
)
(port
(pt 0 80)
(input)
(text "clk" (rect 0 0 15 11)(font "Arial" ))
(text "clk" (rect 21 75 36 86)(font "Arial" ))
(line (pt 0 80)(pt 16 80))
)
(port
(pt 208 32)
(output)
(text "dataOut[n-1..0]" (rect 0 0 74 11)(font "Arial" ))
(text "dataOut[n-1..0]" (rect 125 27 199 38)(font "Arial" ))
(line (pt 208 32)(pt 192 32)(line_width 3))
)
(parameter
"N"
"17"
""
(type "PARAMETER_SIGNED_DEC") )
(drawing
(rectangle (rect 16 16 192 96))
)
(annotation_block (parameter)(rect 720 184 891 214))
)
(symbol
(rect 304 288 448 368)
(text "FreqDivider" (rect 5 0 64 11)(font "Arial" ))
(text "inst4" (rect 8 64 33 77)(font "Intel Clear" ))
(port
(pt 0 32)
(input)
(text "clkIn" (rect 0 0 24 11)(font "Arial" ))
(text "clkIn" (rect 21 27 45 38)(font "Arial" ))
(line (pt 0 32)(pt 16 32))
)
(port
(pt 144 32)
(output)
(text "clkOut" (rect 0 0 33 11)(font "Arial" ))
(text "clkOut" (rect 96 27 129 38)(font "Arial" ))
(line (pt 144 32)(pt 128 32))
)
(drawing
(rectangle (rect 16 16 128 64))
)
)
(connector
(pt 720 248)
(pt 728 248)
(bus)
)
(connector
(pt 512 248)
(pt 448 248)
(bus)
)
(connector
(pt 512 280)
(pt 448 280)
)
(connector
(pt 448 264)
(pt 456 264)
)
(connector
(pt 504 264)
(pt 512 264)
)
(connector
(pt 480 296)
(pt 512 296)
)
(connector
(pt 480 296)
(pt 480 320)
)
(connector
(pt 296 320)
(pt 304 320)
)
(connector
(pt 448 320)
(pt 480 320)
)

18
1ano/2semestre/lsd/pratica05/AccN_Demo/AdderN.vhd Normal file
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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity AdderN is
generic ( N : positive := 8);
port
(
operand1 : in std_logic_vector((N-1) downto 0 );
operand2 : in std_logic_vector((N-1) downto 0 ) := (others => '0');
result : out std_logic_vector((N-1) downto 0 )
);
end AdderN;
architecture Behavioral of AdderN is
begin
result <= operand1 + operand2;
end Behavioral;

44
1ano/2semestre/lsd/pratica05/AccN_Demo/FreqDivider.bsf Normal file
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@ -0,0 +1,44 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 160 96)
(text "FreqDivider" (rect 5 0 52 12)(font "Arial" ))
(text "inst" (rect 8 64 20 76)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "clkIn" (rect 0 0 17 12)(font "Arial" ))
(text "clkIn" (rect 21 27 38 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
(pt 144 32)
(output)
(text "clkOut" (rect 0 0 24 12)(font "Arial" ))
(text "clkOut" (rect 99 27 123 39)(font "Arial" ))
(line (pt 144 32)(pt 128 32)(line_width 1))
)
(drawing
(rectangle (rect 16 16 128 64)(line_width 1))
)
)

33
1ano/2semestre/lsd/pratica05/AccN_Demo/FreqDivider.vhd Normal file
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@ -0,0 +1,33 @@
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity FreqDivider is
port (clkIn : in std_logic;
clkOut : out std_logic
);
end FreqDivider;
architecture Behavioral of FreqDivider is
signal s_counter : unsigned(31 downto 0);
signal s_halfWay : unsigned(31 downto 0);
signal k : std_logic_vector(31 downto 0);
begin
k <= x"008D7840";
s_halfWay <= unsigned(k);
process(clkIn)
begin
if (rising_edge(clkIn)) then
if (s_counter = s_halfWay - 1) then
clkOut <= '0';
s_counter <= (others => '0');
else
if (s_counter = s_halfWay/2 - 1) then
clkOut <= '1';
end if;
s_counter <= s_counter + 1;
end if;
end if;
end process;
end Behavioral;

26
1ano/2semestre/lsd/pratica05/AccN_Demo/RegN.vhd Normal file
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@ -0,0 +1,26 @@
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity RegN is
generic ( N : positive := 8);
port
(
dataIn : in std_logic_vector((N-1) downto 0);
enable, reset, clk : in std_logic;
dataOut : out std_logic_vector((N-1) downto 0)
);
end RegN;
architecture Behavioral of RegN is
begin
process (clk, reset)
begin
if (reset = '1') then
dataOut <= (others => '0');
elsif (rising_edge(clk)) then
if (enable = '1') then
dataOut <= dataIn;
end if;
end if;
end process;
end Behavioral;

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1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.sof Normal file
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733
1ano/2semestre/lsd/pratica05/CmpN_Demo/Cmp8.vwf Normal file
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/*<simulation_settings>
<ftestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off CmpN_Demo -c CmpN_Demo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/Cmp8.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/Cmp8.vwf.vht"</ftestbench_cmd>
<ttestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off CmpN_Demo -c CmpN_Demo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/Cmp8.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/Cmp8.vwf.vht"</ttestbench_cmd>
<fnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/" CmpN_Demo -c CmpN_Demo</fnetlist_cmd>
<tnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/" CmpN_Demo -c CmpN_Demo</tnetlist_cmd>
<modelsim_script>onerror {exit -code 1}
vlib work
vcom -work work CmpN_Demo.vho
vcom work Cmp8.vwf.vht
vsim -novopt -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.CmpN_vhd_vec_tst
vcd file -direction CmpN_Demo.msim.vcd
vcd add -internal CmpN_vhd_vec_tst/*
vcd add -internal CmpN_vhd_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script>
<modelsim_script_timing>onerror {exit -code 1}
vlib work
vcom -work work CmpN_Demo.vho
vcom -work work Cmp8.vwf.vht
vsim -novopt -c -t 1ps -sdfmax CmpN_vhd_vec_tst/i1=CmpN_Demo_vhd.sdo -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.CmpN_vhd_vec_tst
vcd file -direction CmpN_Demo.msim.vcd
vcd add -internal CmpN_vhd_vec_tst/*
vcd add -internal CmpN_vhd_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script_timing>
<hdl_lang>vhdl</hdl_lang>
</simulation_settings>*/
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
HEADER
{
VERSION = 1;
TIME_UNIT = ns;
DATA_OFFSET = 0.0;
DATA_DURATION = 1000.0;
SIMULATION_TIME = 0.0;
GRID_PHASE = 0.0;
GRID_PERIOD = 10.0;
GRID_DUTY_CYCLE = 50;
}
SIGNAL("equal")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("input0")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = BUS;
WIDTH = 8;
LSB_INDEX = 0;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("input0[7]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "input0";
}
SIGNAL("input0[6]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "input0";
}
SIGNAL("input0[5]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "input0";
}
SIGNAL("input0[4]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "input0";
}
SIGNAL("input0[3]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "input0";
}
SIGNAL("input0[2]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "input0";
}
SIGNAL("input0[1]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "input0";
}
SIGNAL("input0[0]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "input0";
}
SIGNAL("input1")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = BUS;
WIDTH = 8;
LSB_INDEX = 0;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("input1[7]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "input1";
}
SIGNAL("input1[6]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "input1";
}
SIGNAL("input1[5]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "input1";
}
SIGNAL("input1[4]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "input1";
}
SIGNAL("input1[3]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "input1";
}
SIGNAL("input1[2]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "input1";
}
SIGNAL("input1[1]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "input1";
}
SIGNAL("input1[0]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "input1";
}
SIGNAL("ltSigned")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("ltUnsigned")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("notEqual")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
TRANSITION_LIST("equal")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("input0[7]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 80.0;
LEVEL 1 FOR 80.0;
LEVEL 0 FOR 840.0;
}
}
TRANSITION_LIST("input0[6]")
{
NODE
{
REPEAT = 1;
LEVEL 1 FOR 80.0;
LEVEL 0 FOR 80.0;
LEVEL 1 FOR 80.0;
LEVEL 0 FOR 760.0;
}
}
TRANSITION_LIST("input0[5]")
{
NODE
{
REPEAT = 1;
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LEVEL 0 FOR 80.0;
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}
TRANSITION_LIST("input0[4]")
{
NODE
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REPEAT = 1;
LEVEL 1 FOR 80.0;
LEVEL 0 FOR 80.0;
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TRANSITION_LIST("input0[3]")
{
NODE
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REPEAT = 1;
LEVEL 1 FOR 80.0;
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}
TRANSITION_LIST("input0[2]")
{
NODE
{
REPEAT = 1;
LEVEL 1 FOR 80.0;
LEVEL 0 FOR 80.0;
LEVEL 1 FOR 80.0;
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}
TRANSITION_LIST("input0[1]")
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NODE
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NODE
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}
TRANSITION_LIST("input1[7]")
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NODE
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LEVEL 1 FOR 80.0;
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}
TRANSITION_LIST("input1[6]")
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TRANSITION_LIST("input1[5]")
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LEVEL 1 FOR 80.0;
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}
TRANSITION_LIST("input1[4]")
{
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LEVEL 1 FOR 80.0;
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}
}
TRANSITION_LIST("input1[3]")
{
NODE
{
REPEAT = 1;
LEVEL 1 FOR 80.0;
LEVEL 0 FOR 920.0;
}
}
TRANSITION_LIST("input1[2]")
{
NODE
{
REPEAT = 1;
LEVEL 1 FOR 80.0;
LEVEL 0 FOR 920.0;
}
}
TRANSITION_LIST("input1[1]")
{
NODE
{
REPEAT = 1;
LEVEL 1 FOR 80.0;
LEVEL 0 FOR 920.0;
}
}
TRANSITION_LIST("input1[0]")
{
NODE
{
REPEAT = 1;
LEVEL 1 FOR 80.0;
LEVEL 0 FOR 920.0;
}
}
TRANSITION_LIST("ltSigned")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("ltUnsigned")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("notEqual")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
DISPLAY_LINE
{
CHANNEL = "input0";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 0;
TREE_LEVEL = 0;
CHILDREN = 1, 2, 3, 4, 5, 6, 7, 8;
}
DISPLAY_LINE
{
CHANNEL = "input0[7]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 1;
TREE_LEVEL = 1;
PARENT = 0;
}
DISPLAY_LINE
{
CHANNEL = "input0[6]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 2;
TREE_LEVEL = 1;
PARENT = 0;
}
DISPLAY_LINE
{
CHANNEL = "input0[5]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 3;
TREE_LEVEL = 1;
PARENT = 0;
}
DISPLAY_LINE
{
CHANNEL = "input0[4]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 4;
TREE_LEVEL = 1;
PARENT = 0;
}
DISPLAY_LINE
{
CHANNEL = "input0[3]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 5;
TREE_LEVEL = 1;
PARENT = 0;
}
DISPLAY_LINE
{
CHANNEL = "input0[2]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 6;
TREE_LEVEL = 1;
PARENT = 0;
}
DISPLAY_LINE
{
CHANNEL = "input0[1]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 7;
TREE_LEVEL = 1;
PARENT = 0;
}
DISPLAY_LINE
{
CHANNEL = "input0[0]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 8;
TREE_LEVEL = 1;
PARENT = 0;
}
DISPLAY_LINE
{
CHANNEL = "input1";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 9;
TREE_LEVEL = 0;
CHILDREN = 10, 11, 12, 13, 14, 15, 16, 17;
}
DISPLAY_LINE
{
CHANNEL = "input1[7]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 10;
TREE_LEVEL = 1;
PARENT = 9;
}
DISPLAY_LINE
{
CHANNEL = "input1[6]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 11;
TREE_LEVEL = 1;
PARENT = 9;
}
DISPLAY_LINE
{
CHANNEL = "input1[5]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 12;
TREE_LEVEL = 1;
PARENT = 9;
}
DISPLAY_LINE
{
CHANNEL = "input1[4]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 13;
TREE_LEVEL = 1;
PARENT = 9;
}
DISPLAY_LINE
{
CHANNEL = "input1[3]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 14;
TREE_LEVEL = 1;
PARENT = 9;
}
DISPLAY_LINE
{
CHANNEL = "input1[2]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 15;
TREE_LEVEL = 1;
PARENT = 9;
}
DISPLAY_LINE
{
CHANNEL = "input1[1]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 16;
TREE_LEVEL = 1;
PARENT = 9;
}
DISPLAY_LINE
{
CHANNEL = "input1[0]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 17;
TREE_LEVEL = 1;
PARENT = 9;
}
DISPLAY_LINE
{
CHANNEL = "equal";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 18;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "notEqual";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 19;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "ltSigned";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 20;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "ltUnsigned";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 21;
TREE_LEVEL = 0;
}
TIME_BAR
{
TIME = 0;
MASTER = TRUE;
}
;

78
1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN.bsf Normal file
View File

@ -0,0 +1,78 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 208 128)
(text "CmpN" (rect 5 0 32 12)(font "Arial" ))
(text "inst" (rect 8 96 20 108)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "input0[n-1..0]" (rect 0 0 48 12)(font "Arial" ))
(text "input0[n-1..0]" (rect 21 27 69 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 3))
)
(port
(pt 0 48)
(input)
(text "input1[n-1..0]" (rect 0 0 47 12)(font "Arial" ))
(text "input1[n-1..0]" (rect 21 43 68 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48)(line_width 3))
)
(port
(pt 192 32)
(output)
(text "equal" (rect 0 0 20 12)(font "Arial" ))
(text "equal" (rect 151 27 171 39)(font "Arial" ))
(line (pt 192 32)(pt 176 32)(line_width 1))
)
(port
(pt 192 48)
(output)
(text "notEqual" (rect 0 0 34 12)(font "Arial" ))
(text "notEqual" (rect 137 43 171 55)(font "Arial" ))
(line (pt 192 48)(pt 176 48)(line_width 1))
)
(port
(pt 192 64)
(output)
(text "ltSigned" (rect 0 0 29 12)(font "Arial" ))
(text "ltSigned" (rect 142 59 171 71)(font "Arial" ))
(line (pt 192 64)(pt 176 64)(line_width 1))
)
(port
(pt 192 80)
(output)
(text "ltUnsigned" (rect 0 0 40 12)(font "Arial" ))
(text "ltUnsigned" (rect 131 75 171 87)(font "Arial" ))
(line (pt 192 80)(pt 176 80)(line_width 1))
)
(parameter
"N"
"4"
""
(type "PARAMETER_SIGNED_DEC") )
(drawing
(rectangle (rect 16 16 176 96)(line_width 1))
)
(annotation_block (parameter)(rect 208 -64 308 16))
)

24
1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN.vhd Normal file
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@ -0,0 +1,24 @@
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity CmpN is
generic (N : positive := 4);
port
(
input0 : in std_logic_vector((N-1) downto 0);
input1 : in std_logic_vector((N-1) downto 0);
equal : out std_logic;
notEqual : out std_logic;
ltSigned : out std_logic;
ltUnsigned : out std_logic
);
end CmpN;
architecture Behavioral of CmpN is
begin
equal <= '1' when (input0 = input1) else '0';
notEqual <= '1' when (input0 /= input1) else '0';
ltSigned <= '1' when (signed(input0) < signed(input1)) else '0';
ltUnsigned <= '1' when (unsigned(input0) < unsigned(input1)) else '0';
end Behavioral;

390
1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.bdf Normal file
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@ -0,0 +1,390 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "graphic" (version "1.4"))
(pin
(input)
(rect 424 240 592 256)
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
(text "SW[7..4]" (rect 5 0 47 11)(font "Arial" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
(annotation_block (location)(rect 360 256 424 272))
)
(pin
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(rect 424 256 592 272)
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(text "SW[3..0]" (rect 5 0 48 13)(font "Intel Clear" ))
(pt 168 8)
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(annotation_block (location)(rect 360 272 424 288))
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(annotation_block (location)(rect 232 472 296 488))
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1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.cdf Normal file
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