[LSD] pratica01 part4 finished
This commit is contained in:
TiagoRG
parent
1ccff15a34
commit
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GPG Key ID:
DFCD48E3F420DB42
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@ -0,0 +1,383 @@
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/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and any partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Intel Program License
|
||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
the Intel FPGA IP License Agreement, or other applicable license
|
||||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details, at
|
||||
https://fpgasoftware.intel.com/eula.
|
||||
*/
|
||||
(header "graphic" (version "1.4"))
|
||||
(pin
|
||||
(input)
|
||||
(rect 120 128 288 144)
|
||||
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
|
||||
(text "input0[3..0]" (rect 5 0 65 13)(font "Intel Clear" ))
|
||||
(pt 168 8)
|
||||
(drawing
|
||||
(line (pt 84 12)(pt 109 12))
|
||||
(line (pt 84 4)(pt 109 4))
|
||||
(line (pt 113 8)(pt 168 8))
|
||||
(line (pt 84 12)(pt 84 4))
|
||||
(line (pt 109 4)(pt 113 8))
|
||||
(line (pt 109 12)(pt 113 8))
|
||||
)
|
||||
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 120 152 288 168)
|
||||
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
|
||||
(text "input1[3..0]" (rect 5 0 65 13)(font "Intel Clear" ))
|
||||
(pt 168 8)
|
||||
(drawing
|
||||
(line (pt 84 12)(pt 109 12))
|
||||
(line (pt 84 4)(pt 109 4))
|
||||
(line (pt 113 8)(pt 168 8))
|
||||
(line (pt 84 12)(pt 84 4))
|
||||
(line (pt 109 4)(pt 113 8))
|
||||
(line (pt 109 12)(pt 113 8))
|
||||
)
|
||||
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(output)
|
||||
(rect 600 296 776 312)
|
||||
(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
|
||||
(text "cmpOut" (rect 90 0 130 11)(font "Arial" ))
|
||||
(pt 0 8)
|
||||
(drawing
|
||||
(line (pt 0 8)(pt 52 8))
|
||||
(line (pt 52 4)(pt 78 4))
|
||||
(line (pt 52 12)(pt 78 12))
|
||||
(line (pt 52 12)(pt 52 4))
|
||||
(line (pt 78 4)(pt 82 8))
|
||||
(line (pt 82 8)(pt 78 12))
|
||||
(line (pt 78 12)(pt 82 8))
|
||||
)
|
||||
)
|
||||
(symbol
|
||||
(rect 296 184 344 248)
|
||||
(text "XNOR" (rect 38 1 48 30)(font "Arial" (font_size 6))(vertical))
|
||||
(text "xnor_3" (rect 1 2 12 37)(font "Arial" )(vertical))
|
||||
(port
|
||||
(pt 32 0)
|
||||
(input)
|
||||
(text "IN1" (rect 2 8 23 19)(font "Courier New" (bold))(invisible))
|
||||
(text "IN1" (rect 29 2 40 23)(font "Courier New" (bold))(vertical)(invisible))
|
||||
(line (pt 32 0)(pt 32 11))
|
||||
)
|
||||
(port
|
||||
(pt 16 0)
|
||||
(input)
|
||||
(text "IN2" (rect 2 23 23 34)(font "Courier New" (bold))(invisible))
|
||||
(text "IN2" (rect 14 2 25 23)(font "Courier New" (bold))(vertical)(invisible))
|
||||
(line (pt 16 0)(pt 16 11))
|
||||
)
|
||||
(port
|
||||
(pt 24 64)
|
||||
(output)
|
||||
(text "OUT" (rect 48 15 69 26)(font "Courier New" (bold))(invisible))
|
||||
(text "OUT" (rect 22 48 33 69)(font "Courier New" (bold))(vertical)(invisible))
|
||||
(line (pt 24 56)(pt 24 64))
|
||||
)
|
||||
(drawing
|
||||
(line (pt 35 14)(pt 35 25))
|
||||
(line (pt 12 14)(pt 12 25))
|
||||
(arc (pt 19 7)(pt 29 7)(rect 7 -14 40 19))
|
||||
(arc (pt 24 49)(pt 35 25)(rect -28 -6 35 57))
|
||||
(arc (pt 19 2)(pt 29 2)(rect 7 -19 40 14))
|
||||
(arc (pt 13 25)(pt 24 49)(rect 12 -6 75 57))
|
||||
(circle (rect 20 48 28 56))
|
||||
)
|
||||
(rotate270)
|
||||
)
|
||||
(symbol
|
||||
(rect 488 184 536 248)
|
||||
(text "XNOR" (rect 38 1 48 30)(font "Arial" (font_size 6))(vertical))
|
||||
(text "xnor_0" (rect 2 1 15 37)(font "Intel Clear" )(vertical))
|
||||
(port
|
||||
(pt 32 0)
|
||||
(input)
|
||||
(text "IN1" (rect 2 8 23 19)(font "Courier New" (bold))(invisible))
|
||||
(text "IN1" (rect 29 2 40 23)(font "Courier New" (bold))(vertical)(invisible))
|
||||
(line (pt 32 0)(pt 32 11))
|
||||
)
|
||||
(port
|
||||
(pt 16 0)
|
||||
(input)
|
||||
(text "IN2" (rect 2 23 23 34)(font "Courier New" (bold))(invisible))
|
||||
(text "IN2" (rect 14 2 25 23)(font "Courier New" (bold))(vertical)(invisible))
|
||||
(line (pt 16 0)(pt 16 11))
|
||||
)
|
||||
(port
|
||||
(pt 24 64)
|
||||
(output)
|
||||
(text "OUT" (rect 48 15 69 26)(font "Courier New" (bold))(invisible))
|
||||
(text "OUT" (rect 22 48 33 69)(font "Courier New" (bold))(vertical)(invisible))
|
||||
(line (pt 24 56)(pt 24 64))
|
||||
)
|
||||
(drawing
|
||||
(line (pt 35 14)(pt 35 25))
|
||||
(line (pt 12 14)(pt 12 25))
|
||||
(arc (pt 19 7)(pt 29 7)(rect 7 -14 40 19))
|
||||
(arc (pt 24 49)(pt 35 25)(rect -28 -6 35 57))
|
||||
(arc (pt 19 2)(pt 29 2)(rect 7 -19 40 14))
|
||||
(arc (pt 13 25)(pt 24 49)(rect 12 -6 75 57))
|
||||
(circle (rect 20 48 28 56))
|
||||
)
|
||||
(rotate270)
|
||||
)
|
||||
(symbol
|
||||
(rect 424 184 472 248)
|
||||
(text "XNOR" (rect 38 1 48 30)(font "Arial" (font_size 6))(vertical))
|
||||
(text "xnor_1" (rect 2 1 15 36)(font "Intel Clear" )(vertical))
|
||||
(port
|
||||
(pt 32 0)
|
||||
(input)
|
||||
(text "IN1" (rect 2 8 23 19)(font "Courier New" (bold))(invisible))
|
||||
(text "IN1" (rect 29 2 40 23)(font "Courier New" (bold))(vertical)(invisible))
|
||||
(line (pt 32 0)(pt 32 11))
|
||||
)
|
||||
(port
|
||||
(pt 16 0)
|
||||
(input)
|
||||
(text "IN2" (rect 2 23 23 34)(font "Courier New" (bold))(invisible))
|
||||
(text "IN2" (rect 14 2 25 23)(font "Courier New" (bold))(vertical)(invisible))
|
||||
(line (pt 16 0)(pt 16 11))
|
||||
)
|
||||
(port
|
||||
(pt 24 64)
|
||||
(output)
|
||||
(text "OUT" (rect 48 15 69 26)(font "Courier New" (bold))(invisible))
|
||||
(text "OUT" (rect 22 48 33 69)(font "Courier New" (bold))(vertical)(invisible))
|
||||
(line (pt 24 56)(pt 24 64))
|
||||
)
|
||||
(drawing
|
||||
(line (pt 35 14)(pt 35 25))
|
||||
(line (pt 12 14)(pt 12 25))
|
||||
(arc (pt 19 7)(pt 29 7)(rect 7 -14 40 19))
|
||||
(arc (pt 24 49)(pt 35 25)(rect -28 -6 35 57))
|
||||
(arc (pt 19 2)(pt 29 2)(rect 7 -19 40 14))
|
||||
(arc (pt 13 25)(pt 24 49)(rect 12 -6 75 57))
|
||||
(circle (rect 20 48 28 56))
|
||||
)
|
||||
(rotate270)
|
||||
)
|
||||
(symbol
|
||||
(rect 360 184 408 248)
|
||||
(text "XNOR" (rect 38 1 48 30)(font "Arial" (font_size 6))(vertical))
|
||||
(text "xnor_2" (rect 2 1 15 36)(font "Intel Clear" )(vertical))
|
||||
(port
|
||||
(pt 32 0)
|
||||
(input)
|
||||
(text "IN1" (rect 2 8 23 19)(font "Courier New" (bold))(invisible))
|
||||
(text "IN1" (rect 29 2 40 23)(font "Courier New" (bold))(vertical)(invisible))
|
||||
(line (pt 32 0)(pt 32 11))
|
||||
)
|
||||
(port
|
||||
(pt 16 0)
|
||||
(input)
|
||||
(text "IN2" (rect 2 23 23 34)(font "Courier New" (bold))(invisible))
|
||||
(text "IN2" (rect 14 2 25 23)(font "Courier New" (bold))(vertical)(invisible))
|
||||
(line (pt 16 0)(pt 16 11))
|
||||
)
|
||||
(port
|
||||
(pt 24 64)
|
||||
(output)
|
||||
(text "OUT" (rect 48 15 69 26)(font "Courier New" (bold))(invisible))
|
||||
(text "OUT" (rect 22 48 33 69)(font "Courier New" (bold))(vertical)(invisible))
|
||||
(line (pt 24 56)(pt 24 64))
|
||||
)
|
||||
(drawing
|
||||
(line (pt 35 14)(pt 35 25))
|
||||
(line (pt 12 14)(pt 12 25))
|
||||
(arc (pt 19 7)(pt 29 7)(rect 7 -14 40 19))
|
||||
(arc (pt 24 49)(pt 35 25)(rect -28 -6 35 57))
|
||||
(arc (pt 19 2)(pt 29 2)(rect 7 -19 40 14))
|
||||
(arc (pt 13 25)(pt 24 49)(rect 12 -6 75 57))
|
||||
(circle (rect 20 48 28 56))
|
||||
)
|
||||
(rotate270)
|
||||
)
|
||||
(symbol
|
||||
(rect 528 264 592 344)
|
||||
(text "AND4" (rect 1 0 29 10)(font "Arial" (font_size 6)))
|
||||
(text "inst" (rect 3 69 21 80)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 16)
|
||||
(input)
|
||||
(text "IN1" (rect 2 7 23 18)(font "Courier New" (bold))(invisible))
|
||||
(text "IN1" (rect 2 7 23 18)(font "Courier New" (bold))(invisible))
|
||||
(line (pt 0 16)(pt 18 16))
|
||||
)
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "IN2" (rect 2 23 23 34)(font "Courier New" (bold))(invisible))
|
||||
(text "IN2" (rect 2 23 23 34)(font "Courier New" (bold))(invisible))
|
||||
(line (pt 0 32)(pt 18 32))
|
||||
)
|
||||
(port
|
||||
(pt 0 48)
|
||||
(input)
|
||||
(text "IN3" (rect 2 39 23 50)(font "Courier New" (bold))(invisible))
|
||||
(text "IN3" (rect 2 39 23 50)(font "Courier New" (bold))(invisible))
|
||||
(line (pt 0 48)(pt 18 48))
|
||||
)
|
||||
(port
|
||||
(pt 0 64)
|
||||
(input)
|
||||
(text "IN4" (rect 2 55 23 66)(font "Courier New" (bold))(invisible))
|
||||
(text "IN4" (rect 2 55 23 66)(font "Courier New" (bold))(invisible))
|
||||
(line (pt 0 64)(pt 18 64))
|
||||
)
|
||||
(port
|
||||
(pt 64 40)
|
||||
(output)
|
||||
(text "OUT" (rect 48 31 69 42)(font "Courier New" (bold))(invisible))
|
||||
(text "OUT" (rect 48 31 69 42)(font "Courier New" (bold))(invisible))
|
||||
(line (pt 46 40)(pt 64 40))
|
||||
)
|
||||
(drawing
|
||||
(line (pt 18 28)(pt 34 28))
|
||||
(line (pt 18 52)(pt 18 28))
|
||||
(line (pt 18 67)(pt 18 13))
|
||||
(line (pt 34 53)(pt 18 53))
|
||||
(arc (pt 34 52)(pt 34 28)(rect 22 28 47 53))
|
||||
)
|
||||
)
|
||||
(connector
|
||||
(pt 592 304)
|
||||
(pt 600 304)
|
||||
)
|
||||
(connector
|
||||
(pt 512 248)
|
||||
(pt 512 280)
|
||||
)
|
||||
(connector
|
||||
(pt 512 280)
|
||||
(pt 528 280)
|
||||
)
|
||||
(connector
|
||||
(pt 448 248)
|
||||
(pt 448 296)
|
||||
)
|
||||
(connector
|
||||
(pt 448 296)
|
||||
(pt 528 296)
|
||||
)
|
||||
(connector
|
||||
(pt 384 248)
|
||||
(pt 384 312)
|
||||
)
|
||||
(connector
|
||||
(pt 384 312)
|
||||
(pt 528 312)
|
||||
)
|
||||
(connector
|
||||
(pt 320 248)
|
||||
(pt 320 328)
|
||||
)
|
||||
(connector
|
||||
(pt 320 328)
|
||||
(pt 528 328)
|
||||
)
|
||||
(connector
|
||||
(pt 288 160)
|
||||
(pt 312 160)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 312 160)
|
||||
(pt 376 160)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 376 160)
|
||||
(pt 440 160)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 440 160)
|
||||
(pt 504 160)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "input1[3]" (rect 296 127 309 175)(font "Intel Clear" )(vertical))
|
||||
(pt 312 184)
|
||||
(pt 312 160)
|
||||
)
|
||||
(connector
|
||||
(text "input1[2]" (rect 360 127 373 175)(font "Intel Clear" )(vertical))
|
||||
(pt 376 184)
|
||||
(pt 376 160)
|
||||
)
|
||||
(connector
|
||||
(text "input1[1]" (rect 424 127 437 175)(font "Intel Clear" )(vertical))
|
||||
(pt 440 184)
|
||||
(pt 440 160)
|
||||
)
|
||||
(connector
|
||||
(text "input1[0]" (rect 488 127 501 175)(font "Intel Clear" )(vertical))
|
||||
(pt 504 184)
|
||||
(pt 504 160)
|
||||
)
|
||||
(connector
|
||||
(pt 456 136)
|
||||
(pt 520 136)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 392 136)
|
||||
(pt 456 136)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 288 136)
|
||||
(pt 328 136)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 328 136)
|
||||
(pt 392 136)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(text "input0[3]" (rect 312 127 325 175)(font "Intel Clear" )(vertical))
|
||||
(pt 328 184)
|
||||
(pt 328 136)
|
||||
)
|
||||
(connector
|
||||
(text "input0[2]" (rect 376 127 389 175)(font "Intel Clear" )(vertical))
|
||||
(pt 392 184)
|
||||
(pt 392 136)
|
||||
)
|
||||
(connector
|
||||
(text "input0[1]" (rect 440 127 453 175)(font "Intel Clear" )(vertical))
|
||||
(pt 456 184)
|
||||
(pt 456 136)
|
||||
)
|
||||
(connector
|
||||
(text "input0[0]" (rect 504 127 517 175)(font "Intel Clear" )(vertical))
|
||||
(pt 520 184)
|
||||
(pt 520 136)
|
||||
)
|
||||
(junction (pt 312 160))
|
||||
(junction (pt 376 160))
|
||||
(junction (pt 440 160))
|
||||
(junction (pt 456 136))
|
||||
(junction (pt 392 136))
|
||||
(junction (pt 328 136))
|
||||
|
|
@ -0,0 +1,51 @@
|
|||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and any partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Intel Program License
|
||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
the Intel FPGA IP License Agreement, or other applicable license
|
||||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details, at
|
||||
https://fpgasoftware.intel.com/eula.
|
||||
*/
|
||||
(header "symbol" (version "1.2"))
|
||||
(symbol
|
||||
(rect 16 16 184 112)
|
||||
(text "EqCmp4" (rect 5 0 55 15)(font "Intel Clear" (font_size 8)))
|
||||
(text "inst" (rect 8 79 28 92)(font "Intel Clear" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "input0[3..0]" (rect 0 0 67 15)(font "Intel Clear" (font_size 8)))
|
||||
(text "input0[3..0]" (rect 21 27 88 42)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 32)(pt 16 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 48)
|
||||
(input)
|
||||
(text "input1[3..0]" (rect 0 0 67 15)(font "Intel Clear" (font_size 8)))
|
||||
(text "input1[3..0]" (rect 21 43 88 58)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 48)(pt 16 48)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 168 32)
|
||||
(output)
|
||||
(text "cmpOut" (rect 0 0 47 15)(font "Intel Clear" (font_size 8)))
|
||||
(text "cmpOut" (rect 100 27 147 42)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 168 32)(pt 152 32))
|
||||
)
|
||||
(drawing
|
||||
(rectangle (rect 16 16 152 80))
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,116 @@
|
|||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and any partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Intel Program License
|
||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
the Intel FPGA IP License Agreement, or other applicable license
|
||||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details, at
|
||||
https://fpgasoftware.intel.com/eula.
|
||||
*/
|
||||
(header "graphic" (version "1.4"))
|
||||
(pin
|
||||
(input)
|
||||
(rect 296 200 464 216)
|
||||
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
|
||||
(text "SW[3..0]" (rect 5 0 49 13)(font "Intel Clear" ))
|
||||
(pt 168 8)
|
||||
(drawing
|
||||
(line (pt 84 12)(pt 109 12))
|
||||
(line (pt 84 4)(pt 109 4))
|
||||
(line (pt 113 8)(pt 168 8))
|
||||
(line (pt 84 12)(pt 84 4))
|
||||
(line (pt 109 4)(pt 113 8))
|
||||
(line (pt 109 12)(pt 113 8))
|
||||
)
|
||||
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
|
||||
(annotation_block (location)(rect 232 216 296 232))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 296 216 464 232)
|
||||
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
|
||||
(text "SW[7..4]" (rect 5 0 49 13)(font "Intel Clear" ))
|
||||
(pt 168 8)
|
||||
(drawing
|
||||
(line (pt 84 12)(pt 109 12))
|
||||
(line (pt 84 4)(pt 109 4))
|
||||
(line (pt 113 8)(pt 168 8))
|
||||
(line (pt 84 12)(pt 84 4))
|
||||
(line (pt 109 4)(pt 113 8))
|
||||
(line (pt 109 12)(pt 113 8))
|
||||
)
|
||||
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
|
||||
(annotation_block (location)(rect 232 232 296 248))
|
||||
)
|
||||
(pin
|
||||
(output)
|
||||
(rect 648 200 824 216)
|
||||
(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
|
||||
(text "LEDG[0]" (rect 90 0 132 11)(font "Arial" ))
|
||||
(pt 0 8)
|
||||
(drawing
|
||||
(line (pt 0 8)(pt 52 8))
|
||||
(line (pt 52 4)(pt 78 4))
|
||||
(line (pt 52 12)(pt 78 12))
|
||||
(line (pt 52 12)(pt 52 4))
|
||||
(line (pt 78 4)(pt 82 8))
|
||||
(line (pt 82 8)(pt 78 12))
|
||||
(line (pt 78 12)(pt 82 8))
|
||||
)
|
||||
(annotation_block (location)(rect 824 216 880 232))
|
||||
)
|
||||
(symbol
|
||||
(rect 472 176 640 272)
|
||||
(text "EqCmp4" (rect 5 0 55 15)(font "Intel Clear" (font_size 8)))
|
||||
(text "inst" (rect 8 79 28 92)(font "Intel Clear" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "input0[3..0]" (rect 0 0 67 15)(font "Intel Clear" (font_size 8)))
|
||||
(text "input0[3..0]" (rect 21 27 88 42)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 32)(pt 16 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 48)
|
||||
(input)
|
||||
(text "input1[3..0]" (rect 0 0 67 15)(font "Intel Clear" (font_size 8)))
|
||||
(text "input1[3..0]" (rect 21 43 88 58)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 0 48)(pt 16 48)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 168 32)
|
||||
(output)
|
||||
(text "cmpOut" (rect 0 0 47 15)(font "Intel Clear" (font_size 8)))
|
||||
(text "cmpOut" (rect 100 27 147 42)(font "Intel Clear" (font_size 8)))
|
||||
(line (pt 168 32)(pt 152 32))
|
||||
)
|
||||
(drawing
|
||||
(rectangle (rect 16 16 152 80))
|
||||
)
|
||||
)
|
||||
(connector
|
||||
(pt 464 208)
|
||||
(pt 472 208)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 464 224)
|
||||
(pt 472 224)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 640 208)
|
||||
(pt 648 208)
|
||||
)
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions
|
||||
# and other software and tools, and any partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Intel Program License
|
||||
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
# the Intel FPGA IP License Agreement, or other applicable license
|
||||
# agreement, including, without limitation, that your use is for
|
||||
# the sole purpose of programming logic devices manufactured by
|
||||
# Intel and sold by Intel or its authorized distributors. Please
|
||||
# refer to the applicable agreement for further details, at
|
||||
# https://fpgasoftware.intel.com/eula.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus Prime
|
||||
# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
||||
# Date created = 17:39:56 March 07, 2023
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
QUARTUS_VERSION = "20.1"
|
||||
DATE = "17:39:56 March 07, 2023"
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "EqCmpDemo"
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,60 @@
|
|||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions
|
||||
# and other software and tools, and any partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Intel Program License
|
||||
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
# the Intel FPGA IP License Agreement, or other applicable license
|
||||
# agreement, including, without limitation, that your use is for
|
||||
# the sole purpose of programming logic devices manufactured by
|
||||
# Intel and sold by Intel or its authorized distributors. Please
|
||||
# refer to the applicable agreement for further details, at
|
||||
# https://fpgasoftware.intel.com/eula.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus Prime
|
||||
# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
||||
# Date created = 17:39:56 March 07, 2023
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Notes:
|
||||
#
|
||||
# 1) The default values for assignments are stored in the file:
|
||||
# EqCmpDemo_assignment_defaults.qdf
|
||||
# If this file doesn't exist, see file:
|
||||
# assignment_defaults.qdf
|
||||
#
|
||||
# 2) Altera recommends that you do not modify this file. This
|
||||
# file is updated automatically by the Quartus Prime software
|
||||
# and any changes you make may be lost or overwritten.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
|
||||
set_global_assignment -name FAMILY "Cyclone IV E"
|
||||
set_global_assignment -name DEVICE EP4CE115F29C7
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY EqCmpDemo
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:39:56 MARCH 07, 2023"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
|
||||
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
|
||||
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
|
||||
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
|
||||
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
|
||||
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
|
||||
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
|
||||
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
|
||||
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
|
||||
set_global_assignment -name BDF_FILE EqCmp4.bdf
|
||||
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
|
||||
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||||
Binary file not shown.
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Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1,7 @@
|
|||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678212363509 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678212363509 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 7 18:06:03 2023 " "Processing started: Tue Mar 7 18:06:03 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678212363509 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1678212363509 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off EqCmpDemo -c EqCmpDemo " "Command: quartus_asm --read_settings_files=off --write_settings_files=off EqCmpDemo -c EqCmpDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1678212363509 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1678212363657 ""}
|
||||
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1678212365227 ""}
|
||||
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1678212365296 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "365 " "Peak virtual memory: 365 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678212365516 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 7 18:06:05 2023 " "Processing ended: Tue Mar 7 18:06:05 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678212365516 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678212365516 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678212365516 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1678212365516 ""}
|
||||
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1,5 @@
|
|||
<?xml version="1.0" ?>
|
||||
<LOG_ROOT>
|
||||
<PROJECT NAME="EqCmpDemo">
|
||||
</PROJECT>
|
||||
</LOG_ROOT>
|
||||
Binary file not shown.
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Binary file not shown.
|
|
@ -0,0 +1,115 @@
|
|||
v1
|
||||
IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
|
||||
IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
|
||||
IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
|
||||
IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
|
||||
IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
|
||||
IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
|
||||
IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
|
||||
IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
|
||||
IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
|
||||
IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
|
||||
IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
|
||||
IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
|
||||
IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
|
||||
IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
|
||||
IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
|
||||
IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
|
||||
IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
|
||||
IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
|
||||
IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
|
||||
IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
|
||||
IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
|
||||
IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
|
||||
IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
|
||||
IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
|
||||
IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
|
||||
IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
|
||||
IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
|
||||
IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,,
|
||||
IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,22 I/O(s) were assigned a toggle rate,
|
||||
IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,22 I/O(s) were assigned a toggle rate,
|
||||
IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
|
||||
IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000001;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000047;IO_000046;IO_000045;IO_000027;IO_000026;IO_000024;IO_000023;IO_000022;IO_000021;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000033;IO_000034;IO_000042,
|
||||
IO_RULES_MATRIX,Total Pass,0;9;9;0;0;73;9;0;0;0;0;0;0;1;0;0;0;72;1;0;72;0;0;1;0;73;73;73;0;0,
|
||||
IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
|
||||
IO_RULES_MATRIX,Total Inapplicable,73;64;64;73;73;0;64;73;73;73;73;73;73;72;73;73;73;1;72;73;1;73;73;72;73;0;0;0;73;73,
|
||||
IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
|
||||
IO_RULES_MATRIX,LEDG[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,SW[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,SW[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,SW[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,SW[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,SW[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,SW[7],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,SW[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,SW[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,AUD_ADCDAT,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,CLOCK2_50,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,CLOCK3_50,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,CLOCK_50,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,ENET0_INT_N,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,ENET0_LINK100,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,ENET0_MDIO,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,ENET0_RX_CLK,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,ENET0_RX_COL,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,ENET0_RX_CRS,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,ENET0_RX_DATA[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,ENET0_RX_DATA[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,ENET0_RX_DATA[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,ENET0_RX_DATA[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,ENET0_RX_DV,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,ENET0_RX_ER,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,ENET0_TX_CLK,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,ENET1_INT_N,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,ENET1_LINK100,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,ENET1_MDIO,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,ENET1_RX_CLK,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,ENET1_RX_COL,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,ENET1_RX_CRS,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,ENET1_RX_DATA[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,ENET1_RX_DATA[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,ENET1_RX_DATA[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,ENET1_RX_DATA[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,ENET1_RX_DV,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,ENET1_RX_ER,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,ENET1_TX_CLK,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,ENETCLK_25,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,FL_RY,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,HSMC_CLKIN0,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,IRDA_RXD,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,KEY[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,KEY[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,KEY[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,KEY[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,OTG_INT,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,SD_WP_N,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,SMA_CLKIN,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,SW[10],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,SW[11],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,SW[12],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,SW[13],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,SW[14],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,SW[15],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,SW[16],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,SW[17],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,SW[8],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,SW[9],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,TD_CLK27,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,TD_DATA[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,TD_DATA[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,TD_DATA[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,TD_DATA[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,TD_DATA[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,TD_DATA[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,TD_DATA[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,TD_DATA[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,TD_HS,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,TD_VS,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,UART_RTS,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,UART_RXD,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_SUMMARY,Total I/O Rules,30,
|
||||
IO_RULES_SUMMARY,Number of I/O Rules Passed,12,
|
||||
IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
|
||||
IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
|
||||
IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,18,
|
||||
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|
@ -0,0 +1,3 @@
|
|||
Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
||||
Version_Index = 520278016
|
||||
Creation_Time = Tue Mar 7 18:59:33 2023
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678212368198 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678212368198 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 7 18:06:08 2023 " "Processing started: Tue Mar 7 18:06:08 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678212368198 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1678212368198 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off EqCmpDemo -c EqCmpDemo " "Command: quartus_eda --read_settings_files=off --write_settings_files=off EqCmpDemo -c EqCmpDemo" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1678212368198 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1678212368373 ""}
|
||||
{ "Info" "IWSC_DONE_HDL_GENERATION" "EqCmpDemo.vho /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/simulation/modelsim/ simulation " "Generated file EqCmpDemo.vho in folder \"/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1678212368407 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "614 " "Peak virtual memory: 614 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678212368422 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 7 18:06:08 2023 " "Processing ended: Tue Mar 7 18:06:08 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678212368422 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678212368422 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678212368422 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1678212368422 ""}
|
||||
File diff suppressed because one or more lines are too long
|
|
@ -0,0 +1,24 @@
|
|||
|EqCmpDemo
|
||||
LEDG[0] <= EqCmp4:inst.cmpOut
|
||||
SW[0] => EqCmp4:inst.input0[0]
|
||||
SW[1] => EqCmp4:inst.input0[1]
|
||||
SW[2] => EqCmp4:inst.input0[2]
|
||||
SW[3] => EqCmp4:inst.input0[3]
|
||||
SW[4] => EqCmp4:inst.input1[0]
|
||||
SW[5] => EqCmp4:inst.input1[1]
|
||||
SW[6] => EqCmp4:inst.input1[2]
|
||||
SW[7] => EqCmp4:inst.input1[3]
|
||||
|
||||
|
||||
|EqCmpDemo|EqCmp4:inst
|
||||
cmpOut <= inst.DB_MAX_OUTPUT_PORT_TYPE
|
||||
input0[0] => xnor_0.IN0
|
||||
input0[1] => xnor_1.IN0
|
||||
input0[2] => xnor_2.IN0
|
||||
input0[3] => xnor_3.IN0
|
||||
input1[0] => xnor_0.IN1
|
||||
input1[1] => xnor_1.IN1
|
||||
input1[2] => xnor_2.IN1
|
||||
input1[3] => xnor_3.IN1
|
||||
|
||||
|
||||
Binary file not shown.
|
|
@ -0,0 +1,34 @@
|
|||
<TABLE>
|
||||
<TR bgcolor="#C0C0C0">
|
||||
<TH>Hierarchy</TH>
|
||||
<TH>Input</TH>
|
||||
<TH>Constant Input</TH>
|
||||
<TH>Unused Input</TH>
|
||||
<TH>Floating Input</TH>
|
||||
<TH>Output</TH>
|
||||
<TH>Constant Output</TH>
|
||||
<TH>Unused Output</TH>
|
||||
<TH>Floating Output</TH>
|
||||
<TH>Bidir</TH>
|
||||
<TH>Constant Bidir</TH>
|
||||
<TH>Unused Bidir</TH>
|
||||
<TH>Input only Bidir</TH>
|
||||
<TH>Output only Bidir</TH>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >inst</TD>
|
||||
<TD >8</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >1</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
</TABLE>
|
||||
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|
|
@ -0,0 +1,7 @@
|
|||
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Legal Partition Candidates ;
|
||||
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
|
||||
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
|
||||
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
|
||||
; inst ; 8 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
|
||||
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|
|
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|
|||
v1
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678212348006 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678212348007 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 7 18:05:47 2023 " "Processing started: Tue Mar 7 18:05:47 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678212348007 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678212348007 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off EqCmpDemo -c EqCmpDemo " "Command: quartus_map --read_settings_files=on --write_settings_files=off EqCmpDemo -c EqCmpDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678212348007 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1678212348170 ""}
|
||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1678212348170 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "EqCmp4.bdf 1 1 " "Found 1 design units, including 1 entities, in source file EqCmp4.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 EqCmp4 " "Found entity 1: EqCmp4" { } { { "EqCmp4.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmp4.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678212353697 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678212353697 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "EqCmpDemo.bdf 1 1 " "Found 1 design units, including 1 entities, in source file EqCmpDemo.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 EqCmpDemo " "Found entity 1: EqCmpDemo" { } { { "EqCmpDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678212353698 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678212353698 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_TOP" "EqCmpDemo " "Elaborating entity \"EqCmpDemo\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1678212353772 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "EqCmp4 EqCmp4:inst " "Elaborating entity \"EqCmp4\" for hierarchy \"EqCmp4:inst\"" { } { { "EqCmpDemo.bdf" "inst" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.bdf" { { 176 472 640 272 "inst" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678212353784 ""}
|
||||
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1678212354268 ""}
|
||||
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1678212354636 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678212354636 ""}
|
||||
{ "Info" "ICUT_CUT_TM_SUMMARY" "12 " "Implemented 12 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "8 " "Implemented 8 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1678212354880 ""} { "Info" "ICUT_CUT_TM_OPINS" "1 " "Implemented 1 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1678212354880 ""} { "Info" "ICUT_CUT_TM_LCELLS" "3 " "Implemented 3 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1678212354880 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1678212354880 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "403 " "Peak virtual memory: 403 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678212354885 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 7 18:05:54 2023 " "Processing ended: Tue Mar 7 18:05:54 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678212354885 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678212354885 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:17 " "Total CPU time (on all processors): 00:00:17" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678212354885 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1678212354885 ""}
|
||||
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|
|
@ -0,0 +1 @@
|
|||
v1
|
||||
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|
|
@ -0,0 +1 @@
|
|||
DONE
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678212366574 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678212366575 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 7 18:06:06 2023 " "Processing started: Tue Mar 7 18:06:06 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678212366575 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1678212366575 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta EqCmpDemo -c EqCmpDemo " "Command: quartus_sta EqCmpDemo -c EqCmpDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1678212366575 ""}
|
||||
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1678212366599 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1678212366685 ""}
|
||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1678212366685 ""}
|
||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678212366739 ""}
|
||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678212366739 ""}
|
||||
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "EqCmpDemo.sdc " "Synopsys Design Constraints File file not found: 'EqCmpDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1678212367062 ""}
|
||||
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678212367062 ""}
|
||||
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1678212367062 ""}
|
||||
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1678212367063 ""}
|
||||
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1678212367063 ""}
|
||||
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678212367063 ""}
|
||||
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1678212367063 ""}
|
||||
{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1678212367067 ""}
|
||||
{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1678212367068 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678212367069 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678212367072 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678212367072 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678212367073 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678212367073 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678212367074 ""}
|
||||
{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1678212367075 ""}
|
||||
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1678212367091 ""}
|
||||
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1678212367348 ""}
|
||||
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678212367362 ""}
|
||||
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1678212367362 ""}
|
||||
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1678212367362 ""}
|
||||
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678212367362 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678212367363 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678212367364 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678212367364 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678212367364 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678212367365 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678212367365 ""}
|
||||
{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1678212367366 ""}
|
||||
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678212367412 ""}
|
||||
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1678212367412 ""}
|
||||
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1678212367413 ""}
|
||||
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678212367413 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678212367414 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678212367415 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678212367416 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678212367416 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678212367417 ""}
|
||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1678212367647 ""}
|
||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1678212367648 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "533 " "Peak virtual memory: 533 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678212367658 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 7 18:06:07 2023 " "Processing ended: Tue Mar 7 18:06:07 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678212367658 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678212367658 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678212367658 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1678212367658 ""}
|
||||
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|
|
@ -0,0 +1,4 @@
|
|||
start_full_compilation:s
|
||||
start_assembler:s-start_full_compilation
|
||||
start_timing_analyzer:s-start_full_compilation
|
||||
start_eda_netlist_writer:s-start_full_compilation
|
||||
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|
|
@ -0,0 +1,45 @@
|
|||
{
|
||||
"partitions" : [
|
||||
{
|
||||
"name" : "Top",
|
||||
"pins" : [
|
||||
{
|
||||
"name" : "LEDG[0]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "SW[4]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "SW[5]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "SW[1]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "SW[0]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "SW[6]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "SW[7]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "SW[3]",
|
||||
"strict" : false
|
||||
},
|
||||
{
|
||||
"name" : "SW[2]",
|
||||
"strict" : false
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
}
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
This folder contains data for incremental compilation.
|
||||
|
||||
The compiled_partitions sub-folder contains previous compilation results for each partition.
|
||||
As long as this folder is preserved, incremental compilation results from earlier compiles
|
||||
can be re-used. To perform a clean compilation from source files for all partitions, both
|
||||
the db and incremental_db folder should be removed.
|
||||
|
||||
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
|
||||
As long as this folder is preserved, imported partitions will be automatically re-imported
|
||||
when the db or incremental_db/compiled_partitions folders are removed.
|
||||
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
||||
Version_Index = 520278016
|
||||
Creation_Time = Tue Mar 7 18:05:53 2023
|
||||
Binary file not shown.
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Binary file not shown.
|
|
@ -0,0 +1 @@
|
|||
v1
|
||||
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|
|
@ -0,0 +1 @@
|
|||
c5eb7f6cdd530884c3b884e0a3668ea4
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,92 @@
|
|||
Assembler report for EqCmpDemo
|
||||
Tue Mar 7 18:06:05 2023
|
||||
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
||||
|
||||
|
||||
---------------------
|
||||
; Table of Contents ;
|
||||
---------------------
|
||||
1. Legal Notice
|
||||
2. Assembler Summary
|
||||
3. Assembler Settings
|
||||
4. Assembler Generated Files
|
||||
5. Assembler Device Options: EqCmpDemo.sof
|
||||
6. Assembler Messages
|
||||
|
||||
|
||||
|
||||
----------------
|
||||
; Legal Notice ;
|
||||
----------------
|
||||
Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and any partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Intel Program License
|
||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
the Intel FPGA IP License Agreement, or other applicable license
|
||||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details, at
|
||||
https://fpgasoftware.intel.com/eula.
|
||||
|
||||
|
||||
|
||||
+---------------------------------------------------------------+
|
||||
; Assembler Summary ;
|
||||
+-----------------------+---------------------------------------+
|
||||
; Assembler Status ; Successful - Tue Mar 7 18:06:05 2023 ;
|
||||
; Revision Name ; EqCmpDemo ;
|
||||
; Top-level Entity Name ; EqCmpDemo ;
|
||||
; Family ; Cyclone IV E ;
|
||||
; Device ; EP4CE115F29C7 ;
|
||||
+-----------------------+---------------------------------------+
|
||||
|
||||
|
||||
+----------------------------------+
|
||||
; Assembler Settings ;
|
||||
+--------+---------+---------------+
|
||||
; Option ; Setting ; Default Value ;
|
||||
+--------+---------+---------------+
|
||||
|
||||
|
||||
+------------------------------------------------------------------------------------------------+
|
||||
; Assembler Generated Files ;
|
||||
+------------------------------------------------------------------------------------------------+
|
||||
; File Name ;
|
||||
+------------------------------------------------------------------------------------------------+
|
||||
; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.sof ;
|
||||
+------------------------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
+-----------------------------------------+
|
||||
; Assembler Device Options: EqCmpDemo.sof ;
|
||||
+----------------+------------------------+
|
||||
; Option ; Setting ;
|
||||
+----------------+------------------------+
|
||||
; JTAG usercode ; 0x0056272C ;
|
||||
; Checksum ; 0x0056272C ;
|
||||
+----------------+------------------------+
|
||||
|
||||
|
||||
+--------------------+
|
||||
; Assembler Messages ;
|
||||
+--------------------+
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus Prime Assembler
|
||||
Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
||||
Info: Processing started: Tue Mar 7 18:06:03 2023
|
||||
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off EqCmpDemo -c EqCmpDemo
|
||||
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
||||
Info (115031): Writing out detailed assembly data for power analysis
|
||||
Info (115030): Assembler is generating device programming files
|
||||
Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
|
||||
Info: Peak virtual memory: 365 megabytes
|
||||
Info: Processing ended: Tue Mar 7 18:06:05 2023
|
||||
Info: Elapsed time: 00:00:02
|
||||
Info: Total CPU time (on all processors): 00:00:02
|
||||
|
||||
|
||||
|
|
@ -0,0 +1 @@
|
|||
Tue Mar 7 18:06:09 2023
|
||||
|
|
@ -0,0 +1,94 @@
|
|||
EDA Netlist Writer report for EqCmpDemo
|
||||
Tue Mar 7 18:06:08 2023
|
||||
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
||||
|
||||
|
||||
---------------------
|
||||
; Table of Contents ;
|
||||
---------------------
|
||||
1. Legal Notice
|
||||
2. EDA Netlist Writer Summary
|
||||
3. Simulation Settings
|
||||
4. Simulation Generated Files
|
||||
5. EDA Netlist Writer Messages
|
||||
|
||||
|
||||
|
||||
----------------
|
||||
; Legal Notice ;
|
||||
----------------
|
||||
Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and any partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Intel Program License
|
||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
the Intel FPGA IP License Agreement, or other applicable license
|
||||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details, at
|
||||
https://fpgasoftware.intel.com/eula.
|
||||
|
||||
|
||||
|
||||
+-------------------------------------------------------------------+
|
||||
; EDA Netlist Writer Summary ;
|
||||
+---------------------------+---------------------------------------+
|
||||
; EDA Netlist Writer Status ; Successful - Tue Mar 7 18:06:08 2023 ;
|
||||
; Revision Name ; EqCmpDemo ;
|
||||
; Top-level Entity Name ; EqCmpDemo ;
|
||||
; Family ; Cyclone IV E ;
|
||||
; Simulation Files Creation ; Successful ;
|
||||
+---------------------------+---------------------------------------+
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------------------------------------------------------+
|
||||
; Simulation Settings ;
|
||||
+---------------------------------------------------------------------------------------------------+------------------------+
|
||||
; Option ; Setting ;
|
||||
+---------------------------------------------------------------------------------------------------+------------------------+
|
||||
; Tool Name ; ModelSim-Altera (VHDL) ;
|
||||
; Generate functional simulation netlist ; On ;
|
||||
; Truncate long hierarchy paths ; Off ;
|
||||
; Map illegal HDL characters ; Off ;
|
||||
; Flatten buses into individual nodes ; Off ;
|
||||
; Maintain hierarchy ; Off ;
|
||||
; Bring out device-wide set/reset signals as ports ; Off ;
|
||||
; Enable glitch filtering ; Off ;
|
||||
; Do not write top level VHDL entity ; Off ;
|
||||
; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ;
|
||||
; Architecture name in VHDL output netlist ; structure ;
|
||||
; Generate third-party EDA tool command script for RTL functional simulation ; Off ;
|
||||
; Generate third-party EDA tool command script for gate-level simulation ; Off ;
|
||||
+---------------------------------------------------------------------------------------------------+------------------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------------------------------------------+
|
||||
; Simulation Generated Files ;
|
||||
+-------------------------------------------------------------------------------------------------------+
|
||||
; Generated Files ;
|
||||
+-------------------------------------------------------------------------------------------------------+
|
||||
; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/simulation/modelsim/EqCmpDemo.vho ;
|
||||
+-------------------------------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
+-----------------------------+
|
||||
; EDA Netlist Writer Messages ;
|
||||
+-----------------------------+
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus Prime EDA Netlist Writer
|
||||
Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
||||
Info: Processing started: Tue Mar 7 18:06:08 2023
|
||||
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off EqCmpDemo -c EqCmpDemo
|
||||
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
||||
Info (204019): Generated file EqCmpDemo.vho in folder "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/simulation/modelsim/" for EDA simulation tool
|
||||
Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
|
||||
Info: Peak virtual memory: 614 megabytes
|
||||
Info: Processing ended: Tue Mar 7 18:06:08 2023
|
||||
Info: Elapsed time: 00:00:00
|
||||
Info: Total CPU time (on all processors): 00:00:00
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,8 @@
|
|||
Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
|
||||
Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
|
||||
Extra Info (176236): Started Fast Input/Output/OE register processing
|
||||
Extra Info (176237): Finished Fast Input/Output/OE register processing
|
||||
Extra Info (176238): Start inferring scan chains for DSP blocks
|
||||
Extra Info (176239): Inferring scan chains for DSP blocks is complete
|
||||
Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
|
||||
Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
Fitter Status : Successful - Tue Mar 7 18:06:02 2023
|
||||
Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
||||
Revision Name : EqCmpDemo
|
||||
Top-level Entity Name : EqCmpDemo
|
||||
Family : Cyclone IV E
|
||||
Device : EP4CE115F29C7
|
||||
Timing Models : Final
|
||||
Total logic elements : 3 / 114,480 ( < 1 % )
|
||||
Total combinational functions : 3 / 114,480 ( < 1 % )
|
||||
Dedicated logic registers : 0 / 114,480 ( 0 % )
|
||||
Total registers : 0
|
||||
Total pins : 73 / 529 ( 14 % )
|
||||
Total virtual pins : 0
|
||||
Total memory bits : 0 / 3,981,312 ( 0 % )
|
||||
Embedded Multiplier 9-bit elements : 0 / 532 ( 0 % )
|
||||
Total PLLs : 0 / 4 ( 0 % )
|
||||
|
|
@ -0,0 +1,136 @@
|
|||
Flow report for EqCmpDemo
|
||||
Tue Mar 7 18:06:08 2023
|
||||
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
||||
|
||||
|
||||
---------------------
|
||||
; Table of Contents ;
|
||||
---------------------
|
||||
1. Legal Notice
|
||||
2. Flow Summary
|
||||
3. Flow Settings
|
||||
4. Flow Non-Default Global Settings
|
||||
5. Flow Elapsed Time
|
||||
6. Flow OS Summary
|
||||
7. Flow Log
|
||||
8. Flow Messages
|
||||
9. Flow Suppressed Messages
|
||||
|
||||
|
||||
|
||||
----------------
|
||||
; Legal Notice ;
|
||||
----------------
|
||||
Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and any partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Intel Program License
|
||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
the Intel FPGA IP License Agreement, or other applicable license
|
||||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details, at
|
||||
https://fpgasoftware.intel.com/eula.
|
||||
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------------+
|
||||
; Flow Summary ;
|
||||
+------------------------------------+---------------------------------------------+
|
||||
; Flow Status ; Successful - Tue Mar 7 18:06:08 2023 ;
|
||||
; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
|
||||
; Revision Name ; EqCmpDemo ;
|
||||
; Top-level Entity Name ; EqCmpDemo ;
|
||||
; Family ; Cyclone IV E ;
|
||||
; Device ; EP4CE115F29C7 ;
|
||||
; Timing Models ; Final ;
|
||||
; Total logic elements ; 3 / 114,480 ( < 1 % ) ;
|
||||
; Total combinational functions ; 3 / 114,480 ( < 1 % ) ;
|
||||
; Dedicated logic registers ; 0 / 114,480 ( 0 % ) ;
|
||||
; Total registers ; 0 ;
|
||||
; Total pins ; 73 / 529 ( 14 % ) ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; Total memory bits ; 0 / 3,981,312 ( 0 % ) ;
|
||||
; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ;
|
||||
; Total PLLs ; 0 / 4 ( 0 % ) ;
|
||||
+------------------------------------+---------------------------------------------+
|
||||
|
||||
|
||||
+-----------------------------------------+
|
||||
; Flow Settings ;
|
||||
+-------------------+---------------------+
|
||||
; Option ; Setting ;
|
||||
+-------------------+---------------------+
|
||||
; Start date & time ; 03/07/2023 18:05:48 ;
|
||||
; Main task ; Compilation ;
|
||||
; Revision Name ; EqCmpDemo ;
|
||||
+-------------------+---------------------+
|
||||
|
||||
|
||||
+------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Flow Non-Default Global Settings ;
|
||||
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
|
||||
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
|
||||
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
|
||||
; COMPILER_SIGNATURE_ID ; 198516037997543.167821234811082 ; -- ; -- ; -- ;
|
||||
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
|
||||
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
|
||||
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
|
||||
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_symbol ;
|
||||
; EDA_OUTPUT_DATA_FORMAT ; Vhdl ; -- ; -- ; eda_simulation ;
|
||||
; EDA_SIMULATION_TOOL ; ModelSim-Altera (VHDL) ; <None> ; -- ; -- ;
|
||||
; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
|
||||
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
|
||||
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
|
||||
; NOMINAL_CORE_SUPPLY_VOLTAGE ; 1.2V ; -- ; -- ; -- ;
|
||||
; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
|
||||
; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
|
||||
; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
|
||||
; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ;
|
||||
; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ;
|
||||
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
|
||||
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------------------------------------------------+
|
||||
; Flow Elapsed Time ;
|
||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
|
||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
; Analysis & Synthesis ; 00:00:07 ; 1.0 ; 399 MB ; 00:00:17 ;
|
||||
; Fitter ; 00:00:07 ; 1.0 ; 1155 MB ; 00:00:10 ;
|
||||
; Assembler ; 00:00:02 ; 1.0 ; 365 MB ; 00:00:02 ;
|
||||
; Timing Analyzer ; 00:00:01 ; 1.0 ; 533 MB ; 00:00:01 ;
|
||||
; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 614 MB ; 00:00:00 ;
|
||||
; Total ; 00:00:17 ; -- ; -- ; 00:00:30 ;
|
||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------------------+
|
||||
; Flow OS Summary ;
|
||||
+----------------------+------------------+----------------+------------+----------------+
|
||||
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
|
||||
+----------------------+------------------+----------------+------------+----------------+
|
||||
; Analysis & Synthesis ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
|
||||
; Fitter ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
|
||||
; Assembler ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
|
||||
; Timing Analyzer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
|
||||
; EDA Netlist Writer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
|
||||
+----------------------+------------------+----------------+------------+----------------+
|
||||
|
||||
|
||||
------------
|
||||
; Flow Log ;
|
||||
------------
|
||||
quartus_map --read_settings_files=on --write_settings_files=off EqCmpDemo -c EqCmpDemo
|
||||
quartus_fit --read_settings_files=off --write_settings_files=off EqCmpDemo -c EqCmpDemo
|
||||
quartus_asm --read_settings_files=off --write_settings_files=off EqCmpDemo -c EqCmpDemo
|
||||
quartus_sta EqCmpDemo -c EqCmpDemo
|
||||
quartus_eda --read_settings_files=off --write_settings_files=off EqCmpDemo -c EqCmpDemo
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
<sld_project_info>
|
||||
<project>
|
||||
<hash md5_digest_80b="a87c89fd9880e5a7dded"/>
|
||||
</project>
|
||||
<file_info>
|
||||
<file device="EP4CE115F29C7" path="EqCmpDemo.sof" usercode="0xFFFFFFFF"/>
|
||||
</file_info>
|
||||
</sld_project_info>
|
||||
|
|
@ -0,0 +1,287 @@
|
|||
Analysis & Synthesis report for EqCmpDemo
|
||||
Tue Mar 7 18:05:54 2023
|
||||
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
||||
|
||||
|
||||
---------------------
|
||||
; Table of Contents ;
|
||||
---------------------
|
||||
1. Legal Notice
|
||||
2. Analysis & Synthesis Summary
|
||||
3. Analysis & Synthesis Settings
|
||||
4. Parallel Compilation
|
||||
5. Analysis & Synthesis Source Files Read
|
||||
6. Analysis & Synthesis Resource Usage Summary
|
||||
7. Analysis & Synthesis Resource Utilization by Entity
|
||||
8. General Register Statistics
|
||||
9. Post-Synthesis Netlist Statistics for Top Partition
|
||||
10. Elapsed Time Per Partition
|
||||
11. Analysis & Synthesis Messages
|
||||
|
||||
|
||||
|
||||
----------------
|
||||
; Legal Notice ;
|
||||
----------------
|
||||
Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and any partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Intel Program License
|
||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
the Intel FPGA IP License Agreement, or other applicable license
|
||||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details, at
|
||||
https://fpgasoftware.intel.com/eula.
|
||||
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Summary ;
|
||||
+------------------------------------+---------------------------------------------+
|
||||
; Analysis & Synthesis Status ; Successful - Tue Mar 7 18:05:54 2023 ;
|
||||
; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
|
||||
; Revision Name ; EqCmpDemo ;
|
||||
; Top-level Entity Name ; EqCmpDemo ;
|
||||
; Family ; Cyclone IV E ;
|
||||
; Total logic elements ; 3 ;
|
||||
; Total combinational functions ; 3 ;
|
||||
; Dedicated logic registers ; 0 ;
|
||||
; Total registers ; 0 ;
|
||||
; Total pins ; 9 ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; Total memory bits ; 0 ;
|
||||
; Embedded Multiplier 9-bit elements ; 0 ;
|
||||
; Total PLLs ; 0 ;
|
||||
+------------------------------------+---------------------------------------------+
|
||||
|
||||
|
||||
+------------------------------------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Settings ;
|
||||
+------------------------------------------------------------------+--------------------+--------------------+
|
||||
; Option ; Setting ; Default Value ;
|
||||
+------------------------------------------------------------------+--------------------+--------------------+
|
||||
; Device ; EP4CE115F29C7 ; ;
|
||||
; Top-level entity name ; EqCmpDemo ; EqCmpDemo ;
|
||||
; Family name ; Cyclone IV E ; Cyclone V ;
|
||||
; Use smart compilation ; Off ; Off ;
|
||||
; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
|
||||
; Enable compact report table ; Off ; Off ;
|
||||
; Restructure Multiplexers ; Auto ; Auto ;
|
||||
; Create Debugging Nodes for IP Cores ; Off ; Off ;
|
||||
; Preserve fewer node names ; On ; On ;
|
||||
; Intel FPGA IP Evaluation Mode ; Enable ; Enable ;
|
||||
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
|
||||
; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
|
||||
; State Machine Processing ; Auto ; Auto ;
|
||||
; Safe State Machine ; Off ; Off ;
|
||||
; Extract Verilog State Machines ; On ; On ;
|
||||
; Extract VHDL State Machines ; On ; On ;
|
||||
; Ignore Verilog initial constructs ; Off ; Off ;
|
||||
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
|
||||
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
|
||||
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
|
||||
; Infer RAMs from Raw Logic ; On ; On ;
|
||||
; Parallel Synthesis ; On ; On ;
|
||||
; DSP Block Balancing ; Auto ; Auto ;
|
||||
; NOT Gate Push-Back ; On ; On ;
|
||||
; Power-Up Don't Care ; On ; On ;
|
||||
; Remove Redundant Logic Cells ; Off ; Off ;
|
||||
; Remove Duplicate Registers ; On ; On ;
|
||||
; Ignore CARRY Buffers ; Off ; Off ;
|
||||
; Ignore CASCADE Buffers ; Off ; Off ;
|
||||
; Ignore GLOBAL Buffers ; Off ; Off ;
|
||||
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
|
||||
; Ignore LCELL Buffers ; Off ; Off ;
|
||||
; Ignore SOFT Buffers ; On ; On ;
|
||||
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
|
||||
; Optimization Technique ; Balanced ; Balanced ;
|
||||
; Carry Chain Length ; 70 ; 70 ;
|
||||
; Auto Carry Chains ; On ; On ;
|
||||
; Auto Open-Drain Pins ; On ; On ;
|
||||
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
|
||||
; Auto ROM Replacement ; On ; On ;
|
||||
; Auto RAM Replacement ; On ; On ;
|
||||
; Auto DSP Block Replacement ; On ; On ;
|
||||
; Auto Shift Register Replacement ; Auto ; Auto ;
|
||||
; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
|
||||
; Auto Clock Enable Replacement ; On ; On ;
|
||||
; Strict RAM Replacement ; Off ; Off ;
|
||||
; Allow Synchronous Control Signals ; On ; On ;
|
||||
; Force Use of Synchronous Clear Signals ; Off ; Off ;
|
||||
; Auto RAM Block Balancing ; On ; On ;
|
||||
; Auto RAM to Logic Cell Conversion ; Off ; Off ;
|
||||
; Auto Resource Sharing ; Off ; Off ;
|
||||
; Allow Any RAM Size For Recognition ; Off ; Off ;
|
||||
; Allow Any ROM Size For Recognition ; Off ; Off ;
|
||||
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
|
||||
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
|
||||
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
|
||||
; Timing-Driven Synthesis ; On ; On ;
|
||||
; Report Parameter Settings ; On ; On ;
|
||||
; Report Source Assignments ; On ; On ;
|
||||
; Report Connectivity Checks ; On ; On ;
|
||||
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
|
||||
; Synchronization Register Chain Length ; 2 ; 2 ;
|
||||
; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
|
||||
; HDL message level ; Level2 ; Level2 ;
|
||||
; Suppress Register Optimization Related Messages ; Off ; Off ;
|
||||
; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
|
||||
; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
|
||||
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
|
||||
; Clock MUX Protection ; On ; On ;
|
||||
; Auto Gated Clock Conversion ; Off ; Off ;
|
||||
; Block Design Naming ; Auto ; Auto ;
|
||||
; SDC constraint protection ; Off ; Off ;
|
||||
; Synthesis Effort ; Auto ; Auto ;
|
||||
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
|
||||
; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
|
||||
; Analysis & Synthesis Message Level ; Medium ; Medium ;
|
||||
; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
|
||||
; Resource Aware Inference For Block RAM ; On ; On ;
|
||||
+------------------------------------------------------------------+--------------------+--------------------+
|
||||
|
||||
|
||||
+------------------------------------------+
|
||||
; Parallel Compilation ;
|
||||
+----------------------------+-------------+
|
||||
; Processors ; Number ;
|
||||
+----------------------------+-------------+
|
||||
; Number detected on machine ; 8 ;
|
||||
; Maximum allowed ; 4 ;
|
||||
; ; ;
|
||||
; Average used ; 1.00 ;
|
||||
; Maximum used ; 1 ;
|
||||
; ; ;
|
||||
; Usage by Processor ; % Time Used ;
|
||||
; Processor 1 ; 100.0% ;
|
||||
+----------------------------+-------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Source Files Read ;
|
||||
+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------------+---------+
|
||||
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
|
||||
+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------------+---------+
|
||||
; EqCmp4.bdf ; yes ; User Block Diagram/Schematic File ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmp4.bdf ; ;
|
||||
; EqCmpDemo.bdf ; yes ; User Block Diagram/Schematic File ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.bdf ; ;
|
||||
+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------------+---------+
|
||||
|
||||
|
||||
+------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Resource Usage Summary ;
|
||||
+---------------------------------------------+--------------------+
|
||||
; Resource ; Usage ;
|
||||
+---------------------------------------------+--------------------+
|
||||
; Estimated Total logic elements ; 3 ;
|
||||
; ; ;
|
||||
; Total combinational functions ; 3 ;
|
||||
; Logic element usage by number of LUT inputs ; ;
|
||||
; -- 4 input functions ; 2 ;
|
||||
; -- 3 input functions ; 0 ;
|
||||
; -- <=2 input functions ; 1 ;
|
||||
; ; ;
|
||||
; Logic elements by mode ; ;
|
||||
; -- normal mode ; 3 ;
|
||||
; -- arithmetic mode ; 0 ;
|
||||
; ; ;
|
||||
; Total registers ; 0 ;
|
||||
; -- Dedicated logic registers ; 0 ;
|
||||
; -- I/O registers ; 0 ;
|
||||
; ; ;
|
||||
; I/O pins ; 9 ;
|
||||
; ; ;
|
||||
; Embedded Multiplier 9-bit elements ; 0 ;
|
||||
; ; ;
|
||||
; Maximum fan-out node ; EqCmp4:inst|inst~0 ;
|
||||
; Maximum fan-out ; 1 ;
|
||||
; Total fan-out ; 20 ;
|
||||
; Average fan-out ; 0.95 ;
|
||||
+---------------------------------------------+--------------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Resource Utilization by Entity ;
|
||||
+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+------------------------+-------------+--------------+
|
||||
; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
|
||||
+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+------------------------+-------------+--------------+
|
||||
; |EqCmpDemo ; 3 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 9 ; 0 ; |EqCmpDemo ; EqCmpDemo ; work ;
|
||||
; |EqCmp4:inst| ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |EqCmpDemo|EqCmp4:inst ; EqCmp4 ; work ;
|
||||
+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+------------------------+-------------+--------------+
|
||||
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
|
||||
|
||||
|
||||
+------------------------------------------------------+
|
||||
; General Register Statistics ;
|
||||
+----------------------------------------------+-------+
|
||||
; Statistic ; Value ;
|
||||
+----------------------------------------------+-------+
|
||||
; Total registers ; 0 ;
|
||||
; Number of registers using Synchronous Clear ; 0 ;
|
||||
; Number of registers using Synchronous Load ; 0 ;
|
||||
; Number of registers using Asynchronous Clear ; 0 ;
|
||||
; Number of registers using Asynchronous Load ; 0 ;
|
||||
; Number of registers using Clock Enable ; 0 ;
|
||||
; Number of registers using Preset ; 0 ;
|
||||
+----------------------------------------------+-------+
|
||||
|
||||
|
||||
+-----------------------------------------------------+
|
||||
; Post-Synthesis Netlist Statistics for Top Partition ;
|
||||
+-----------------------+-----------------------------+
|
||||
; Type ; Count ;
|
||||
+-----------------------+-----------------------------+
|
||||
; boundary_port ; 9 ;
|
||||
; cycloneiii_lcell_comb ; 3 ;
|
||||
; normal ; 3 ;
|
||||
; 2 data inputs ; 1 ;
|
||||
; 4 data inputs ; 2 ;
|
||||
; ; ;
|
||||
; Max LUT depth ; 2.00 ;
|
||||
; Average LUT depth ; 2.00 ;
|
||||
+-----------------------+-----------------------------+
|
||||
|
||||
|
||||
+-------------------------------+
|
||||
; Elapsed Time Per Partition ;
|
||||
+----------------+--------------+
|
||||
; Partition Name ; Elapsed Time ;
|
||||
+----------------+--------------+
|
||||
; Top ; 00:00:00 ;
|
||||
+----------------+--------------+
|
||||
|
||||
|
||||
+-------------------------------+
|
||||
; Analysis & Synthesis Messages ;
|
||||
+-------------------------------+
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus Prime Analysis & Synthesis
|
||||
Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
||||
Info: Processing started: Tue Mar 7 18:05:47 2023
|
||||
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off EqCmpDemo -c EqCmpDemo
|
||||
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
||||
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file EqCmp4.bdf
|
||||
Info (12023): Found entity 1: EqCmp4
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file EqCmpDemo.bdf
|
||||
Info (12023): Found entity 1: EqCmpDemo
|
||||
Info (12127): Elaborating entity "EqCmpDemo" for the top level hierarchy
|
||||
Info (12128): Elaborating entity "EqCmp4" for hierarchy "EqCmp4:inst"
|
||||
Info (286030): Timing-Driven Synthesis is running
|
||||
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
|
||||
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
|
||||
Info (21057): Implemented 12 device resources after synthesis - the final resource count might be different
|
||||
Info (21058): Implemented 8 input pins
|
||||
Info (21059): Implemented 1 output pins
|
||||
Info (21061): Implemented 3 logic cells
|
||||
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning
|
||||
Info: Peak virtual memory: 403 megabytes
|
||||
Info: Processing ended: Tue Mar 7 18:05:54 2023
|
||||
Info: Elapsed time: 00:00:07
|
||||
Info: Total CPU time (on all processors): 00:00:17
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
Analysis & Synthesis Status : Successful - Tue Mar 7 18:05:54 2023
|
||||
Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
||||
Revision Name : EqCmpDemo
|
||||
Top-level Entity Name : EqCmpDemo
|
||||
Family : Cyclone IV E
|
||||
Total logic elements : 3
|
||||
Total combinational functions : 3
|
||||
Dedicated logic registers : 0
|
||||
Total registers : 0
|
||||
Total pins : 9
|
||||
Total virtual pins : 0
|
||||
Total memory bits : 0
|
||||
Embedded Multiplier 9-bit elements : 0
|
||||
Total PLLs : 0
|
||||
|
|
@ -0,0 +1,851 @@
|
|||
-- Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
-- Your use of Intel Corporation's design tools, logic functions
|
||||
-- and other software and tools, and any partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Intel Program License
|
||||
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
-- the Intel FPGA IP License Agreement, or other applicable license
|
||||
-- agreement, including, without limitation, that your use is for
|
||||
-- the sole purpose of programming logic devices manufactured by
|
||||
-- Intel and sold by Intel or its authorized distributors. Please
|
||||
-- refer to the applicable agreement for further details, at
|
||||
-- https://fpgasoftware.intel.com/eula.
|
||||
--
|
||||
-- This is a Quartus Prime output file. It is for reporting purposes only, and is
|
||||
-- not intended for use as a Quartus Prime input file. This file cannot be used
|
||||
-- to make Quartus Prime pin assignments - for instructions on how to make pin
|
||||
-- assignments, please see Quartus Prime help.
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
---------------------------------------------------------------------------------
|
||||
-- NC : No Connect. This pin has no internal connection to the device.
|
||||
-- DNU : Do Not Use. This pin MUST NOT be connected.
|
||||
-- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
|
||||
-- VCCIO : Dedicated power pin, which MUST be connected to VCC
|
||||
-- of its bank.
|
||||
-- Bank 1: 3.3V
|
||||
-- Bank 2: 2.5V
|
||||
-- Bank 3: 3.3V
|
||||
-- Bank 4: 3.3V
|
||||
-- Bank 5: 2.5V
|
||||
-- Bank 6: 2.5V
|
||||
-- Bank 7: 2.5V
|
||||
-- Bank 8: 3.3V
|
||||
-- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
|
||||
-- It can also be used to report unused dedicated pins. The connection
|
||||
-- on the board for unused dedicated pins depends on whether this will
|
||||
-- be used in a future design. One example is device migration. When
|
||||
-- using device migration, refer to the device pin-tables. If it is a
|
||||
-- GND pin in the pin table or if it will not be used in a future design
|
||||
-- for another purpose the it MUST be connected to GND. If it is an unused
|
||||
-- dedicated pin, then it can be connected to a valid signal on the board
|
||||
-- (low, high, or toggling) if that signal is required for a different
|
||||
-- revision of the design.
|
||||
-- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
|
||||
-- This pin should be connected to GND. It may also be connected to a
|
||||
-- valid signal on the board (low, high, or toggling) if that signal
|
||||
-- is required for a different revision of the design.
|
||||
-- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
|
||||
-- or leave it unconnected.
|
||||
-- RESERVED : Unused I/O pin, which MUST be left unconnected.
|
||||
-- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
|
||||
-- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
|
||||
-- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
|
||||
-- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
---------------------------------------------------------------------------------
|
||||
-- Pin directions (input, output or bidir) are based on device operating in user mode.
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
||||
CHIP "EqCmpDemo" ASSIGNED TO AN: EP4CE115F29C7
|
||||
|
||||
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
|
||||
-------------------------------------------------------------------------------------------------------------
|
||||
VCCIO8 : A2 : power : : 3.3V : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8 :
|
||||
VCCIO8 : A5 : power : : 3.3V : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8 :
|
||||
TD_DATA[1] : A7 : input : 3.3-V LVTTL : : 8 : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 8 :
|
||||
VCCIO8 : A9 : power : : 3.3V : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A12 : : : : 8 :
|
||||
VCCIO8 : A13 : power : : 3.3V : 8 :
|
||||
ENETCLK_25 : A14 : input : 3.3-V LVTTL : : 8 : Y
|
||||
ENET0_RX_CLK : A15 : input : 2.5 V : : 7 : Y
|
||||
VCCIO7 : A16 : power : : 2.5V : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A17 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7 :
|
||||
VCCIO7 : A20 : power : : 2.5V : 7 :
|
||||
ENET0_INT_N : A21 : input : 2.5 V : : 7 : Y
|
||||
ENET1_RX_DV : A22 : input : 2.5 V : : 7 : Y
|
||||
ENET1_RX_DATA[2] : A23 : input : 2.5 V : : 7 : Y
|
||||
VCCIO7 : A24 : power : : 2.5V : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A25 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : A26 : : : : 7 :
|
||||
VCCIO7 : A27 : power : : 2.5V : 7 :
|
||||
VCCIO2 : AA1 : power : : 2.5V : 2 :
|
||||
GND : AA2 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AA3 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AA4 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AA5 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AA6 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AA8 : : : : 3 :
|
||||
GNDA1 : AA9 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AA10 : : : : 3 :
|
||||
VCCIO3 : AA11 : power : : 3.3V : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AA12 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AA13 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AA14 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AA15 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AA17 : : : : 4 :
|
||||
VCCIO4 : AA18 : power : : 3.3V : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AA19 : : : : 4 :
|
||||
GNDA4 : AA20 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 4 :
|
||||
SW[15] : AA22 : input : 2.5 V : : 5 : Y
|
||||
SW[14] : AA23 : input : 2.5 V : : 5 : Y
|
||||
SW[13] : AA24 : input : 2.5 V : : 5 : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AA25 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AA26 : : : : 5 :
|
||||
GND : AA27 : gnd : : : :
|
||||
VCCIO5 : AA28 : power : : 2.5V : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB1 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB2 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB3 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB4 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB5 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB6 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB7 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB8 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB9 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB10 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB11 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB13 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB14 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB16 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB18 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB19 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB20 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB21 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AB22 : : : : 4 :
|
||||
SW[12] : AB23 : input : 2.5 V : : 5 : Y
|
||||
SW[11] : AB24 : input : 2.5 V : : 5 : Y
|
||||
SW[9] : AB25 : input : 2.5 V : : 5 : Y
|
||||
SW[7] : AB26 : input : 2.5 V : : 5 : Y
|
||||
SW[4] : AB27 : input : 2.5 V : : 5 : Y
|
||||
SW[0] : AB28 : input : 2.5 V : : 5 : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC1 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC2 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC3 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC4 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC5 : : : : 2 :
|
||||
GND : AC6 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC7 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC8 : : : : 3 :
|
||||
GND : AC9 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC10 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC11 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC12 : : : : 3 :
|
||||
GND : AC13 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC14 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC15 : : : : 4 :
|
||||
GND : AC16 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC17 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC18 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC19 : : : : 4 :
|
||||
GND : AC20 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC21 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AC22 : : : : 4 :
|
||||
GND : AC23 : gnd : : : :
|
||||
SW[10] : AC24 : input : 2.5 V : : 5 : Y
|
||||
SW[8] : AC25 : input : 2.5 V : : 5 : Y
|
||||
SW[5] : AC26 : input : 2.5 V : : 5 : Y
|
||||
SW[2] : AC27 : input : 2.5 V : : 5 : Y
|
||||
SW[1] : AC28 : input : 2.5 V : : 5 : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD1 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD2 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD3 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD4 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD5 : : : : 3 :
|
||||
VCCIO3 : AD6 : power : : 3.3V : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD7 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD8 : : : : 3 :
|
||||
VCCIO3 : AD9 : power : : 3.3V : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD10 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD11 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD12 : : : : 3 :
|
||||
VCCIO3 : AD13 : power : : 3.3V : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD14 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD15 : : : : 4 :
|
||||
VCCIO4 : AD16 : power : : 3.3V : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD17 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD18 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD19 : : : : 4 :
|
||||
VCCIO4 : AD20 : power : : 3.3V : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD21 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD22 : : : : 4 :
|
||||
VCCIO4 : AD23 : power : : 3.3V : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD24 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD25 : : : : 4 :
|
||||
SW[6] : AD26 : input : 2.5 V : : 5 : Y
|
||||
SW[3] : AD27 : input : 2.5 V : : 5 : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AD28 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE1 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE2 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE3 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE4 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE5 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE6 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE7 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE8 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE9 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE10 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE11 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE12 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE13 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE14 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE15 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE16 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE17 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE18 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE19 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE20 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE21 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE22 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE23 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE24 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE25 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE26 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE27 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AE28 : : : : 5 :
|
||||
GND : AF1 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF2 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF3 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF4 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF5 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF6 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF7 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF8 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF9 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF10 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF11 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF12 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF13 : : : : 3 :
|
||||
SD_WP_N : AF14 : input : 3.3-V LVTTL : : 3 : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF15 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF16 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF17 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF18 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF19 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF20 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF21 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF22 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF23 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF24 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF25 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF26 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AF27 : : : : 5 :
|
||||
GND : AF28 : gnd : : : :
|
||||
VCCIO2 : AG1 : power : : 2.5V : 2 :
|
||||
GND : AG2 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AG3 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AG4 : : : : 3 :
|
||||
GND : AG5 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AG6 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AG7 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AG8 : : : : 3 :
|
||||
GND : AG9 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AG10 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AG11 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AG12 : : : : 3 :
|
||||
GND : AG13 : gnd : : : :
|
||||
CLOCK2_50 : AG14 : input : 3.3-V LVTTL : : 3 : Y
|
||||
CLOCK3_50 : AG15 : input : 3.3-V LVTTL : : 4 : Y
|
||||
GND : AG16 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AG17 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AG18 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AG19 : : : : 4 :
|
||||
GND : AG20 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AG21 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AG22 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AG23 : : : : 4 :
|
||||
GND : AG24 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AG25 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AG26 : : : : 4 :
|
||||
GND : AG27 : gnd : : : :
|
||||
VCCIO5 : AG28 : power : : 2.5V : 5 :
|
||||
VCCIO3 : AH2 : power : : 3.3V : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AH3 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AH4 : : : : 3 :
|
||||
VCCIO3 : AH5 : power : : 3.3V : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AH6 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AH7 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AH8 : : : : 3 :
|
||||
VCCIO3 : AH9 : power : : 3.3V : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AH10 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AH11 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AH12 : : : : 3 :
|
||||
VCCIO3 : AH13 : power : : 3.3V : 3 :
|
||||
SMA_CLKIN : AH14 : input : 3.3-V LVTTL : : 3 : Y
|
||||
HSMC_CLKIN0 : AH15 : input : 3.3-V LVTTL : : 4 : Y
|
||||
VCCIO4 : AH16 : power : : 3.3V : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AH17 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AH18 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AH19 : : : : 4 :
|
||||
VCCIO4 : AH20 : power : : 3.3V : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AH21 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AH22 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AH23 : : : : 4 :
|
||||
VCCIO4 : AH24 : power : : 3.3V : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AH25 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : AH26 : : : : 4 :
|
||||
VCCIO4 : AH27 : power : : 3.3V : 4 :
|
||||
VCCIO1 : B1 : power : : 3.3V : 1 :
|
||||
GND : B2 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 :
|
||||
GND : B5 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 8 :
|
||||
GND : B9 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 8 :
|
||||
GND : B12 : gnd : : : :
|
||||
GND : B13 : gnd : : : :
|
||||
TD_CLK27 : B14 : input : 3.3-V LVTTL : : 8 : Y
|
||||
ENET1_RX_CLK : B15 : input : 2.5 V : : 7 : Y
|
||||
GND : B16 : gnd : : : :
|
||||
ENET0_TX_CLK : B17 : input : 2.5 V : : 7 : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B18 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B19 : : : : 7 :
|
||||
GND : B20 : gnd : : : :
|
||||
ENET0_MDIO : B21 : input : 2.5 V : : 7 : Y
|
||||
ENET1_RX_COL : B22 : input : 2.5 V : : 7 : Y
|
||||
ENET1_RX_DATA[0] : B23 : input : 2.5 V : : 7 : Y
|
||||
GND : B24 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B25 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : B26 : : : : 7 :
|
||||
GND : B27 : gnd : : : :
|
||||
VCCIO6 : B28 : power : : 2.5V : 6 :
|
||||
GND : C1 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C5 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C6 : : : : 8 :
|
||||
TD_DATA[3] : C7 : input : 3.3-V LVTTL : : 8 : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C10 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C11 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C12 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 8 :
|
||||
ENET0_LINK100 : C14 : input : 3.3-V LVTTL : : 8 : Y
|
||||
ENET0_RX_DATA[3] : C15 : input : 2.5 V : : 7 : Y
|
||||
ENET0_RX_DATA[0] : C16 : input : 2.5 V : : 7 : Y
|
||||
ENET0_RX_DV : C17 : input : 2.5 V : : 7 : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C18 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 7 :
|
||||
ENET1_RX_DATA[1] : C21 : input : 2.5 V : : 7 : Y
|
||||
ENET1_TX_CLK : C22 : input : 2.5 V : : 7 : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C23 : : : : 7 :
|
||||
ENET1_RX_ER : C24 : input : 2.5 V : : 7 : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C25 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C26 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : C27 : : : : 6 :
|
||||
GND : C28 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : : : : 1 :
|
||||
AUD_ADCDAT : D2 : input : 3.3-V LVTTL : : 1 : Y
|
||||
GND : D3 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D4 : : : : 8 :
|
||||
OTG_INT : D5 : input : 3.3-V LVTTL : : 8 : Y
|
||||
TD_DATA[5] : D6 : input : 3.3-V LVTTL : : 8 : Y
|
||||
TD_DATA[4] : D7 : input : 3.3-V LVTTL : : 8 : Y
|
||||
TD_DATA[2] : D8 : input : 3.3-V LVTTL : : 8 : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D11 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 8 :
|
||||
ENET1_LINK100 : D13 : input : 3.3-V LVTTL : : 8 : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 8 :
|
||||
ENET0_RX_CRS : D15 : input : 2.5 V : : 7 : Y
|
||||
ENET0_RX_DATA[1] : D16 : input : 2.5 V : : 7 : Y
|
||||
ENET0_RX_DATA[2] : D17 : input : 2.5 V : : 7 : Y
|
||||
ENET0_RX_ER : D18 : input : 2.5 V : : 7 : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D19 : : : : 7 :
|
||||
ENET1_RX_CRS : D20 : input : 2.5 V : : 7 : Y
|
||||
ENET1_RX_DATA[3] : D21 : input : 2.5 V : : 7 : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D23 : : : : 7 :
|
||||
ENET1_INT_N : D24 : input : 2.5 V : : 7 : Y
|
||||
ENET1_MDIO : D25 : input : 2.5 V : : 7 : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D26 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D27 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : D28 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : E1 : : : : 1 :
|
||||
~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : E2 : input : 3.3-V LVTTL : : 1 : N
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : E3 : : : : 1 :
|
||||
TD_VS : E4 : input : 3.3-V LVTTL : : 8 : Y
|
||||
TD_HS : E5 : input : 3.3-V LVTTL : : 8 : Y
|
||||
VCCIO8 : E6 : power : : 3.3V : 8 :
|
||||
TD_DATA[6] : E7 : input : 3.3-V LVTTL : : 8 : Y
|
||||
TD_DATA[0] : E8 : input : 3.3-V LVTTL : : 8 : Y
|
||||
VCCIO8 : E9 : power : : 3.3V : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : E12 : : : : 8 :
|
||||
VCCIO8 : E13 : power : : 3.3V : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : E14 : : : : 8 :
|
||||
ENET0_RX_COL : E15 : input : 2.5 V : : 7 : Y
|
||||
VCCIO7 : E16 : power : : 2.5V : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : E17 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : E18 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : E19 : : : : 7 :
|
||||
VCCIO7 : E20 : power : : 2.5V : 7 :
|
||||
LEDG[0] : E21 : output : 2.5 V : : 7 : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : E22 : : : : 7 :
|
||||
VCCIO7 : E23 : power : : 2.5V : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : E24 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : E25 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : E26 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : E27 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : E28 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F1 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F2 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F3 : : : : 1 :
|
||||
~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : F4 : input : 3.3-V LVTTL : : 1 : N
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F5 : : : : 1 :
|
||||
GND : F6 : gnd : : : :
|
||||
TD_DATA[7] : F7 : input : 3.3-V LVTTL : : 8 : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F8 : : : : 8 :
|
||||
GND : F9 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F10 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F11 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F12 : : : : 8 :
|
||||
GND : F13 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F14 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 7 :
|
||||
GND : F16 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F17 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F18 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F19 : : : : 7 :
|
||||
GND : F20 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F21 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F22 : : : : 7 :
|
||||
GND : F23 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F24 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F25 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F26 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F27 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : F28 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G1 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G2 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G3 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G4 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G5 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G6 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G7 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G8 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G9 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G10 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G11 : : : : 8 :
|
||||
UART_RXD : G12 : input : 3.3-V LVTTL : : 8 : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G13 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G14 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G15 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G16 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G17 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G18 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G19 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G20 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G21 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G22 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G23 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G24 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G25 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G26 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G27 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : G28 : : : : 6 :
|
||||
VCCIO1 : H1 : power : : 3.3V : 1 :
|
||||
GND : H2 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H3 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H4 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H5 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H6 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H7 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H8 : : : : 8 :
|
||||
GNDA3 : H9 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H10 : : : : 8 :
|
||||
VCCIO8 : H11 : power : : 3.3V : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H15 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H16 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 7 :
|
||||
VCCIO7 : H18 : power : : 2.5V : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H19 : : : : 7 :
|
||||
GNDA2 : H20 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H21 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H22 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H23 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H24 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H25 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : H26 : : : : 6 :
|
||||
GND : H27 : gnd : : : :
|
||||
VCCIO6 : H28 : power : : 2.5V : 6 :
|
||||
GND+ : J1 : : : : 1 :
|
||||
GND : J2 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : J3 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : J4 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : J5 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : J6 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : J7 : : : : 1 :
|
||||
VCCA3 : J8 : power : : 2.5V : :
|
||||
VCCD_PLL3 : J9 : power : : 1.2V : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : J10 : : : : 8 :
|
||||
GND : J11 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 8 :
|
||||
UART_RTS : J13 : input : 3.3-V LVTTL : : 8 : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 8 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : J15 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : J16 : : : : 7 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : J17 : : : : 7 :
|
||||
GND : J18 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : J19 : : : : 7 :
|
||||
VCCD_PLL2 : J20 : power : : 1.2V : :
|
||||
VCCA2 : J21 : power : : 2.5V : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : J22 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : J23 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : J24 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : J25 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : J26 : : : : 6 :
|
||||
GND+ : J27 : : : : 6 :
|
||||
GND+ : J28 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : K1 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : K2 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : K3 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : K4 : : : : 1 :
|
||||
VCCIO1 : K5 : power : : 3.3V : 1 :
|
||||
GND : K6 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : K7 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 1 :
|
||||
VCCINT : K9 : power : : 1.2V : :
|
||||
GND : K10 : gnd : : : :
|
||||
VCCINT : K11 : power : : 1.2V : :
|
||||
GND : K12 : gnd : : : :
|
||||
VCCINT : K13 : power : : 1.2V : :
|
||||
GND : K14 : gnd : : : :
|
||||
VCCINT : K15 : power : : 1.2V : :
|
||||
GND : K16 : gnd : : : :
|
||||
VCCINT : K17 : power : : 1.2V : :
|
||||
GND : K18 : gnd : : : :
|
||||
VCCINT : K19 : power : : 1.2V : :
|
||||
GND : K20 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : K22 : : : : 6 :
|
||||
GND : K23 : gnd : : : :
|
||||
VCCIO6 : K24 : power : : 2.5V : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : K25 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : K26 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : K27 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : K28 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : L1 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : L2 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : L3 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : L4 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : L5 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : L6 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : L7 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : L8 : : : : 1 :
|
||||
GND : L9 : gnd : : : :
|
||||
VCCINT : L10 : power : : 1.2V : :
|
||||
GND : L11 : gnd : : : :
|
||||
VCCINT : L12 : power : : 1.2V : :
|
||||
GND : L13 : gnd : : : :
|
||||
VCCINT : L14 : power : : 1.2V : :
|
||||
GND : L15 : gnd : : : :
|
||||
VCCINT : L16 : power : : 1.2V : :
|
||||
GND : L17 : gnd : : : :
|
||||
VCCINT : L18 : power : : 1.2V : :
|
||||
GND : L19 : gnd : : : :
|
||||
VCCINT : L20 : power : : 1.2V : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : L21 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : L22 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : L23 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : L24 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : L25 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : L26 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : L27 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : L28 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : M1 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : M2 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : M3 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : M4 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : M5 : : : : 1 :
|
||||
nSTATUS : M6 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : M7 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : M8 : : : : 1 :
|
||||
VCCINT : M9 : power : : 1.2V : :
|
||||
GND : M10 : gnd : : : :
|
||||
VCCINT : M11 : power : : 1.2V : :
|
||||
GND : M12 : gnd : : : :
|
||||
VCCINT : M13 : power : : 1.2V : :
|
||||
GND : M14 : gnd : : : :
|
||||
VCCINT : M15 : power : : 1.2V : :
|
||||
GND : M16 : gnd : : : :
|
||||
VCCINT : M17 : power : : 1.2V : :
|
||||
GND : M18 : gnd : : : :
|
||||
VCCINT : M19 : power : : 1.2V : :
|
||||
GND : M20 : gnd : : : :
|
||||
KEY[1] : M21 : input : 2.5 V : : 6 : Y
|
||||
MSEL2 : M22 : : : : 6 :
|
||||
KEY[0] : M23 : input : 2.5 V : : 6 : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : M24 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : M25 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : M26 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : M27 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : M28 : : : : 6 :
|
||||
VCCIO1 : N1 : power : : 3.3V : 1 :
|
||||
GND : N2 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : N3 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : N4 : : : : 1 :
|
||||
VCCIO1 : N5 : power : : 3.3V : 1 :
|
||||
GND : N6 : gnd : : : :
|
||||
~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : N7 : input : 3.3-V LVTTL : : 1 : N
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : N8 : : : : 1 :
|
||||
GND : N9 : gnd : : : :
|
||||
VCCINT : N10 : power : : 1.2V : :
|
||||
GND : N11 : gnd : : : :
|
||||
VCCINT : N12 : power : : 1.2V : :
|
||||
GND : N13 : gnd : : : :
|
||||
VCCINT : N14 : power : : 1.2V : :
|
||||
GND : N15 : gnd : : : :
|
||||
VCCINT : N16 : power : : 1.2V : :
|
||||
GND : N17 : gnd : : : :
|
||||
VCCINT : N18 : power : : 1.2V : :
|
||||
GND : N19 : gnd : : : :
|
||||
VCCINT : N20 : power : : 1.2V : :
|
||||
KEY[2] : N21 : input : 2.5 V : : 6 : Y
|
||||
MSEL0 : N22 : : : : 6 :
|
||||
GND : N23 : gnd : : : :
|
||||
VCCIO6 : N24 : power : : 2.5V : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : N25 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : N26 : : : : 6 :
|
||||
GND : N27 : gnd : : : :
|
||||
VCCIO6 : N28 : power : : 2.5V : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : P1 : : : : 1 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : P2 : : : : 1 :
|
||||
~ALTERA_DCLK~ : P3 : output : 3.3-V LVTTL : : 1 : N
|
||||
nCONFIG : P4 : : : : 1 :
|
||||
TCK : P5 : input : : : 1 :
|
||||
TDO : P6 : output : : : 1 :
|
||||
TDI : P7 : input : : : 1 :
|
||||
TMS : P8 : input : : : 1 :
|
||||
VCCINT : P9 : power : : 1.2V : :
|
||||
GND : P10 : gnd : : : :
|
||||
VCCINT : P11 : power : : 1.2V : :
|
||||
GND : P12 : gnd : : : :
|
||||
VCCINT : P13 : power : : 1.2V : :
|
||||
GND : P14 : gnd : : : :
|
||||
VCCINT : P15 : power : : 1.2V : :
|
||||
GND : P16 : gnd : : : :
|
||||
VCCINT : P17 : power : : 1.2V : :
|
||||
GND : P18 : gnd : : : :
|
||||
VCCINT : P19 : power : : 1.2V : :
|
||||
GND : P20 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : P21 : : : : 5 :
|
||||
MSEL3 : P22 : : : : 6 :
|
||||
MSEL1 : P23 : : : : 6 :
|
||||
CONF_DONE : P24 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : P25 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : P26 : : : : 6 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : P27 : : : : 6 :
|
||||
~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : P28 : output : 2.5 V : : 6 : N
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : R1 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : R2 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : R3 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : R4 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : R5 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : R6 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : R7 : : : : 2 :
|
||||
nCE : R8 : : : : 1 :
|
||||
GND : R9 : gnd : : : :
|
||||
VCCINT : R10 : power : : 1.2V : :
|
||||
GND : R11 : gnd : : : :
|
||||
VCCINT : R12 : power : : 1.2V : :
|
||||
GND : R13 : gnd : : : :
|
||||
VCCINT : R14 : power : : 1.2V : :
|
||||
GND : R15 : gnd : : : :
|
||||
VCCINT : R16 : power : : 1.2V : :
|
||||
GND : R17 : gnd : : : :
|
||||
VCCINT : R18 : power : : 1.2V : :
|
||||
GND : R19 : gnd : : : :
|
||||
VCCINT : R20 : power : : 1.2V : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : R21 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : R22 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : R23 : : : : 5 :
|
||||
KEY[3] : R24 : input : 2.5 V : : 5 : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : R25 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : R26 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : R27 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : R28 : : : : 5 :
|
||||
VCCIO2 : T1 : power : : 2.5V : 2 :
|
||||
GND : T2 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : T3 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : T4 : : : : 2 :
|
||||
VCCIO2 : T5 : power : : 2.5V : 2 :
|
||||
GND : T6 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : T7 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : T8 : : : : 2 :
|
||||
VCCINT : T9 : power : : 1.2V : :
|
||||
GND : T10 : gnd : : : :
|
||||
VCCINT : T11 : power : : 1.2V : :
|
||||
GND : T12 : gnd : : : :
|
||||
VCCINT : T13 : power : : 1.2V : :
|
||||
GND : T14 : gnd : : : :
|
||||
VCCINT : T15 : power : : 1.2V : :
|
||||
GND : T16 : gnd : : : :
|
||||
VCCINT : T17 : power : : 1.2V : :
|
||||
GND : T18 : gnd : : : :
|
||||
VCCINT : T19 : power : : 1.2V : :
|
||||
GND : T20 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : T21 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : T22 : : : : 5 :
|
||||
GND : T23 : gnd : : : :
|
||||
VCCIO5 : T24 : power : : 2.5V : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : T25 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : T26 : : : : 5 :
|
||||
GND : T27 : gnd : : : :
|
||||
VCCIO5 : T28 : power : : 2.5V : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U1 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U2 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U3 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U4 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U5 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U6 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U8 : : : : 2 :
|
||||
GND : U9 : gnd : : : :
|
||||
VCCINT : U10 : power : : 1.2V : :
|
||||
GND : U11 : gnd : : : :
|
||||
VCCINT : U12 : power : : 1.2V : :
|
||||
GND : U13 : gnd : : : :
|
||||
VCCINT : U14 : power : : 1.2V : :
|
||||
GND : U15 : gnd : : : :
|
||||
VCCINT : U16 : power : : 1.2V : :
|
||||
GND : U17 : gnd : : : :
|
||||
VCCINT : U18 : power : : 1.2V : :
|
||||
GND : U19 : gnd : : : :
|
||||
VCCINT : U20 : power : : 1.2V : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U21 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U22 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U23 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U24 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U25 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U26 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U27 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : U28 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V1 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V2 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V3 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V4 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V5 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V6 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V7 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V8 : : : : 2 :
|
||||
VCCINT : V9 : power : : 1.2V : :
|
||||
GND : V10 : gnd : : : :
|
||||
VCCINT : V11 : power : : 1.2V : :
|
||||
GND : V12 : gnd : : : :
|
||||
VCCINT : V13 : power : : 1.2V : :
|
||||
GND : V14 : gnd : : : :
|
||||
VCCINT : V15 : power : : 1.2V : :
|
||||
GND : V16 : gnd : : : :
|
||||
VCCINT : V17 : power : : 1.2V : :
|
||||
GND : V18 : gnd : : : :
|
||||
VCCINT : V19 : power : : 1.2V : :
|
||||
GND : V20 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V21 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V23 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V24 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V25 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V26 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V27 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : V28 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W1 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W2 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W3 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W4 : : : : 2 :
|
||||
VCCIO2 : W5 : power : : 2.5V : 2 :
|
||||
GND : W6 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W7 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 2 :
|
||||
GND : W9 : gnd : : : :
|
||||
VCCINT : W10 : power : : 1.2V : :
|
||||
GND : W11 : gnd : : : :
|
||||
VCCINT : W12 : power : : 1.2V : :
|
||||
GND : W13 : gnd : : : :
|
||||
VCCINT : W14 : power : : 1.2V : :
|
||||
GND : W15 : gnd : : : :
|
||||
VCCINT : W16 : power : : 1.2V : :
|
||||
GND : W17 : gnd : : : :
|
||||
VCCINT : W18 : power : : 1.2V : :
|
||||
GND : W19 : gnd : : : :
|
||||
VCCINT : W20 : power : : 1.2V : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W21 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W22 : : : : 5 :
|
||||
GND : W23 : gnd : : : :
|
||||
VCCIO5 : W24 : power : : 2.5V : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W25 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W26 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W27 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : W28 : : : : 5 :
|
||||
FL_RY : Y1 : input : 3.3-V LVTTL : : 2 : Y
|
||||
CLOCK_50 : Y2 : input : 2.5 V : : 2 : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : Y3 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : Y4 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : Y5 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : Y6 : : : : 2 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : Y7 : : : : 2 :
|
||||
VCCA1 : Y8 : power : : 2.5V : :
|
||||
VCCD_PLL1 : Y9 : power : : 1.2V : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : Y10 : : : : 3 :
|
||||
GND : Y11 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : Y12 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 3 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : Y14 : : : : 3 :
|
||||
IRDA_RXD : Y15 : input : 3.3-V LVTTL : : 3 : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 4 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : Y17 : : : : 4 :
|
||||
GND : Y18 : gnd : : : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : Y19 : : : : 4 :
|
||||
VCCD_PLL4 : Y20 : power : : 1.2V : :
|
||||
VCCA4 : Y21 : power : : 2.5V : :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : Y22 : : : : 5 :
|
||||
SW[17] : Y23 : input : 2.5 V : : 5 : Y
|
||||
SW[16] : Y24 : input : 2.5 V : : 5 : Y
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : Y25 : : : : 5 :
|
||||
RESERVED_INPUT_WITH_WEAK_PULLUP : Y26 : : : : 5 :
|
||||
GND+ : Y27 : : : : 5 :
|
||||
GND+ : Y28 : : : : 5 :
|
||||
|
|
@ -0,0 +1 @@
|
|||
<sld_project_info/>
|
||||
Binary file not shown.
|
|
@ -0,0 +1,513 @@
|
|||
Timing Analyzer report for EqCmpDemo
|
||||
Tue Mar 7 18:06:07 2023
|
||||
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
||||
|
||||
|
||||
---------------------
|
||||
; Table of Contents ;
|
||||
---------------------
|
||||
1. Legal Notice
|
||||
2. Timing Analyzer Summary
|
||||
3. Parallel Compilation
|
||||
4. Clocks
|
||||
5. Slow 1200mV 85C Model Fmax Summary
|
||||
6. Timing Closure Recommendations
|
||||
7. Slow 1200mV 85C Model Setup Summary
|
||||
8. Slow 1200mV 85C Model Hold Summary
|
||||
9. Slow 1200mV 85C Model Recovery Summary
|
||||
10. Slow 1200mV 85C Model Removal Summary
|
||||
11. Slow 1200mV 85C Model Minimum Pulse Width Summary
|
||||
12. Slow 1200mV 85C Model Metastability Summary
|
||||
13. Slow 1200mV 0C Model Fmax Summary
|
||||
14. Slow 1200mV 0C Model Setup Summary
|
||||
15. Slow 1200mV 0C Model Hold Summary
|
||||
16. Slow 1200mV 0C Model Recovery Summary
|
||||
17. Slow 1200mV 0C Model Removal Summary
|
||||
18. Slow 1200mV 0C Model Minimum Pulse Width Summary
|
||||
19. Slow 1200mV 0C Model Metastability Summary
|
||||
20. Fast 1200mV 0C Model Setup Summary
|
||||
21. Fast 1200mV 0C Model Hold Summary
|
||||
22. Fast 1200mV 0C Model Recovery Summary
|
||||
23. Fast 1200mV 0C Model Removal Summary
|
||||
24. Fast 1200mV 0C Model Minimum Pulse Width Summary
|
||||
25. Fast 1200mV 0C Model Metastability Summary
|
||||
26. Multicorner Timing Analysis Summary
|
||||
27. Board Trace Model Assignments
|
||||
28. Input Transition Times
|
||||
29. Signal Integrity Metrics (Slow 1200mv 0c Model)
|
||||
30. Signal Integrity Metrics (Slow 1200mv 85c Model)
|
||||
31. Signal Integrity Metrics (Fast 1200mv 0c Model)
|
||||
32. Clock Transfers
|
||||
33. Report TCCS
|
||||
34. Report RSKM
|
||||
35. Unconstrained Paths Summary
|
||||
36. Unconstrained Input Ports
|
||||
37. Unconstrained Output Ports
|
||||
38. Unconstrained Input Ports
|
||||
39. Unconstrained Output Ports
|
||||
40. Timing Analyzer Messages
|
||||
|
||||
|
||||
|
||||
----------------
|
||||
; Legal Notice ;
|
||||
----------------
|
||||
Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and any partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Intel Program License
|
||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
the Intel FPGA IP License Agreement, or other applicable license
|
||||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details, at
|
||||
https://fpgasoftware.intel.com/eula.
|
||||
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------------+
|
||||
; Timing Analyzer Summary ;
|
||||
+-----------------------+-----------------------------------------------------+
|
||||
; Quartus Prime Version ; Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
|
||||
; Timing Analyzer ; Legacy Timing Analyzer ;
|
||||
; Revision Name ; EqCmpDemo ;
|
||||
; Device Family ; Cyclone IV E ;
|
||||
; Device Name ; EP4CE115F29C7 ;
|
||||
; Timing Models ; Final ;
|
||||
; Delay Model ; Combined ;
|
||||
; Rise/Fall Delays ; Enabled ;
|
||||
+-----------------------+-----------------------------------------------------+
|
||||
|
||||
|
||||
+------------------------------------------+
|
||||
; Parallel Compilation ;
|
||||
+----------------------------+-------------+
|
||||
; Processors ; Number ;
|
||||
+----------------------------+-------------+
|
||||
; Number detected on machine ; 8 ;
|
||||
; Maximum allowed ; 4 ;
|
||||
; ; ;
|
||||
; Average used ; 1.01 ;
|
||||
; Maximum used ; 4 ;
|
||||
; ; ;
|
||||
; Usage by Processor ; % Time Used ;
|
||||
; Processor 1 ; 100.0% ;
|
||||
; Processors 2-4 ; 0.2% ;
|
||||
+----------------------------+-------------+
|
||||
|
||||
|
||||
----------
|
||||
; Clocks ;
|
||||
----------
|
||||
No clocks to report.
|
||||
|
||||
|
||||
--------------------------------------
|
||||
; Slow 1200mV 85C Model Fmax Summary ;
|
||||
--------------------------------------
|
||||
No paths to report.
|
||||
|
||||
|
||||
----------------------------------
|
||||
; Timing Closure Recommendations ;
|
||||
----------------------------------
|
||||
HTML report is unavailable in plain text report export.
|
||||
|
||||
|
||||
---------------------------------------
|
||||
; Slow 1200mV 85C Model Setup Summary ;
|
||||
---------------------------------------
|
||||
No paths to report.
|
||||
|
||||
|
||||
--------------------------------------
|
||||
; Slow 1200mV 85C Model Hold Summary ;
|
||||
--------------------------------------
|
||||
No paths to report.
|
||||
|
||||
|
||||
------------------------------------------
|
||||
; Slow 1200mV 85C Model Recovery Summary ;
|
||||
------------------------------------------
|
||||
No paths to report.
|
||||
|
||||
|
||||
-----------------------------------------
|
||||
; Slow 1200mV 85C Model Removal Summary ;
|
||||
-----------------------------------------
|
||||
No paths to report.
|
||||
|
||||
|
||||
-----------------------------------------------------
|
||||
; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
|
||||
-----------------------------------------------------
|
||||
No paths to report.
|
||||
|
||||
|
||||
-----------------------------------------------
|
||||
; Slow 1200mV 85C Model Metastability Summary ;
|
||||
-----------------------------------------------
|
||||
No synchronizer chains to report.
|
||||
|
||||
|
||||
-------------------------------------
|
||||
; Slow 1200mV 0C Model Fmax Summary ;
|
||||
-------------------------------------
|
||||
No paths to report.
|
||||
|
||||
|
||||
--------------------------------------
|
||||
; Slow 1200mV 0C Model Setup Summary ;
|
||||
--------------------------------------
|
||||
No paths to report.
|
||||
|
||||
|
||||
-------------------------------------
|
||||
; Slow 1200mV 0C Model Hold Summary ;
|
||||
-------------------------------------
|
||||
No paths to report.
|
||||
|
||||
|
||||
-----------------------------------------
|
||||
; Slow 1200mV 0C Model Recovery Summary ;
|
||||
-----------------------------------------
|
||||
No paths to report.
|
||||
|
||||
|
||||
----------------------------------------
|
||||
; Slow 1200mV 0C Model Removal Summary ;
|
||||
----------------------------------------
|
||||
No paths to report.
|
||||
|
||||
|
||||
----------------------------------------------------
|
||||
; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
|
||||
----------------------------------------------------
|
||||
No paths to report.
|
||||
|
||||
|
||||
----------------------------------------------
|
||||
; Slow 1200mV 0C Model Metastability Summary ;
|
||||
----------------------------------------------
|
||||
No synchronizer chains to report.
|
||||
|
||||
|
||||
--------------------------------------
|
||||
; Fast 1200mV 0C Model Setup Summary ;
|
||||
--------------------------------------
|
||||
No paths to report.
|
||||
|
||||
|
||||
-------------------------------------
|
||||
; Fast 1200mV 0C Model Hold Summary ;
|
||||
-------------------------------------
|
||||
No paths to report.
|
||||
|
||||
|
||||
-----------------------------------------
|
||||
; Fast 1200mV 0C Model Recovery Summary ;
|
||||
-----------------------------------------
|
||||
No paths to report.
|
||||
|
||||
|
||||
----------------------------------------
|
||||
; Fast 1200mV 0C Model Removal Summary ;
|
||||
----------------------------------------
|
||||
No paths to report.
|
||||
|
||||
|
||||
----------------------------------------------------
|
||||
; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
|
||||
----------------------------------------------------
|
||||
No paths to report.
|
||||
|
||||
|
||||
----------------------------------------------
|
||||
; Fast 1200mV 0C Model Metastability Summary ;
|
||||
----------------------------------------------
|
||||
No synchronizer chains to report.
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------+
|
||||
; Multicorner Timing Analysis Summary ;
|
||||
+------------------+-------+------+----------+---------+---------------------+
|
||||
; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
|
||||
+------------------+-------+------+----------+---------+---------------------+
|
||||
; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; N/A ;
|
||||
; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ;
|
||||
+------------------+-------+------+----------+---------+---------------------+
|
||||
|
||||
|
||||
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Board Trace Model Assignments ;
|
||||
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
|
||||
; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
|
||||
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
|
||||
; LEDG[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||
; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||
; ~ALTERA_nCEO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
|
||||
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------+
|
||||
; Input Transition Times ;
|
||||
+-------------------------+--------------+-----------------+-----------------+
|
||||
; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
|
||||
+-------------------------+--------------+-----------------+-----------------+
|
||||
; SW[4] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; SW[5] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; SW[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; SW[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; SW[6] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; SW[7] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; SW[3] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; SW[2] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; AUD_ADCDAT ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
|
||||
; CLOCK2_50 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
|
||||
; CLOCK3_50 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
|
||||
; CLOCK_50 ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; ENET0_INT_N ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; ENET0_LINK100 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
|
||||
; ENET0_MDIO ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; ENET0_RX_CLK ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; ENET0_RX_COL ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; ENET0_RX_CRS ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; ENET0_RX_DATA[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; ENET0_RX_DATA[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; ENET0_RX_DATA[2] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; ENET0_RX_DATA[3] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; ENET0_RX_DV ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; ENET0_RX_ER ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; ENET0_TX_CLK ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; ENET1_INT_N ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; ENET1_LINK100 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
|
||||
; ENET1_MDIO ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; ENET1_RX_CLK ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; ENET1_RX_COL ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; ENET1_RX_CRS ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; ENET1_RX_DATA[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; ENET1_RX_DATA[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; ENET1_RX_DATA[2] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; ENET1_RX_DATA[3] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; ENET1_RX_DV ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; ENET1_RX_ER ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; ENET1_TX_CLK ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; ENETCLK_25 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
|
||||
; FL_RY ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
|
||||
; HSMC_CLKIN0 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
|
||||
; IRDA_RXD ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
|
||||
; KEY[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; KEY[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; KEY[2] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; KEY[3] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; OTG_INT ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
|
||||
; SD_WP_N ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
|
||||
; SMA_CLKIN ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
|
||||
; SW[10] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; SW[11] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; SW[12] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; SW[13] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; SW[14] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; SW[15] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; SW[16] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; SW[17] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; SW[8] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; SW[9] ; 2.5 V ; 2000 ps ; 2000 ps ;
|
||||
; TD_CLK27 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
|
||||
; TD_DATA[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
|
||||
; TD_DATA[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
|
||||
; TD_DATA[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
|
||||
; TD_DATA[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
|
||||
; TD_DATA[4] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
|
||||
; TD_DATA[5] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
|
||||
; TD_DATA[6] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
|
||||
; TD_DATA[7] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
|
||||
; TD_HS ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
|
||||
; TD_VS ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
|
||||
; UART_RTS ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
|
||||
; UART_RXD ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
|
||||
; ~ALTERA_ASDO_DATA1~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
|
||||
; ~ALTERA_FLASH_nCE_nCSO~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
|
||||
; ~ALTERA_DATA0~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
|
||||
+-------------------------+--------------+-----------------+-----------------+
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Signal Integrity Metrics (Slow 1200mv 0c Model) ;
|
||||
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
|
||||
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||
; LEDG[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
|
||||
; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 5.73e-09 V ; 3.19 V ; -0.173 V ; 0.151 V ; 0.259 V ; 2.79e-10 s ; 2.42e-10 s ; Yes ; Yes ; 3.08 V ; 5.73e-09 V ; 3.19 V ; -0.173 V ; 0.151 V ; 0.259 V ; 2.79e-10 s ; 2.42e-10 s ; Yes ; Yes ;
|
||||
; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.18e-09 V ; 2.38 V ; -0.00483 V ; 0.152 V ; 0.012 V ; 4.81e-10 s ; 6.29e-10 s ; Yes ; Yes ; 2.32 V ; 4.18e-09 V ; 2.38 V ; -0.00483 V ; 0.152 V ; 0.012 V ; 4.81e-10 s ; 6.29e-10 s ; Yes ; Yes ;
|
||||
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Signal Integrity Metrics (Slow 1200mv 85c Model) ;
|
||||
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
|
||||
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||
; LEDG[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
|
||||
; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 6.54e-07 V ; 3.14 V ; -0.115 V ; 0.146 V ; 0.141 V ; 3.07e-10 s ; 3.96e-10 s ; Yes ; No ; 3.08 V ; 6.54e-07 V ; 3.14 V ; -0.115 V ; 0.146 V ; 0.141 V ; 3.07e-10 s ; 3.96e-10 s ; Yes ; No ;
|
||||
; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.15e-07 V ; 2.35 V ; -0.00712 V ; 0.093 V ; 0.02 V ; 6.21e-10 s ; 7.9e-10 s ; Yes ; Yes ; 2.32 V ; 6.15e-07 V ; 2.35 V ; -0.00712 V ; 0.093 V ; 0.02 V ; 6.21e-10 s ; 7.9e-10 s ; Yes ; Yes ;
|
||||
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Signal Integrity Metrics (Fast 1200mv 0c Model) ;
|
||||
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
|
||||
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||
; LEDG[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
|
||||
; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 6.54e-08 V ; 3.66 V ; -0.26 V ; 0.41 V ; 0.32 V ; 1.57e-10 s ; 2.15e-10 s ; No ; Yes ; 3.46 V ; 6.54e-08 V ; 3.66 V ; -0.26 V ; 0.41 V ; 0.32 V ; 1.57e-10 s ; 2.15e-10 s ; No ; Yes ;
|
||||
; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ;
|
||||
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||||
|
||||
|
||||
-------------------
|
||||
; Clock Transfers ;
|
||||
-------------------
|
||||
Nothing to report.
|
||||
|
||||
|
||||
---------------
|
||||
; Report TCCS ;
|
||||
---------------
|
||||
No dedicated SERDES Transmitter circuitry present in device or used in design
|
||||
|
||||
|
||||
---------------
|
||||
; Report RSKM ;
|
||||
---------------
|
||||
No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
|
||||
|
||||
|
||||
+------------------------------------------------+
|
||||
; Unconstrained Paths Summary ;
|
||||
+---------------------------------+-------+------+
|
||||
; Property ; Setup ; Hold ;
|
||||
+---------------------------------+-------+------+
|
||||
; Illegal Clocks ; 0 ; 0 ;
|
||||
; Unconstrained Clocks ; 0 ; 0 ;
|
||||
; Unconstrained Input Ports ; 8 ; 8 ;
|
||||
; Unconstrained Input Port Paths ; 8 ; 8 ;
|
||||
; Unconstrained Output Ports ; 1 ; 1 ;
|
||||
; Unconstrained Output Port Paths ; 8 ; 8 ;
|
||||
+---------------------------------+-------+------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------+
|
||||
; Unconstrained Input Ports ;
|
||||
+------------+--------------------------------------------------------------------------------------+
|
||||
; Input Port ; Comment ;
|
||||
+------------+--------------------------------------------------------------------------------------+
|
||||
; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; SW[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; SW[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; SW[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; SW[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; SW[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; SW[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
+------------+--------------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------------------------------------+
|
||||
; Unconstrained Output Ports ;
|
||||
+-------------+---------------------------------------------------------------------------------------+
|
||||
; Output Port ; Comment ;
|
||||
+-------------+---------------------------------------------------------------------------------------+
|
||||
; LEDG[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
+-------------+---------------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------+
|
||||
; Unconstrained Input Ports ;
|
||||
+------------+--------------------------------------------------------------------------------------+
|
||||
; Input Port ; Comment ;
|
||||
+------------+--------------------------------------------------------------------------------------+
|
||||
; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; SW[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; SW[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; SW[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; SW[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; SW[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; SW[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
+------------+--------------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------------------------------------+
|
||||
; Unconstrained Output Ports ;
|
||||
+-------------+---------------------------------------------------------------------------------------+
|
||||
; Output Port ; Comment ;
|
||||
+-------------+---------------------------------------------------------------------------------------+
|
||||
; LEDG[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
+-------------+---------------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
+--------------------------+
|
||||
; Timing Analyzer Messages ;
|
||||
+--------------------------+
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus Prime Timing Analyzer
|
||||
Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
||||
Info: Processing started: Tue Mar 7 18:06:06 2023
|
||||
Info: Command: quartus_sta EqCmpDemo -c EqCmpDemo
|
||||
Info: qsta_default_script.tcl version: #1
|
||||
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
||||
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
|
||||
Info (21077): Low junction temperature is 0 degrees C
|
||||
Info (21077): High junction temperature is 85 degrees C
|
||||
Critical Warning (332012): Synopsys Design Constraints File file not found: 'EqCmpDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
|
||||
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
|
||||
Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
|
||||
Warning (332068): No clocks defined in design.
|
||||
Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
|
||||
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
|
||||
Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
|
||||
Info (332159): No clocks to report
|
||||
Info: Analyzing Slow 1200mV 85C Model
|
||||
Info (332140): No fmax paths to report
|
||||
Info (332140): No Setup paths to report
|
||||
Info (332140): No Hold paths to report
|
||||
Info (332140): No Recovery paths to report
|
||||
Info (332140): No Removal paths to report
|
||||
Info (332140): No Minimum Pulse Width paths to report
|
||||
Info: Analyzing Slow 1200mV 0C Model
|
||||
Info (334003): Started post-fitting delay annotation
|
||||
Info (334004): Delay annotation completed successfully
|
||||
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
|
||||
Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
|
||||
Warning (332068): No clocks defined in design.
|
||||
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
|
||||
Info (332140): No fmax paths to report
|
||||
Info (332140): No Setup paths to report
|
||||
Info (332140): No Hold paths to report
|
||||
Info (332140): No Recovery paths to report
|
||||
Info (332140): No Removal paths to report
|
||||
Info (332140): No Minimum Pulse Width paths to report
|
||||
Info: Analyzing Fast 1200mV 0C Model
|
||||
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
|
||||
Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
|
||||
Warning (332068): No clocks defined in design.
|
||||
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
|
||||
Info (332140): No Setup paths to report
|
||||
Info (332140): No Hold paths to report
|
||||
Info (332140): No Recovery paths to report
|
||||
Info (332140): No Removal paths to report
|
||||
Info (332140): No Minimum Pulse Width paths to report
|
||||
Info (332102): Design is not fully constrained for setup requirements
|
||||
Info (332102): Design is not fully constrained for hold requirements
|
||||
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings
|
||||
Info: Peak virtual memory: 533 megabytes
|
||||
Info: Processing ended: Tue Mar 7 18:06:07 2023
|
||||
Info: Elapsed time: 00:00:01
|
||||
Info: Total CPU time (on all processors): 00:00:01
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
------------------------------------------------------------
|
||||
Timing Analyzer Summary
|
||||
------------------------------------------------------------
|
||||
|
||||
------------------------------------------------------------
|
||||
|
|
@ -0,0 +1 @@
|
|||
set tool_name "ModelSim-Altera (VHDL)"
|
||||
|
|
@ -0,0 +1,477 @@
|
|||
-- Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
-- Your use of Intel Corporation's design tools, logic functions
|
||||
-- and other software and tools, and any partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Intel Program License
|
||||
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
-- the Intel FPGA IP License Agreement, or other applicable license
|
||||
-- agreement, including, without limitation, that your use is for
|
||||
-- the sole purpose of programming logic devices manufactured by
|
||||
-- Intel and sold by Intel or its authorized distributors. Please
|
||||
-- refer to the applicable agreement for further details, at
|
||||
-- https://fpgasoftware.intel.com/eula.
|
||||
|
||||
-- VENDOR "Altera"
|
||||
-- PROGRAM "Quartus Prime"
|
||||
-- VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
|
||||
|
||||
-- DATE "03/07/2023 18:06:08"
|
||||
|
||||
--
|
||||
-- Device: Altera EP4CE115F29C7 Package FBGA780
|
||||
--
|
||||
|
||||
--
|
||||
-- This VHDL file should be used for ModelSim-Altera (VHDL) only
|
||||
--
|
||||
|
||||
LIBRARY CYCLONEIVE;
|
||||
LIBRARY IEEE;
|
||||
USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
ENTITY hard_block IS
|
||||
PORT (
|
||||
devoe : IN std_logic;
|
||||
devclrn : IN std_logic;
|
||||
devpor : IN std_logic
|
||||
);
|
||||
END hard_block;
|
||||
|
||||
-- Design Ports Information
|
||||
-- AUD_ADCDAT => Location: PIN_D2, I/O Standard: 3.3-V LVTTL, Current Strength: Default
|
||||
-- CLOCK2_50 => Location: PIN_AG14, I/O Standard: 3.3-V LVTTL, Current Strength: Default
|
||||
-- CLOCK3_50 => Location: PIN_AG15, I/O Standard: 3.3-V LVTTL, Current Strength: Default
|
||||
-- CLOCK_50 => Location: PIN_Y2, I/O Standard: 2.5 V, Current Strength: Default
|
||||
-- ENET0_INT_N => Location: PIN_A21, I/O Standard: 2.5 V, Current Strength: Default
|
||||
-- ENET0_LINK100 => Location: PIN_C14, I/O Standard: 3.3-V LVTTL, Current Strength: Default
|
||||
-- ENET0_MDIO => Location: PIN_B21, I/O Standard: 2.5 V, Current Strength: Default
|
||||
-- ENET0_RX_CLK => Location: PIN_A15, I/O Standard: 2.5 V, Current Strength: Default
|
||||
-- ENET0_RX_COL => Location: PIN_E15, I/O Standard: 2.5 V, Current Strength: Default
|
||||
-- ENET0_RX_CRS => Location: PIN_D15, I/O Standard: 2.5 V, Current Strength: Default
|
||||
-- ENET0_RX_DATA[0] => Location: PIN_C16, I/O Standard: 2.5 V, Current Strength: Default
|
||||
-- ENET0_RX_DATA[1] => Location: PIN_D16, I/O Standard: 2.5 V, Current Strength: Default
|
||||
-- ENET0_RX_DATA[2] => Location: PIN_D17, I/O Standard: 2.5 V, Current Strength: Default
|
||||
-- ENET0_RX_DATA[3] => Location: PIN_C15, I/O Standard: 2.5 V, Current Strength: Default
|
||||
-- ENET0_RX_DV => Location: PIN_C17, I/O Standard: 2.5 V, Current Strength: Default
|
||||
-- ENET0_RX_ER => Location: PIN_D18, I/O Standard: 2.5 V, Current Strength: Default
|
||||
-- ENET0_TX_CLK => Location: PIN_B17, I/O Standard: 2.5 V, Current Strength: Default
|
||||
-- ENET1_INT_N => Location: PIN_D24, I/O Standard: 2.5 V, Current Strength: Default
|
||||
-- ENET1_LINK100 => Location: PIN_D13, I/O Standard: 3.3-V LVTTL, Current Strength: Default
|
||||
-- ENET1_MDIO => Location: PIN_D25, I/O Standard: 2.5 V, Current Strength: Default
|
||||
-- ENET1_RX_CLK => Location: PIN_B15, I/O Standard: 2.5 V, Current Strength: Default
|
||||
-- ENET1_RX_COL => Location: PIN_B22, I/O Standard: 2.5 V, Current Strength: Default
|
||||
-- ENET1_RX_CRS => Location: PIN_D20, I/O Standard: 2.5 V, Current Strength: Default
|
||||
-- ENET1_RX_DATA[0] => Location: PIN_B23, I/O Standard: 2.5 V, Current Strength: Default
|
||||
-- ENET1_RX_DATA[1] => Location: PIN_C21, I/O Standard: 2.5 V, Current Strength: Default
|
||||
-- ENET1_RX_DATA[2] => Location: PIN_A23, I/O Standard: 2.5 V, Current Strength: Default
|
||||
-- ENET1_RX_DATA[3] => Location: PIN_D21, I/O Standard: 2.5 V, Current Strength: Default
|
||||
-- ENET1_RX_DV => Location: PIN_A22, I/O Standard: 2.5 V, Current Strength: Default
|
||||
-- ENET1_RX_ER => Location: PIN_C24, I/O Standard: 2.5 V, Current Strength: Default
|
||||
-- ENET1_TX_CLK => Location: PIN_C22, I/O Standard: 2.5 V, Current Strength: Default
|
||||
-- ENETCLK_25 => Location: PIN_A14, I/O Standard: 3.3-V LVTTL, Current Strength: Default
|
||||
-- FL_RY => Location: PIN_Y1, I/O Standard: 3.3-V LVTTL, Current Strength: Default
|
||||
-- HSMC_CLKIN0 => Location: PIN_AH15, I/O Standard: 3.3-V LVTTL, Current Strength: Default
|
||||
-- IRDA_RXD => Location: PIN_Y15, I/O Standard: 3.3-V LVTTL, Current Strength: Default
|
||||
-- KEY[0] => Location: PIN_M23, I/O Standard: 2.5 V, Current Strength: Default
|
||||
-- KEY[1] => Location: PIN_M21, I/O Standard: 2.5 V, Current Strength: Default
|
||||
-- KEY[2] => Location: PIN_N21, I/O Standard: 2.5 V, Current Strength: Default
|
||||
-- KEY[3] => Location: PIN_R24, I/O Standard: 2.5 V, Current Strength: Default
|
||||
-- OTG_INT => Location: PIN_D5, I/O Standard: 3.3-V LVTTL, Current Strength: Default
|
||||
-- SD_WP_N => Location: PIN_AF14, I/O Standard: 3.3-V LVTTL, Current Strength: Default
|
||||
-- SMA_CLKIN => Location: PIN_AH14, I/O Standard: 3.3-V LVTTL, Current Strength: Default
|
||||
-- SW[10] => Location: PIN_AC24, I/O Standard: 2.5 V, Current Strength: Default
|
||||
-- SW[11] => Location: PIN_AB24, I/O Standard: 2.5 V, Current Strength: Default
|
||||
-- SW[12] => Location: PIN_AB23, I/O Standard: 2.5 V, Current Strength: Default
|
||||
-- SW[13] => Location: PIN_AA24, I/O Standard: 2.5 V, Current Strength: Default
|
||||
-- SW[14] => Location: PIN_AA23, I/O Standard: 2.5 V, Current Strength: Default
|
||||
-- SW[15] => Location: PIN_AA22, I/O Standard: 2.5 V, Current Strength: Default
|
||||
-- SW[16] => Location: PIN_Y24, I/O Standard: 2.5 V, Current Strength: Default
|
||||
-- SW[17] => Location: PIN_Y23, I/O Standard: 2.5 V, Current Strength: Default
|
||||
-- SW[8] => Location: PIN_AC25, I/O Standard: 2.5 V, Current Strength: Default
|
||||
-- SW[9] => Location: PIN_AB25, I/O Standard: 2.5 V, Current Strength: Default
|
||||
-- TD_CLK27 => Location: PIN_B14, I/O Standard: 3.3-V LVTTL, Current Strength: Default
|
||||
-- TD_DATA[0] => Location: PIN_E8, I/O Standard: 3.3-V LVTTL, Current Strength: Default
|
||||
-- TD_DATA[1] => Location: PIN_A7, I/O Standard: 3.3-V LVTTL, Current Strength: Default
|
||||
-- TD_DATA[2] => Location: PIN_D8, I/O Standard: 3.3-V LVTTL, Current Strength: Default
|
||||
-- TD_DATA[3] => Location: PIN_C7, I/O Standard: 3.3-V LVTTL, Current Strength: Default
|
||||
-- TD_DATA[4] => Location: PIN_D7, I/O Standard: 3.3-V LVTTL, Current Strength: Default
|
||||
-- TD_DATA[5] => Location: PIN_D6, I/O Standard: 3.3-V LVTTL, Current Strength: Default
|
||||
-- TD_DATA[6] => Location: PIN_E7, I/O Standard: 3.3-V LVTTL, Current Strength: Default
|
||||
-- TD_DATA[7] => Location: PIN_F7, I/O Standard: 3.3-V LVTTL, Current Strength: Default
|
||||
-- TD_HS => Location: PIN_E5, I/O Standard: 3.3-V LVTTL, Current Strength: Default
|
||||
-- TD_VS => Location: PIN_E4, I/O Standard: 3.3-V LVTTL, Current Strength: Default
|
||||
-- UART_RTS => Location: PIN_J13, I/O Standard: 3.3-V LVTTL, Current Strength: Default
|
||||
-- UART_RXD => Location: PIN_G12, I/O Standard: 3.3-V LVTTL, Current Strength: Default
|
||||
-- ~ALTERA_ASDO_DATA1~ => Location: PIN_F4, I/O Standard: 3.3-V LVTTL, Current Strength: Default
|
||||
-- ~ALTERA_FLASH_nCE_nCSO~ => Location: PIN_E2, I/O Standard: 3.3-V LVTTL, Current Strength: Default
|
||||
-- ~ALTERA_DCLK~ => Location: PIN_P3, I/O Standard: 3.3-V LVTTL, Current Strength: Default
|
||||
-- ~ALTERA_DATA0~ => Location: PIN_N7, I/O Standard: 3.3-V LVTTL, Current Strength: Default
|
||||
-- ~ALTERA_nCEO~ => Location: PIN_P28, I/O Standard: 2.5 V, Current Strength: 8mA
|
||||
|
||||
|
||||
ARCHITECTURE structure OF hard_block IS
|
||||
SIGNAL gnd : std_logic := '0';
|
||||
SIGNAL vcc : std_logic := '1';
|
||||
SIGNAL unknown : std_logic := 'X';
|
||||
SIGNAL ww_devoe : std_logic;
|
||||
SIGNAL ww_devclrn : std_logic;
|
||||
SIGNAL ww_devpor : std_logic;
|
||||
SIGNAL \AUD_ADCDAT~padout\ : std_logic;
|
||||
SIGNAL \CLOCK2_50~padout\ : std_logic;
|
||||
SIGNAL \CLOCK3_50~padout\ : std_logic;
|
||||
SIGNAL \CLOCK_50~padout\ : std_logic;
|
||||
SIGNAL \ENET0_INT_N~padout\ : std_logic;
|
||||
SIGNAL \ENET0_LINK100~padout\ : std_logic;
|
||||
SIGNAL \ENET0_MDIO~padout\ : std_logic;
|
||||
SIGNAL \ENET0_RX_CLK~padout\ : std_logic;
|
||||
SIGNAL \ENET0_RX_COL~padout\ : std_logic;
|
||||
SIGNAL \ENET0_RX_CRS~padout\ : std_logic;
|
||||
SIGNAL \ENET0_RX_DATA[0]~padout\ : std_logic;
|
||||
SIGNAL \ENET0_RX_DATA[1]~padout\ : std_logic;
|
||||
SIGNAL \ENET0_RX_DATA[2]~padout\ : std_logic;
|
||||
SIGNAL \ENET0_RX_DATA[3]~padout\ : std_logic;
|
||||
SIGNAL \ENET0_RX_DV~padout\ : std_logic;
|
||||
SIGNAL \ENET0_RX_ER~padout\ : std_logic;
|
||||
SIGNAL \ENET0_TX_CLK~padout\ : std_logic;
|
||||
SIGNAL \ENET1_INT_N~padout\ : std_logic;
|
||||
SIGNAL \ENET1_LINK100~padout\ : std_logic;
|
||||
SIGNAL \ENET1_MDIO~padout\ : std_logic;
|
||||
SIGNAL \ENET1_RX_CLK~padout\ : std_logic;
|
||||
SIGNAL \ENET1_RX_COL~padout\ : std_logic;
|
||||
SIGNAL \ENET1_RX_CRS~padout\ : std_logic;
|
||||
SIGNAL \ENET1_RX_DATA[0]~padout\ : std_logic;
|
||||
SIGNAL \ENET1_RX_DATA[1]~padout\ : std_logic;
|
||||
SIGNAL \ENET1_RX_DATA[2]~padout\ : std_logic;
|
||||
SIGNAL \ENET1_RX_DATA[3]~padout\ : std_logic;
|
||||
SIGNAL \ENET1_RX_DV~padout\ : std_logic;
|
||||
SIGNAL \ENET1_RX_ER~padout\ : std_logic;
|
||||
SIGNAL \ENET1_TX_CLK~padout\ : std_logic;
|
||||
SIGNAL \ENETCLK_25~padout\ : std_logic;
|
||||
SIGNAL \FL_RY~padout\ : std_logic;
|
||||
SIGNAL \HSMC_CLKIN0~padout\ : std_logic;
|
||||
SIGNAL \IRDA_RXD~padout\ : std_logic;
|
||||
SIGNAL \KEY[0]~padout\ : std_logic;
|
||||
SIGNAL \KEY[1]~padout\ : std_logic;
|
||||
SIGNAL \KEY[2]~padout\ : std_logic;
|
||||
SIGNAL \KEY[3]~padout\ : std_logic;
|
||||
SIGNAL \OTG_INT~padout\ : std_logic;
|
||||
SIGNAL \SD_WP_N~padout\ : std_logic;
|
||||
SIGNAL \SMA_CLKIN~padout\ : std_logic;
|
||||
SIGNAL \TD_CLK27~padout\ : std_logic;
|
||||
SIGNAL \TD_DATA[0]~padout\ : std_logic;
|
||||
SIGNAL \TD_DATA[1]~padout\ : std_logic;
|
||||
SIGNAL \TD_DATA[2]~padout\ : std_logic;
|
||||
SIGNAL \TD_DATA[3]~padout\ : std_logic;
|
||||
SIGNAL \TD_DATA[4]~padout\ : std_logic;
|
||||
SIGNAL \TD_DATA[5]~padout\ : std_logic;
|
||||
SIGNAL \TD_DATA[6]~padout\ : std_logic;
|
||||
SIGNAL \TD_DATA[7]~padout\ : std_logic;
|
||||
SIGNAL \TD_HS~padout\ : std_logic;
|
||||
SIGNAL \TD_VS~padout\ : std_logic;
|
||||
SIGNAL \UART_RTS~padout\ : std_logic;
|
||||
SIGNAL \UART_RXD~padout\ : std_logic;
|
||||
SIGNAL \~ALTERA_ASDO_DATA1~~padout\ : std_logic;
|
||||
SIGNAL \~ALTERA_FLASH_nCE_nCSO~~padout\ : std_logic;
|
||||
SIGNAL \~ALTERA_DATA0~~padout\ : std_logic;
|
||||
SIGNAL \AUD_ADCDAT~ibuf_o\ : std_logic;
|
||||
SIGNAL \CLOCK2_50~ibuf_o\ : std_logic;
|
||||
SIGNAL \CLOCK3_50~ibuf_o\ : std_logic;
|
||||
SIGNAL \CLOCK_50~ibuf_o\ : std_logic;
|
||||
SIGNAL \ENET0_INT_N~ibuf_o\ : std_logic;
|
||||
SIGNAL \ENET0_LINK100~ibuf_o\ : std_logic;
|
||||
SIGNAL \ENET0_MDIO~ibuf_o\ : std_logic;
|
||||
SIGNAL \ENET0_RX_CLK~ibuf_o\ : std_logic;
|
||||
SIGNAL \ENET0_RX_COL~ibuf_o\ : std_logic;
|
||||
SIGNAL \ENET0_RX_CRS~ibuf_o\ : std_logic;
|
||||
SIGNAL \ENET0_RX_DATA[0]~ibuf_o\ : std_logic;
|
||||
SIGNAL \ENET0_RX_DATA[1]~ibuf_o\ : std_logic;
|
||||
SIGNAL \ENET0_RX_DATA[2]~ibuf_o\ : std_logic;
|
||||
SIGNAL \ENET0_RX_DATA[3]~ibuf_o\ : std_logic;
|
||||
SIGNAL \ENET0_RX_DV~ibuf_o\ : std_logic;
|
||||
SIGNAL \ENET0_RX_ER~ibuf_o\ : std_logic;
|
||||
SIGNAL \ENET0_TX_CLK~ibuf_o\ : std_logic;
|
||||
SIGNAL \ENET1_INT_N~ibuf_o\ : std_logic;
|
||||
SIGNAL \ENET1_LINK100~ibuf_o\ : std_logic;
|
||||
SIGNAL \ENET1_MDIO~ibuf_o\ : std_logic;
|
||||
SIGNAL \ENET1_RX_CLK~ibuf_o\ : std_logic;
|
||||
SIGNAL \ENET1_RX_COL~ibuf_o\ : std_logic;
|
||||
SIGNAL \ENET1_RX_CRS~ibuf_o\ : std_logic;
|
||||
SIGNAL \ENET1_RX_DATA[0]~ibuf_o\ : std_logic;
|
||||
SIGNAL \ENET1_RX_DATA[1]~ibuf_o\ : std_logic;
|
||||
SIGNAL \ENET1_RX_DATA[2]~ibuf_o\ : std_logic;
|
||||
SIGNAL \ENET1_RX_DATA[3]~ibuf_o\ : std_logic;
|
||||
SIGNAL \ENET1_RX_DV~ibuf_o\ : std_logic;
|
||||
SIGNAL \ENET1_RX_ER~ibuf_o\ : std_logic;
|
||||
SIGNAL \ENET1_TX_CLK~ibuf_o\ : std_logic;
|
||||
SIGNAL \ENETCLK_25~ibuf_o\ : std_logic;
|
||||
SIGNAL \FL_RY~ibuf_o\ : std_logic;
|
||||
SIGNAL \HSMC_CLKIN0~ibuf_o\ : std_logic;
|
||||
SIGNAL \IRDA_RXD~ibuf_o\ : std_logic;
|
||||
SIGNAL \KEY[0]~ibuf_o\ : std_logic;
|
||||
SIGNAL \KEY[1]~ibuf_o\ : std_logic;
|
||||
SIGNAL \KEY[2]~ibuf_o\ : std_logic;
|
||||
SIGNAL \KEY[3]~ibuf_o\ : std_logic;
|
||||
SIGNAL \OTG_INT~ibuf_o\ : std_logic;
|
||||
SIGNAL \SD_WP_N~ibuf_o\ : std_logic;
|
||||
SIGNAL \SMA_CLKIN~ibuf_o\ : std_logic;
|
||||
SIGNAL \SW[10]~ibuf_o\ : std_logic;
|
||||
SIGNAL \SW[11]~ibuf_o\ : std_logic;
|
||||
SIGNAL \SW[12]~ibuf_o\ : std_logic;
|
||||
SIGNAL \SW[13]~ibuf_o\ : std_logic;
|
||||
SIGNAL \SW[14]~ibuf_o\ : std_logic;
|
||||
SIGNAL \SW[15]~ibuf_o\ : std_logic;
|
||||
SIGNAL \SW[16]~ibuf_o\ : std_logic;
|
||||
SIGNAL \SW[17]~ibuf_o\ : std_logic;
|
||||
SIGNAL \SW[8]~ibuf_o\ : std_logic;
|
||||
SIGNAL \SW[9]~ibuf_o\ : std_logic;
|
||||
SIGNAL \TD_CLK27~ibuf_o\ : std_logic;
|
||||
SIGNAL \TD_DATA[0]~ibuf_o\ : std_logic;
|
||||
SIGNAL \TD_DATA[1]~ibuf_o\ : std_logic;
|
||||
SIGNAL \TD_DATA[2]~ibuf_o\ : std_logic;
|
||||
SIGNAL \TD_DATA[3]~ibuf_o\ : std_logic;
|
||||
SIGNAL \TD_DATA[4]~ibuf_o\ : std_logic;
|
||||
SIGNAL \TD_DATA[5]~ibuf_o\ : std_logic;
|
||||
SIGNAL \TD_DATA[6]~ibuf_o\ : std_logic;
|
||||
SIGNAL \TD_DATA[7]~ibuf_o\ : std_logic;
|
||||
SIGNAL \TD_HS~ibuf_o\ : std_logic;
|
||||
SIGNAL \TD_VS~ibuf_o\ : std_logic;
|
||||
SIGNAL \UART_RTS~ibuf_o\ : std_logic;
|
||||
SIGNAL \UART_RXD~ibuf_o\ : std_logic;
|
||||
SIGNAL \~ALTERA_ASDO_DATA1~~ibuf_o\ : std_logic;
|
||||
SIGNAL \~ALTERA_FLASH_nCE_nCSO~~ibuf_o\ : std_logic;
|
||||
SIGNAL \~ALTERA_DATA0~~ibuf_o\ : std_logic;
|
||||
SIGNAL SW : std_logic_vector(7 DOWNTO 0);
|
||||
|
||||
BEGIN
|
||||
|
||||
ww_devoe <= devoe;
|
||||
ww_devclrn <= devclrn;
|
||||
ww_devpor <= devpor;
|
||||
END structure;
|
||||
|
||||
|
||||
LIBRARY CYCLONEIVE;
|
||||
LIBRARY IEEE;
|
||||
USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
ENTITY EqCmpDemo IS
|
||||
PORT (
|
||||
LEDG : OUT std_logic_vector(0 DOWNTO 0);
|
||||
SW : IN std_logic_vector(7 DOWNTO 0)
|
||||
);
|
||||
END EqCmpDemo;
|
||||
|
||||
-- Design Ports Information
|
||||
-- LEDG[0] => Location: PIN_E21, I/O Standard: 2.5 V, Current Strength: Default
|
||||
-- SW[4] => Location: PIN_AB27, I/O Standard: 2.5 V, Current Strength: Default
|
||||
-- SW[5] => Location: PIN_AC26, I/O Standard: 2.5 V, Current Strength: Default
|
||||
-- SW[1] => Location: PIN_AC28, I/O Standard: 2.5 V, Current Strength: Default
|
||||
-- SW[0] => Location: PIN_AB28, I/O Standard: 2.5 V, Current Strength: Default
|
||||
-- SW[6] => Location: PIN_AD26, I/O Standard: 2.5 V, Current Strength: Default
|
||||
-- SW[7] => Location: PIN_AB26, I/O Standard: 2.5 V, Current Strength: Default
|
||||
-- SW[3] => Location: PIN_AD27, I/O Standard: 2.5 V, Current Strength: Default
|
||||
-- SW[2] => Location: PIN_AC27, I/O Standard: 2.5 V, Current Strength: Default
|
||||
|
||||
|
||||
ARCHITECTURE structure OF EqCmpDemo IS
|
||||
SIGNAL gnd : std_logic := '0';
|
||||
SIGNAL vcc : std_logic := '1';
|
||||
SIGNAL unknown : std_logic := 'X';
|
||||
SIGNAL devoe : std_logic := '1';
|
||||
SIGNAL devclrn : std_logic := '1';
|
||||
SIGNAL devpor : std_logic := '1';
|
||||
SIGNAL ww_devoe : std_logic;
|
||||
SIGNAL ww_devclrn : std_logic;
|
||||
SIGNAL ww_devpor : std_logic;
|
||||
SIGNAL ww_LEDG : std_logic_vector(0 DOWNTO 0);
|
||||
SIGNAL ww_SW : std_logic_vector(7 DOWNTO 0);
|
||||
SIGNAL \LEDG[0]~output_o\ : std_logic;
|
||||
SIGNAL \SW[1]~input_o\ : std_logic;
|
||||
SIGNAL \SW[0]~input_o\ : std_logic;
|
||||
SIGNAL \SW[5]~input_o\ : std_logic;
|
||||
SIGNAL \SW[4]~input_o\ : std_logic;
|
||||
SIGNAL \inst|inst~0_combout\ : std_logic;
|
||||
SIGNAL \SW[7]~input_o\ : std_logic;
|
||||
SIGNAL \SW[6]~input_o\ : std_logic;
|
||||
SIGNAL \SW[3]~input_o\ : std_logic;
|
||||
SIGNAL \SW[2]~input_o\ : std_logic;
|
||||
SIGNAL \inst|inst~1_combout\ : std_logic;
|
||||
SIGNAL \inst|inst~combout\ : std_logic;
|
||||
|
||||
COMPONENT hard_block
|
||||
PORT (
|
||||
devoe : IN std_logic;
|
||||
devclrn : IN std_logic;
|
||||
devpor : IN std_logic);
|
||||
END COMPONENT;
|
||||
|
||||
BEGIN
|
||||
|
||||
LEDG <= ww_LEDG;
|
||||
ww_SW <= SW;
|
||||
ww_devoe <= devoe;
|
||||
ww_devclrn <= devclrn;
|
||||
ww_devpor <= devpor;
|
||||
auto_generated_inst : hard_block
|
||||
PORT MAP (
|
||||
devoe => ww_devoe,
|
||||
devclrn => ww_devclrn,
|
||||
devpor => ww_devpor);
|
||||
|
||||
-- Location: IOOBUF_X107_Y73_N9
|
||||
\LEDG[0]~output\ : cycloneive_io_obuf
|
||||
-- pragma translate_off
|
||||
GENERIC MAP (
|
||||
bus_hold => "false",
|
||||
open_drain_output => "false")
|
||||
-- pragma translate_on
|
||||
PORT MAP (
|
||||
i => \inst|inst~combout\,
|
||||
devoe => ww_devoe,
|
||||
o => \LEDG[0]~output_o\);
|
||||
|
||||
-- Location: IOIBUF_X115_Y14_N1
|
||||
\SW[1]~input\ : cycloneive_io_ibuf
|
||||
-- pragma translate_off
|
||||
GENERIC MAP (
|
||||
bus_hold => "false",
|
||||
simulate_z_as => "z")
|
||||
-- pragma translate_on
|
||||
PORT MAP (
|
||||
i => ww_SW(1),
|
||||
o => \SW[1]~input_o\);
|
||||
|
||||
-- Location: IOIBUF_X115_Y17_N1
|
||||
\SW[0]~input\ : cycloneive_io_ibuf
|
||||
-- pragma translate_off
|
||||
GENERIC MAP (
|
||||
bus_hold => "false",
|
||||
simulate_z_as => "z")
|
||||
-- pragma translate_on
|
||||
PORT MAP (
|
||||
i => ww_SW(0),
|
||||
o => \SW[0]~input_o\);
|
||||
|
||||
-- Location: IOIBUF_X115_Y11_N8
|
||||
\SW[5]~input\ : cycloneive_io_ibuf
|
||||
-- pragma translate_off
|
||||
GENERIC MAP (
|
||||
bus_hold => "false",
|
||||
simulate_z_as => "z")
|
||||
-- pragma translate_on
|
||||
PORT MAP (
|
||||
i => ww_SW(5),
|
||||
o => \SW[5]~input_o\);
|
||||
|
||||
-- Location: IOIBUF_X115_Y18_N8
|
||||
\SW[4]~input\ : cycloneive_io_ibuf
|
||||
-- pragma translate_off
|
||||
GENERIC MAP (
|
||||
bus_hold => "false",
|
||||
simulate_z_as => "z")
|
||||
-- pragma translate_on
|
||||
PORT MAP (
|
||||
i => ww_SW(4),
|
||||
o => \SW[4]~input_o\);
|
||||
|
||||
-- Location: LCCOMB_X114_Y15_N24
|
||||
\inst|inst~0\ : cycloneive_lcell_comb
|
||||
-- Equation(s):
|
||||
-- \inst|inst~0_combout\ = (\SW[1]~input_o\ & (\SW[5]~input_o\ & (\SW[0]~input_o\ $ (!\SW[4]~input_o\)))) # (!\SW[1]~input_o\ & (!\SW[5]~input_o\ & (\SW[0]~input_o\ $ (!\SW[4]~input_o\))))
|
||||
|
||||
-- pragma translate_off
|
||||
GENERIC MAP (
|
||||
lut_mask => "1000010000100001",
|
||||
sum_lutc_input => "datac")
|
||||
-- pragma translate_on
|
||||
PORT MAP (
|
||||
dataa => \SW[1]~input_o\,
|
||||
datab => \SW[0]~input_o\,
|
||||
datac => \SW[5]~input_o\,
|
||||
datad => \SW[4]~input_o\,
|
||||
combout => \inst|inst~0_combout\);
|
||||
|
||||
-- Location: IOIBUF_X115_Y15_N1
|
||||
\SW[7]~input\ : cycloneive_io_ibuf
|
||||
-- pragma translate_off
|
||||
GENERIC MAP (
|
||||
bus_hold => "false",
|
||||
simulate_z_as => "z")
|
||||
-- pragma translate_on
|
||||
PORT MAP (
|
||||
i => ww_SW(7),
|
||||
o => \SW[7]~input_o\);
|
||||
|
||||
-- Location: IOIBUF_X115_Y10_N1
|
||||
\SW[6]~input\ : cycloneive_io_ibuf
|
||||
-- pragma translate_off
|
||||
GENERIC MAP (
|
||||
bus_hold => "false",
|
||||
simulate_z_as => "z")
|
||||
-- pragma translate_on
|
||||
PORT MAP (
|
||||
i => ww_SW(6),
|
||||
o => \SW[6]~input_o\);
|
||||
|
||||
-- Location: IOIBUF_X115_Y13_N8
|
||||
\SW[3]~input\ : cycloneive_io_ibuf
|
||||
-- pragma translate_off
|
||||
GENERIC MAP (
|
||||
bus_hold => "false",
|
||||
simulate_z_as => "z")
|
||||
-- pragma translate_on
|
||||
PORT MAP (
|
||||
i => ww_SW(3),
|
||||
o => \SW[3]~input_o\);
|
||||
|
||||
-- Location: IOIBUF_X115_Y15_N8
|
||||
\SW[2]~input\ : cycloneive_io_ibuf
|
||||
-- pragma translate_off
|
||||
GENERIC MAP (
|
||||
bus_hold => "false",
|
||||
simulate_z_as => "z")
|
||||
-- pragma translate_on
|
||||
PORT MAP (
|
||||
i => ww_SW(2),
|
||||
o => \SW[2]~input_o\);
|
||||
|
||||
-- Location: LCCOMB_X114_Y15_N10
|
||||
\inst|inst~1\ : cycloneive_lcell_comb
|
||||
-- Equation(s):
|
||||
-- \inst|inst~1_combout\ = (\SW[7]~input_o\ & (\SW[3]~input_o\ & (\SW[6]~input_o\ $ (!\SW[2]~input_o\)))) # (!\SW[7]~input_o\ & (!\SW[3]~input_o\ & (\SW[6]~input_o\ $ (!\SW[2]~input_o\))))
|
||||
|
||||
-- pragma translate_off
|
||||
GENERIC MAP (
|
||||
lut_mask => "1000010000100001",
|
||||
sum_lutc_input => "datac")
|
||||
-- pragma translate_on
|
||||
PORT MAP (
|
||||
dataa => \SW[7]~input_o\,
|
||||
datab => \SW[6]~input_o\,
|
||||
datac => \SW[3]~input_o\,
|
||||
datad => \SW[2]~input_o\,
|
||||
combout => \inst|inst~1_combout\);
|
||||
|
||||
-- Location: LCCOMB_X114_Y15_N28
|
||||
\inst|inst\ : cycloneive_lcell_comb
|
||||
-- Equation(s):
|
||||
-- \inst|inst~combout\ = (\inst|inst~0_combout\ & \inst|inst~1_combout\)
|
||||
|
||||
-- pragma translate_off
|
||||
GENERIC MAP (
|
||||
lut_mask => "1100110000000000",
|
||||
sum_lutc_input => "datac")
|
||||
-- pragma translate_on
|
||||
PORT MAP (
|
||||
datab => \inst|inst~0_combout\,
|
||||
datad => \inst|inst~1_combout\,
|
||||
combout => \inst|inst~combout\);
|
||||
|
||||
ww_LEDG(0) <= \LEDG[0]~output_o\;
|
||||
END structure;
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
vendor_name = ModelSim
|
||||
source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmp4.bdf
|
||||
source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.bdf
|
||||
source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.cbx.xml
|
||||
design_name = hard_block
|
||||
design_name = EqCmpDemo
|
||||
instance = comp, \LEDG[0]~output\, LEDG[0]~output, EqCmpDemo, 1
|
||||
instance = comp, \SW[1]~input\, SW[1]~input, EqCmpDemo, 1
|
||||
instance = comp, \SW[0]~input\, SW[0]~input, EqCmpDemo, 1
|
||||
instance = comp, \SW[5]~input\, SW[5]~input, EqCmpDemo, 1
|
||||
instance = comp, \SW[4]~input\, SW[4]~input, EqCmpDemo, 1
|
||||
instance = comp, \inst|inst~0\, inst|inst~0, EqCmpDemo, 1
|
||||
instance = comp, \SW[7]~input\, SW[7]~input, EqCmpDemo, 1
|
||||
instance = comp, \SW[6]~input\, SW[6]~input, EqCmpDemo, 1
|
||||
instance = comp, \SW[3]~input\, SW[3]~input, EqCmpDemo, 1
|
||||
instance = comp, \SW[2]~input\, SW[2]~input, EqCmpDemo, 1
|
||||
instance = comp, \inst|inst~1\, inst|inst~1, EqCmpDemo, 1
|
||||
instance = comp, \inst|inst\, inst|inst, EqCmpDemo, 1
|
||||
Loading…
Reference in New Issue