TiagoRG
/
uaveiro-leci
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

LSD aula01 initial commit, base VHDL files, to be finished along the hardware

This commit is contained in:
TiagoRG 2023-02-20 22:37:32 +00:00
parent 090a36d8e4
commit 4fbb93468b
230 changed files with 13284 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

114
1ano/2semestre/lsd/aula01/part1/GateDemo.bdf Normal file
View File

@ -0,0 +1,114 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "graphic" (version "1.4"))
(pin
(input)
(rect 344 240 512 256)
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
(text "SW[0]" (rect 5 0 39 13)(font "Intel Clear" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
)
(pin
(input)
(rect 344 256 512 272)
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
(text "SW[1]" (rect 5 0 39 13)(font "Intel Clear" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
)
(pin
(output)
(rect 592 248 768 264)
(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
(text "LEDR[0]" (rect 90 0 132 11)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
(line (pt 52 4)(pt 78 4))
(line (pt 52 12)(pt 78 12))
(line (pt 52 12)(pt 52 4))
(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
)
(symbol
(rect 520 232 584 280)
(text "AND2" (rect 1 0 29 10)(font "Arial" (font_size 6)))
(text "inst" (rect 3 37 21 48)(font "Arial" ))
(port
(pt 0 16)
(input)
(text "IN1" (rect 2 7 23 18)(font "Courier New" (bold))(invisible))
(text "IN1" (rect 2 7 23 18)(font "Courier New" (bold))(invisible))
(line (pt 0 16)(pt 14 16))
)
(port
(pt 0 32)
(input)
(text "IN2" (rect 2 23 23 34)(font "Courier New" (bold))(invisible))
(text "IN2" (rect 2 23 23 34)(font "Courier New" (bold))(invisible))
(line (pt 0 32)(pt 14 32))
)
(port
(pt 64 24)
(output)
(text "OUT" (rect 48 15 69 26)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 69 26)(font "Courier New" (bold))(invisible))
(line (pt 42 24)(pt 64 24))
)
(drawing
(line (pt 14 12)(pt 30 12))
(line (pt 14 37)(pt 31 37))
(line (pt 14 12)(pt 14 37))
(arc (pt 31 37)(pt 30 12)(rect 18 12 43 37))
)
)
(connector
(pt 512 248)
(pt 520 248)
)
(connector
(pt 512 264)
(pt 520 264)
)
(connector
(pt 584 256)
(pt 592 256)
)

31
1ano/2semestre/lsd/aula01/part1/GateDemo.qpf Normal file
View File

@ -0,0 +1,31 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2020 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
# Date created = 14:43:19 February 18, 2023
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "20.1"
DATE = "14:43:19 February 18, 2023"
# Revisions
PROJECT_REVISION = "GateDemo"

582
1ano/2semestre/lsd/aula01/part1/GateDemo.qsf Normal file
View File

@ -0,0 +1,582 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2020 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
# Date created = 14:43:19 February 18, 2023
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# GateDemo_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE115F29C7
set_global_assignment -name TOP_LEVEL_ENTITY GateDemo
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:43:19 FEBRUARY 18, 2023"
set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
set_global_assignment -name BDF_FILE GateDemo.bdf
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VECTOR_WAVEFORM_FILE GateDemo.vwf
set_location_assignment PIN_Y2 -to CLOCK_50
set_location_assignment PIN_AG14 -to CLOCK2_50
set_location_assignment PIN_AG15 -to CLOCK3_50
set_location_assignment PIN_AH14 -to SMA_CLKIN
set_location_assignment PIN_AE23 -to SMA_CLKOUT
set_location_assignment PIN_M23 -to KEY[0]
set_location_assignment PIN_M21 -to KEY[1]
set_location_assignment PIN_N21 -to KEY[2]
set_location_assignment PIN_R24 -to KEY[3]
set_location_assignment PIN_AB28 -to SW[0]
set_location_assignment PIN_AC28 -to SW[1]
set_location_assignment PIN_AC27 -to SW[2]
set_location_assignment PIN_AD27 -to SW[3]
set_location_assignment PIN_AB27 -to SW[4]
set_location_assignment PIN_AC26 -to SW[5]
set_location_assignment PIN_AD26 -to SW[6]
set_location_assignment PIN_AB26 -to SW[7]
set_location_assignment PIN_AC25 -to SW[8]
set_location_assignment PIN_AB25 -to SW[9]
set_location_assignment PIN_AC24 -to SW[10]
set_location_assignment PIN_AB24 -to SW[11]
set_location_assignment PIN_AB23 -to SW[12]
set_location_assignment PIN_AA24 -to SW[13]
set_location_assignment PIN_AA23 -to SW[14]
set_location_assignment PIN_AA22 -to SW[15]
set_location_assignment PIN_Y24 -to SW[16]
set_location_assignment PIN_Y23 -to SW[17]
set_location_assignment PIN_G19 -to LEDR[0]
set_location_assignment PIN_F19 -to LEDR[1]
set_location_assignment PIN_E19 -to LEDR[2]
set_location_assignment PIN_F21 -to LEDR[3]
set_location_assignment PIN_F18 -to LEDR[4]
set_location_assignment PIN_E18 -to LEDR[5]
set_location_assignment PIN_J19 -to LEDR[6]
set_location_assignment PIN_H19 -to LEDR[7]
set_location_assignment PIN_J17 -to LEDR[8]
set_location_assignment PIN_G17 -to LEDR[9]
set_location_assignment PIN_J15 -to LEDR[10]
set_location_assignment PIN_H16 -to LEDR[11]
set_location_assignment PIN_J16 -to LEDR[12]
set_location_assignment PIN_H17 -to LEDR[13]
set_location_assignment PIN_F15 -to LEDR[14]
set_location_assignment PIN_G15 -to LEDR[15]
set_location_assignment PIN_G16 -to LEDR[16]
set_location_assignment PIN_H15 -to LEDR[17]
set_location_assignment PIN_E21 -to LEDG[0]
set_location_assignment PIN_E22 -to LEDG[1]
set_location_assignment PIN_E25 -to LEDG[2]
set_location_assignment PIN_E24 -to LEDG[3]
set_location_assignment PIN_H21 -to LEDG[4]
set_location_assignment PIN_G20 -to LEDG[5]
set_location_assignment PIN_G22 -to LEDG[6]
set_location_assignment PIN_G21 -to LEDG[7]
set_location_assignment PIN_F17 -to LEDG[8]
set_location_assignment PIN_G18 -to HEX0[0]
set_location_assignment PIN_F22 -to HEX0[1]
set_location_assignment PIN_E17 -to HEX0[2]
set_location_assignment PIN_L26 -to HEX0[3]
set_location_assignment PIN_L25 -to HEX0[4]
set_location_assignment PIN_J22 -to HEX0[5]
set_location_assignment PIN_H22 -to HEX0[6]
set_location_assignment PIN_M24 -to HEX1[0]
set_location_assignment PIN_Y22 -to HEX1[1]
set_location_assignment PIN_W21 -to HEX1[2]
set_location_assignment PIN_W22 -to HEX1[3]
set_location_assignment PIN_W25 -to HEX1[4]
set_location_assignment PIN_U23 -to HEX1[5]
set_location_assignment PIN_U24 -to HEX1[6]
set_location_assignment PIN_AA25 -to HEX2[0]
set_location_assignment PIN_AA26 -to HEX2[1]
set_location_assignment PIN_Y25 -to HEX2[2]
set_location_assignment PIN_W26 -to HEX2[3]
set_location_assignment PIN_Y26 -to HEX2[4]
set_location_assignment PIN_W27 -to HEX2[5]
set_location_assignment PIN_W28 -to HEX2[6]
set_location_assignment PIN_V21 -to HEX3[0]
set_location_assignment PIN_U21 -to HEX3[1]
set_location_assignment PIN_AB20 -to HEX3[2]
set_location_assignment PIN_AA21 -to HEX3[3]
set_location_assignment PIN_AD24 -to HEX3[4]
set_location_assignment PIN_AF23 -to HEX3[5]
set_location_assignment PIN_Y19 -to HEX3[6]
set_location_assignment PIN_AB19 -to HEX4[0]
set_location_assignment PIN_AA19 -to HEX4[1]
set_location_assignment PIN_AG21 -to HEX4[2]
set_location_assignment PIN_AH21 -to HEX4[3]
set_location_assignment PIN_AE19 -to HEX4[4]
set_location_assignment PIN_AF19 -to HEX4[5]
set_location_assignment PIN_AE18 -to HEX4[6]
set_location_assignment PIN_AD18 -to HEX5[0]
set_location_assignment PIN_AC18 -to HEX5[1]
set_location_assignment PIN_AB18 -to HEX5[2]
set_location_assignment PIN_AH19 -to HEX5[3]
set_location_assignment PIN_AG19 -to HEX5[4]
set_location_assignment PIN_AF18 -to HEX5[5]
set_location_assignment PIN_AH18 -to HEX5[6]
set_location_assignment PIN_AA17 -to HEX6[0]
set_location_assignment PIN_AB16 -to HEX6[1]
set_location_assignment PIN_AA16 -to HEX6[2]
set_location_assignment PIN_AB17 -to HEX6[3]
set_location_assignment PIN_AB15 -to HEX6[4]
set_location_assignment PIN_AA15 -to HEX6[5]
set_location_assignment PIN_AC17 -to HEX6[6]
set_location_assignment PIN_AD17 -to HEX7[0]
set_location_assignment PIN_AE17 -to HEX7[1]
set_location_assignment PIN_AG17 -to HEX7[2]
set_location_assignment PIN_AH17 -to HEX7[3]
set_location_assignment PIN_AF17 -to HEX7[4]
set_location_assignment PIN_AG18 -to HEX7[5]
set_location_assignment PIN_AA14 -to HEX7[6]
set_location_assignment PIN_L3 -to LCD_DATA[0]
set_location_assignment PIN_L1 -to LCD_DATA[1]
set_location_assignment PIN_L2 -to LCD_DATA[2]
set_location_assignment PIN_K7 -to LCD_DATA[3]
set_location_assignment PIN_K1 -to LCD_DATA[4]
set_location_assignment PIN_K2 -to LCD_DATA[5]
set_location_assignment PIN_M3 -to LCD_DATA[6]
set_location_assignment PIN_M5 -to LCD_DATA[7]
set_location_assignment PIN_L6 -to LCD_BLON
set_location_assignment PIN_M1 -to LCD_RW
set_location_assignment PIN_L4 -to LCD_EN
set_location_assignment PIN_M2 -to LCD_RS
set_location_assignment PIN_L5 -to LCD_ON
set_location_assignment PIN_G9 -to UART_TXD
set_location_assignment PIN_G12 -to UART_RXD
set_location_assignment PIN_G14 -to UART_CTS
set_location_assignment PIN_J13 -to UART_RTS
set_location_assignment PIN_G6 -to PS2_CLK
set_location_assignment PIN_H5 -to PS2_DAT
set_location_assignment PIN_G5 -to PS2_CLK2
set_location_assignment PIN_F5 -to PS2_DAT2
set_location_assignment PIN_AE13 -to SD_CLK
set_location_assignment PIN_AD14 -to SD_CMD
set_location_assignment PIN_AF14 -to SD_WP_N
set_location_assignment PIN_AE14 -to SD_DAT[0]
set_location_assignment PIN_AF13 -to SD_DAT[1]
set_location_assignment PIN_AB14 -to SD_DAT[2]
set_location_assignment PIN_AC14 -to SD_DAT[3]
set_location_assignment PIN_G13 -to VGA_HS
set_location_assignment PIN_C13 -to VGA_VS
set_location_assignment PIN_C10 -to VGA_SYNC_N
set_location_assignment PIN_A12 -to VGA_CLK
set_location_assignment PIN_F11 -to VGA_BLANK_N
set_location_assignment PIN_E12 -to VGA_R[0]
set_location_assignment PIN_E11 -to VGA_R[1]
set_location_assignment PIN_D10 -to VGA_R[2]
set_location_assignment PIN_F12 -to VGA_R[3]
set_location_assignment PIN_G10 -to VGA_R[4]
set_location_assignment PIN_J12 -to VGA_R[5]
set_location_assignment PIN_H8 -to VGA_R[6]
set_location_assignment PIN_H10 -to VGA_R[7]
set_location_assignment PIN_G8 -to VGA_G[0]
set_location_assignment PIN_G11 -to VGA_G[1]
set_location_assignment PIN_F8 -to VGA_G[2]
set_location_assignment PIN_H12 -to VGA_G[3]
set_location_assignment PIN_C8 -to VGA_G[4]
set_location_assignment PIN_B8 -to VGA_G[5]
set_location_assignment PIN_F10 -to VGA_G[6]
set_location_assignment PIN_C9 -to VGA_G[7]
set_location_assignment PIN_B10 -to VGA_B[0]
set_location_assignment PIN_A10 -to VGA_B[1]
set_location_assignment PIN_C11 -to VGA_B[2]
set_location_assignment PIN_B11 -to VGA_B[3]
set_location_assignment PIN_A11 -to VGA_B[4]
set_location_assignment PIN_C12 -to VGA_B[5]
set_location_assignment PIN_D11 -to VGA_B[6]
set_location_assignment PIN_D12 -to VGA_B[7]
set_location_assignment PIN_C2 -to AUD_ADCLRCK
set_location_assignment PIN_D2 -to AUD_ADCDAT
set_location_assignment PIN_E3 -to AUD_DACLRCK
set_location_assignment PIN_D1 -to AUD_DACDAT
set_location_assignment PIN_E1 -to AUD_XCK
set_location_assignment PIN_F2 -to AUD_BCLK
set_location_assignment PIN_D14 -to EEP_I2C_SCLK
set_location_assignment PIN_E14 -to EEP_I2C_SDAT
set_location_assignment PIN_B7 -to I2C_SCLK
set_location_assignment PIN_A8 -to I2C_SDAT
set_location_assignment PIN_A14 -to ENETCLK_25
set_location_assignment PIN_C14 -to ENET0_LINK100
set_location_assignment PIN_A17 -to ENET0_GTX_CLK
set_location_assignment PIN_C19 -to ENET0_RST_N
set_location_assignment PIN_C20 -to ENET0_MDC
set_location_assignment PIN_B21 -to ENET0_MDIO
set_location_assignment PIN_A21 -to ENET0_INT_N
set_location_assignment PIN_C18 -to ENET0_TX_DATA[0]
set_location_assignment PIN_D19 -to ENET0_TX_DATA[1]
set_location_assignment PIN_A19 -to ENET0_TX_DATA[2]
set_location_assignment PIN_B19 -to ENET0_TX_DATA[3]
set_location_assignment PIN_B17 -to ENET0_TX_CLK
set_location_assignment PIN_A18 -to ENET0_TX_EN
set_location_assignment PIN_B18 -to ENET0_TX_ER
set_location_assignment PIN_C16 -to ENET0_RX_DATA[0]
set_location_assignment PIN_D16 -to ENET0_RX_DATA[1]
set_location_assignment PIN_D17 -to ENET0_RX_DATA[2]
set_location_assignment PIN_C15 -to ENET0_RX_DATA[3]
set_location_assignment PIN_A15 -to ENET0_RX_CLK
set_location_assignment PIN_C17 -to ENET0_RX_DV
set_location_assignment PIN_D18 -to ENET0_RX_ER
set_location_assignment PIN_D15 -to ENET0_RX_CRS
set_location_assignment PIN_E15 -to ENET0_RX_COL
set_location_assignment PIN_D13 -to ENET1_LINK100
set_location_assignment PIN_C23 -to ENET1_GTX_CLK
set_location_assignment PIN_D22 -to ENET1_RST_N
set_location_assignment PIN_D23 -to ENET1_MDC
set_location_assignment PIN_D25 -to ENET1_MDIO
set_location_assignment PIN_D24 -to ENET1_INT_N
set_location_assignment PIN_C25 -to ENET1_TX_DATA[0]
set_location_assignment PIN_A26 -to ENET1_TX_DATA[1]
set_location_assignment PIN_B26 -to ENET1_TX_DATA[2]
set_location_assignment PIN_C26 -to ENET1_TX_DATA[3]
set_location_assignment PIN_C22 -to ENET1_TX_CLK
set_location_assignment PIN_B25 -to ENET1_TX_EN
set_location_assignment PIN_A25 -to ENET1_TX_ER
set_location_assignment PIN_B23 -to ENET1_RX_DATA[0]
set_location_assignment PIN_C21 -to ENET1_RX_DATA[1]
set_location_assignment PIN_A23 -to ENET1_RX_DATA[2]
set_location_assignment PIN_D21 -to ENET1_RX_DATA[3]
set_location_assignment PIN_B15 -to ENET1_RX_CLK
set_location_assignment PIN_A22 -to ENET1_RX_DV
set_location_assignment PIN_C24 -to ENET1_RX_ER
set_location_assignment PIN_D20 -to ENET1_RX_CRS
set_location_assignment PIN_B22 -to ENET1_RX_COL
set_location_assignment PIN_E5 -to TD_HS
set_location_assignment PIN_E4 -to TD_VS
set_location_assignment PIN_B14 -to TD_CLK27
set_location_assignment PIN_G7 -to TD_RESET_N
set_location_assignment PIN_E8 -to TD_DATA[0]
set_location_assignment PIN_A7 -to TD_DATA[1]
set_location_assignment PIN_D8 -to TD_DATA[2]
set_location_assignment PIN_C7 -to TD_DATA[3]
set_location_assignment PIN_D7 -to TD_DATA[4]
set_location_assignment PIN_D6 -to TD_DATA[5]
set_location_assignment PIN_E7 -to TD_DATA[6]
set_location_assignment PIN_F7 -to TD_DATA[7]
set_location_assignment PIN_J6 -to OTG_DATA[0]
set_location_assignment PIN_K4 -to OTG_DATA[1]
set_location_assignment PIN_J5 -to OTG_DATA[2]
set_location_assignment PIN_K3 -to OTG_DATA[3]
set_location_assignment PIN_J4 -to OTG_DATA[4]
set_location_assignment PIN_J3 -to OTG_DATA[5]
set_location_assignment PIN_J7 -to OTG_DATA[6]
set_location_assignment PIN_H6 -to OTG_DATA[7]
set_location_assignment PIN_H3 -to OTG_DATA[8]
set_location_assignment PIN_H4 -to OTG_DATA[9]
set_location_assignment PIN_G1 -to OTG_DATA[10]
set_location_assignment PIN_G2 -to OTG_DATA[11]
set_location_assignment PIN_G3 -to OTG_DATA[12]
set_location_assignment PIN_F1 -to OTG_DATA[13]
set_location_assignment PIN_F3 -to OTG_DATA[14]
set_location_assignment PIN_G4 -to OTG_DATA[15]
set_location_assignment PIN_H7 -to OTG_ADDR[0]
set_location_assignment PIN_C3 -to OTG_ADDR[1]
set_location_assignment PIN_J1 -to OTG_DREQ[0]
set_location_assignment PIN_A3 -to OTG_CS_N
set_location_assignment PIN_A4 -to OTG_WR_N
set_location_assignment PIN_B3 -to OTG_RD_N
set_location_assignment PIN_D5 -to OTG_INT
set_location_assignment PIN_C5 -to OTG_RST_N
set_location_assignment PIN_Y15 -to IRDA_RXD
set_location_assignment PIN_U7 -to DRAM_BA[0]
set_location_assignment PIN_R4 -to DRAM_BA[1]
set_location_assignment PIN_U2 -to DRAM_DQM[0]
set_location_assignment PIN_W4 -to DRAM_DQM[1]
set_location_assignment PIN_K8 -to DRAM_DQM[2]
set_location_assignment PIN_N8 -to DRAM_DQM[3]
set_location_assignment PIN_U6 -to DRAM_RAS_N
set_location_assignment PIN_V7 -to DRAM_CAS_N
set_location_assignment PIN_AA6 -to DRAM_CKE
set_location_assignment PIN_AE5 -to DRAM_CLK
set_location_assignment PIN_V6 -to DRAM_WE_N
set_location_assignment PIN_T4 -to DRAM_CS_N
set_location_assignment PIN_W3 -to DRAM_DQ[0]
set_location_assignment PIN_W2 -to DRAM_DQ[1]
set_location_assignment PIN_V4 -to DRAM_DQ[2]
set_location_assignment PIN_W1 -to DRAM_DQ[3]
set_location_assignment PIN_V3 -to DRAM_DQ[4]
set_location_assignment PIN_V2 -to DRAM_DQ[5]
set_location_assignment PIN_V1 -to DRAM_DQ[6]
set_location_assignment PIN_U3 -to DRAM_DQ[7]
set_location_assignment PIN_Y3 -to DRAM_DQ[8]
set_location_assignment PIN_Y4 -to DRAM_DQ[9]
set_location_assignment PIN_AB1 -to DRAM_DQ[10]
set_location_assignment PIN_AA3 -to DRAM_DQ[11]
set_location_assignment PIN_AB2 -to DRAM_DQ[12]
set_location_assignment PIN_AC1 -to DRAM_DQ[13]
set_location_assignment PIN_AB3 -to DRAM_DQ[14]
set_location_assignment PIN_AC2 -to DRAM_DQ[15]
set_location_assignment PIN_M8 -to DRAM_DQ[16]
set_location_assignment PIN_L8 -to DRAM_DQ[17]
set_location_assignment PIN_P2 -to DRAM_DQ[18]
set_location_assignment PIN_N3 -to DRAM_DQ[19]
set_location_assignment PIN_N4 -to DRAM_DQ[20]
set_location_assignment PIN_M4 -to DRAM_DQ[21]
set_location_assignment PIN_M7 -to DRAM_DQ[22]
set_location_assignment PIN_L7 -to DRAM_DQ[23]
set_location_assignment PIN_U5 -to DRAM_DQ[24]
set_location_assignment PIN_R7 -to DRAM_DQ[25]
set_location_assignment PIN_R1 -to DRAM_DQ[26]
set_location_assignment PIN_R2 -to DRAM_DQ[27]
set_location_assignment PIN_R3 -to DRAM_DQ[28]
set_location_assignment PIN_T3 -to DRAM_DQ[29]
set_location_assignment PIN_U4 -to DRAM_DQ[30]
set_location_assignment PIN_U1 -to DRAM_DQ[31]
set_location_assignment PIN_R6 -to DRAM_ADDR[0]
set_location_assignment PIN_V8 -to DRAM_ADDR[1]
set_location_assignment PIN_U8 -to DRAM_ADDR[2]
set_location_assignment PIN_P1 -to DRAM_ADDR[3]
set_location_assignment PIN_V5 -to DRAM_ADDR[4]
set_location_assignment PIN_W8 -to DRAM_ADDR[5]
set_location_assignment PIN_W7 -to DRAM_ADDR[6]
set_location_assignment PIN_AA7 -to DRAM_ADDR[7]
set_location_assignment PIN_Y5 -to DRAM_ADDR[8]
set_location_assignment PIN_Y6 -to DRAM_ADDR[9]
set_location_assignment PIN_R5 -to DRAM_ADDR[10]
set_location_assignment PIN_AA5 -to DRAM_ADDR[11]
set_location_assignment PIN_Y7 -to DRAM_ADDR[12]
set_location_assignment PIN_AB7 -to SRAM_ADDR[0]
set_location_assignment PIN_AD7 -to SRAM_ADDR[1]
set_location_assignment PIN_AE7 -to SRAM_ADDR[2]
set_location_assignment PIN_AC7 -to SRAM_ADDR[3]
set_location_assignment PIN_AB6 -to SRAM_ADDR[4]
set_location_assignment PIN_AE6 -to SRAM_ADDR[5]
set_location_assignment PIN_AB5 -to SRAM_ADDR[6]
set_location_assignment PIN_AC5 -to SRAM_ADDR[7]
set_location_assignment PIN_AF5 -to SRAM_ADDR[8]
set_location_assignment PIN_T7 -to SRAM_ADDR[9]
set_location_assignment PIN_AF2 -to SRAM_ADDR[10]
set_location_assignment PIN_AD3 -to SRAM_ADDR[11]
set_location_assignment PIN_AB4 -to SRAM_ADDR[12]
set_location_assignment PIN_AC3 -to SRAM_ADDR[13]
set_location_assignment PIN_AA4 -to SRAM_ADDR[14]
set_location_assignment PIN_AB11 -to SRAM_ADDR[15]
set_location_assignment PIN_AC11 -to SRAM_ADDR[16]
set_location_assignment PIN_AB9 -to SRAM_ADDR[17]
set_location_assignment PIN_AB8 -to SRAM_ADDR[18]
set_location_assignment PIN_T8 -to SRAM_ADDR[19]
set_location_assignment PIN_AH3 -to SRAM_DQ[0]
set_location_assignment PIN_AF4 -to SRAM_DQ[1]
set_location_assignment PIN_AG4 -to SRAM_DQ[2]
set_location_assignment PIN_AH4 -to SRAM_DQ[3]
set_location_assignment PIN_AF6 -to SRAM_DQ[4]
set_location_assignment PIN_AG6 -to SRAM_DQ[5]
set_location_assignment PIN_AH6 -to SRAM_DQ[6]
set_location_assignment PIN_AF7 -to SRAM_DQ[7]
set_location_assignment PIN_AD1 -to SRAM_DQ[8]
set_location_assignment PIN_AD2 -to SRAM_DQ[9]
set_location_assignment PIN_AE2 -to SRAM_DQ[10]
set_location_assignment PIN_AE1 -to SRAM_DQ[11]
set_location_assignment PIN_AE3 -to SRAM_DQ[12]
set_location_assignment PIN_AE4 -to SRAM_DQ[13]
set_location_assignment PIN_AF3 -to SRAM_DQ[14]
set_location_assignment PIN_AG3 -to SRAM_DQ[15]
set_location_assignment PIN_AC4 -to SRAM_UB_N
set_location_assignment PIN_AD4 -to SRAM_LB_N
set_location_assignment PIN_AF8 -to SRAM_CE_N
set_location_assignment PIN_AD5 -to SRAM_OE_N
set_location_assignment PIN_AE8 -to SRAM_WE_N
set_location_assignment PIN_AG12 -to FL_ADDR[0]
set_location_assignment PIN_AH7 -to FL_ADDR[1]
set_location_assignment PIN_Y13 -to FL_ADDR[2]
set_location_assignment PIN_Y14 -to FL_ADDR[3]
set_location_assignment PIN_Y12 -to FL_ADDR[4]
set_location_assignment PIN_AA13 -to FL_ADDR[5]
set_location_assignment PIN_AA12 -to FL_ADDR[6]
set_location_assignment PIN_AB13 -to FL_ADDR[7]
set_location_assignment PIN_AB12 -to FL_ADDR[8]
set_location_assignment PIN_AB10 -to FL_ADDR[9]
set_location_assignment PIN_AE9 -to FL_ADDR[10]
set_location_assignment PIN_AF9 -to FL_ADDR[11]
set_location_assignment PIN_AA10 -to FL_ADDR[12]
set_location_assignment PIN_AD8 -to FL_ADDR[13]
set_location_assignment PIN_AC8 -to FL_ADDR[14]
set_location_assignment PIN_Y10 -to FL_ADDR[15]
set_location_assignment PIN_AA8 -to FL_ADDR[16]
set_location_assignment PIN_AH12 -to FL_ADDR[17]
set_location_assignment PIN_AC12 -to FL_ADDR[18]
set_location_assignment PIN_AD12 -to FL_ADDR[19]
set_location_assignment PIN_AE10 -to FL_ADDR[20]
set_location_assignment PIN_AD10 -to FL_ADDR[21]
set_location_assignment PIN_AD11 -to FL_ADDR[22]
set_location_assignment PIN_AH8 -to FL_DQ[0]
set_location_assignment PIN_AF10 -to FL_DQ[1]
set_location_assignment PIN_AG10 -to FL_DQ[2]
set_location_assignment PIN_AH10 -to FL_DQ[3]
set_location_assignment PIN_AF11 -to FL_DQ[4]
set_location_assignment PIN_AG11 -to FL_DQ[5]
set_location_assignment PIN_AH11 -to FL_DQ[6]
set_location_assignment PIN_AF12 -to FL_DQ[7]
set_location_assignment PIN_AG7 -to FL_CE_N
set_location_assignment PIN_AG8 -to FL_OE_N
set_location_assignment PIN_AE11 -to FL_RST_N
set_location_assignment PIN_Y1 -to FL_RY
set_location_assignment PIN_AC10 -to FL_WE_N
set_location_assignment PIN_AE12 -to FL_WP_N
set_location_assignment PIN_AB22 -to GPIO[0]
set_location_assignment PIN_AC15 -to GPIO[1]
set_location_assignment PIN_AB21 -to GPIO[2]
set_location_assignment PIN_Y17 -to GPIO[3]
set_location_assignment PIN_AC21 -to GPIO[4]
set_location_assignment PIN_Y16 -to GPIO[5]
set_location_assignment PIN_AD21 -to GPIO[6]
set_location_assignment PIN_AE16 -to GPIO[7]
set_location_assignment PIN_AD15 -to GPIO[8]
set_location_assignment PIN_AE15 -to GPIO[9]
set_location_assignment PIN_AC19 -to GPIO[10]
set_location_assignment PIN_AF16 -to GPIO[11]
set_location_assignment PIN_AD19 -to GPIO[12]
set_location_assignment PIN_AF15 -to GPIO[13]
set_location_assignment PIN_AF24 -to GPIO[14]
set_location_assignment PIN_AE21 -to GPIO[15]
set_location_assignment PIN_AF25 -to GPIO[16]
set_location_assignment PIN_AC22 -to GPIO[17]
set_location_assignment PIN_AE22 -to GPIO[18]
set_location_assignment PIN_AF21 -to GPIO[19]
set_location_assignment PIN_AF22 -to GPIO[20]
set_location_assignment PIN_AD22 -to GPIO[21]
set_location_assignment PIN_AG25 -to GPIO[22]
set_location_assignment PIN_AD25 -to GPIO[23]
set_location_assignment PIN_AH25 -to GPIO[24]
set_location_assignment PIN_AE25 -to GPIO[25]
set_location_assignment PIN_AG22 -to GPIO[26]
set_location_assignment PIN_AE24 -to GPIO[27]
set_location_assignment PIN_AH22 -to GPIO[28]
set_location_assignment PIN_AF26 -to GPIO[29]
set_location_assignment PIN_AE20 -to GPIO[30]
set_location_assignment PIN_AG23 -to GPIO[31]
set_location_assignment PIN_AF20 -to GPIO[32]
set_location_assignment PIN_AH26 -to GPIO[33]
set_location_assignment PIN_AH23 -to GPIO[34]
set_location_assignment PIN_AG26 -to GPIO[35]
set_location_assignment PIN_AH15 -to HSMC_CLKIN0
set_location_assignment PIN_AD28 -to HSMC_CLKOUT0
set_location_assignment PIN_AE26 -to HSMC_D[0]
set_location_assignment PIN_AE28 -to HSMC_D[1]
set_location_assignment PIN_AE27 -to HSMC_D[2]
set_location_assignment PIN_AF27 -to HSMC_D[3]
set_location_assignment PIN_J27 -to HSMC_CLKIN_P1
set_location_assignment PIN_J28 -to HSMC_CLKIN_N1
set_location_assignment PIN_G23 -to HSMC_CLKOUT_P1
set_location_assignment PIN_G24 -to HSMC_CLKOUT_N1
set_location_assignment PIN_Y27 -to HSMC_CLKIN_P2
set_location_assignment PIN_Y28 -to HSMC_CLKIN_N2
set_location_assignment PIN_V23 -to HSMC_CLKOUT_P2
set_location_assignment PIN_V24 -to HSMC_CLKOUT_N2
set_location_assignment PIN_D27 -to HSMC_TX_D_P[0]
set_location_assignment PIN_D28 -to HSMC_TX_D_N[0]
set_location_assignment PIN_E27 -to HSMC_TX_D_P[1]
set_location_assignment PIN_E28 -to HSMC_TX_D_N[1]
set_location_assignment PIN_F27 -to HSMC_TX_D_P[2]
set_location_assignment PIN_F28 -to HSMC_TX_D_N[2]
set_location_assignment PIN_G27 -to HSMC_TX_D_P[3]
set_location_assignment PIN_G28 -to HSMC_TX_D_N[3]
set_location_assignment PIN_K27 -to HSMC_TX_D_P[4]
set_location_assignment PIN_K28 -to HSMC_TX_D_N[4]
set_location_assignment PIN_M27 -to HSMC_TX_D_P[5]
set_location_assignment PIN_M28 -to HSMC_TX_D_N[5]
set_location_assignment PIN_K21 -to HSMC_TX_D_P[6]
set_location_assignment PIN_K22 -to HSMC_TX_D_N[6]
set_location_assignment PIN_H23 -to HSMC_TX_D_P[7]
set_location_assignment PIN_H24 -to HSMC_TX_D_N[7]
set_location_assignment PIN_J23 -to HSMC_TX_D_P[8]
set_location_assignment PIN_J24 -to HSMC_TX_D_N[8]
set_location_assignment PIN_P27 -to HSMC_TX_D_P[9]
set_location_assignment PIN_P28 -to HSMC_TX_D_N[9]
set_location_assignment PIN_J25 -to HSMC_TX_D_P[10]
set_location_assignment PIN_J26 -to HSMC_TX_D_N[10]
set_location_assignment PIN_L27 -to HSMC_TX_D_P[11]
set_location_assignment PIN_L28 -to HSMC_TX_D_N[11]
set_location_assignment PIN_V25 -to HSMC_TX_D_P[12]
set_location_assignment PIN_V26 -to HSMC_TX_D_N[12]
set_location_assignment PIN_R27 -to HSMC_TX_D_P[13]
set_location_assignment PIN_R28 -to HSMC_TX_D_N[13]
set_location_assignment PIN_U27 -to HSMC_TX_D_P[14]
set_location_assignment PIN_U28 -to HSMC_TX_D_N[14]
set_location_assignment PIN_V27 -to HSMC_TX_D_P[15]
set_location_assignment PIN_V28 -to HSMC_TX_D_N[15]
set_location_assignment PIN_U22 -to HSMC_TX_D_P[16]
set_location_assignment PIN_V22 -to HSMC_TX_D_N[16]
set_location_assignment PIN_F24 -to HSMC_RX_D_P[0]
set_location_assignment PIN_F25 -to HSMC_RX_D_N[0]
set_location_assignment PIN_D26 -to HSMC_RX_D_P[1]
set_location_assignment PIN_C27 -to HSMC_RX_D_N[1]
set_location_assignment PIN_F26 -to HSMC_RX_D_P[2]
set_location_assignment PIN_E26 -to HSMC_RX_D_N[2]
set_location_assignment PIN_G25 -to HSMC_RX_D_P[3]
set_location_assignment PIN_G26 -to HSMC_RX_D_N[3]
set_location_assignment PIN_H25 -to HSMC_RX_D_P[4]
set_location_assignment PIN_H26 -to HSMC_RX_D_N[4]
set_location_assignment PIN_K25 -to HSMC_RX_D_P[5]
set_location_assignment PIN_K26 -to HSMC_RX_D_N[5]
set_location_assignment PIN_L23 -to HSMC_RX_D_P[6]
set_location_assignment PIN_L24 -to HSMC_RX_D_N[6]
set_location_assignment PIN_M25 -to HSMC_RX_D_P[7]
set_location_assignment PIN_M26 -to HSMC_RX_D_N[7]
set_location_assignment PIN_R25 -to HSMC_RX_D_P[8]
set_location_assignment PIN_R26 -to HSMC_RX_D_N[8]
set_location_assignment PIN_T25 -to HSMC_RX_D_P[9]
set_location_assignment PIN_T26 -to HSMC_RX_D_N[9]
set_location_assignment PIN_U25 -to HSMC_RX_D_P[10]
set_location_assignment PIN_U26 -to HSMC_RX_D_N[10]
set_location_assignment PIN_L21 -to HSMC_RX_D_P[11]
set_location_assignment PIN_L22 -to HSMC_RX_D_N[11]
set_location_assignment PIN_N25 -to HSMC_RX_D_P[12]
set_location_assignment PIN_N26 -to HSMC_RX_D_N[12]
set_location_assignment PIN_P25 -to HSMC_RX_D_P[13]
set_location_assignment PIN_P26 -to HSMC_RX_D_N[13]
set_location_assignment PIN_P21 -to HSMC_RX_D_P[14]
set_location_assignment PIN_R21 -to HSMC_RX_D_N[14]
set_location_assignment PIN_R22 -to HSMC_RX_D_P[15]
set_location_assignment PIN_R23 -to HSMC_RX_D_N[15]
set_location_assignment PIN_T21 -to HSMC_RX_D_P[16]
set_location_assignment PIN_T22 -to HSMC_RX_D_N[16]
set_location_assignment PIN_J10 -to EX_IO[0]
set_location_assignment PIN_J14 -to EX_IO[1]
set_location_assignment PIN_H13 -to EX_IO[2]
set_location_assignment PIN_H14 -to EX_IO[3]
set_location_assignment PIN_F14 -to EX_IO[4]
set_location_assignment PIN_E10 -to EX_IO[5]
set_location_assignment PIN_D9 -to EX_IO[6]
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

62
1ano/2semestre/lsd/aula01/part1/GateDemo.qsf.bak Normal file
View File

@ -0,0 +1,62 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2020 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
# Date created = 14:43:19 February 18, 2023
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# GateDemo_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE115F29C7
set_global_assignment -name TOP_LEVEL_ENTITY GateDemo
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:43:19 FEBRUARY 18, 2023"
set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
set_global_assignment -name BDF_FILE GateDemo.bdf
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top

BIN
1ano/2semestre/lsd/aula01/part1/GateDemo.qws Normal file
View File

Binary file not shown.

184
1ano/2semestre/lsd/aula01/part1/GateDemo.vwf Normal file
View File

@ -0,0 +1,184 @@
/*<simulation_settings>
<ftestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off GateDemo -c GateDemo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/GateDemo.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/simulation/qsim/GateDemo.vwf.vht"</ftestbench_cmd>
<ttestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off GateDemo -c GateDemo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/GateDemo.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/simulation/qsim/GateDemo.vwf.vht"</ttestbench_cmd>
<fnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/simulation/qsim/" GateDemo -c GateDemo</fnetlist_cmd>
<tnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/simulation/qsim/" GateDemo -c GateDemo</tnetlist_cmd>
<modelsim_script>onerror {exit -code 1}
vlib work
vcom -work work GateDemo.vho
vcom -work work GateDemo.vwf.vht
vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.GateDemo_vhd_vec_tst
vcd file -direction GateDemo.msim.vcd
vcd add -internal GateDemo_vhd_vec_tst/*
vcd add -internal GateDemo_vhd_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script>
<modelsim_script_timing>onerror {exit -code 1}
vlib work
vcom -work work GateDemo.vho
vcom -work work GateDemo.vwf.vht
vsim -novopt -c -t 1ps -sdfmax GateDemo_vhd_vec_tst/i1=GateDemo_vhd.sdo -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.GateDemo_vhd_vec_tst
vcd file -direction GateDemo.msim.vcd
vcd add -internal GateDemo_vhd_vec_tst/*
vcd add -internal GateDemo_vhd_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script_timing>
<hdl_lang>vhdl</hdl_lang>
</simulation_settings>*/
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
HEADER
{
VERSION = 1;
TIME_UNIT = ns;
DATA_OFFSET = 0.0;
DATA_DURATION = 1000.0;
SIMULATION_TIME = 0.0;
GRID_PHASE = 0.0;
GRID_PERIOD = 10.0;
GRID_DUTY_CYCLE = 50;
}
SIGNAL("LEDR[0]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("SW[0]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("SW[1]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
TRANSITION_LIST("LEDR[0]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("SW[0]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 80.0;
LEVEL 1 FOR 100.0;
LEVEL 0 FOR 240.0;
LEVEL 1 FOR 200.0;
LEVEL 0 FOR 40.0;
LEVEL 1 FOR 60.0;
LEVEL 0 FOR 80.0;
LEVEL 1 FOR 100.0;
LEVEL 0 FOR 100.0;
}
}
TRANSITION_LIST("SW[1]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 240.0;
LEVEL 1 FOR 100.0;
LEVEL 0 FOR 140.0;
LEVEL 1 FOR 80.0;
LEVEL 0 FOR 100.0;
LEVEL 1 FOR 60.0;
LEVEL 0 FOR 40.0;
LEVEL 1 FOR 200.0;
LEVEL 0 FOR 40.0;
}
}
DISPLAY_LINE
{
CHANNEL = "SW[0]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 0;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "SW[1]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 1;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "LEDR[0]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 2;
TREE_LEVEL = 0;
}
TIME_BAR
{
TIME = 0;
MASTER = TRUE;
}
;

BIN
1ano/2semestre/lsd/aula01/part1/db/GateDemo.(0).cnf.cdb Normal file
View File

Binary file not shown.

BIN
1ano/2semestre/lsd/aula01/part1/db/GateDemo.(0).cnf.hdb Normal file
View File

Binary file not shown.

7
1ano/2semestre/lsd/aula01/part1/db/GateDemo.asm.qmsg Normal file
View File

@ -0,0 +1,7 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1676732819706 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1676732819706 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Feb 18 15:06:59 2023 " "Processing started: Sat Feb 18 15:06:59 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1676732819706 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1676732819706 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off GateDemo -c GateDemo " "Command: quartus_asm --read_settings_files=off --write_settings_files=off GateDemo -c GateDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1676732819706 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1676732819909 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1676732822053 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1676732822155 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "367 " "Peak virtual memory: 367 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1676732822435 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Feb 18 15:07:02 2023 " "Processing ended: Sat Feb 18 15:07:02 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1676732822435 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1676732822435 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1676732822435 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1676732822435 ""}

BIN
1ano/2semestre/lsd/aula01/part1/db/GateDemo.asm.rdb Normal file
View File

Binary file not shown.

BIN
1ano/2semestre/lsd/aula01/part1/db/GateDemo.asm_labs.ddb Normal file
View File

Binary file not shown.

5
1ano/2semestre/lsd/aula01/part1/db/GateDemo.cbx.xml Normal file
View File

@ -0,0 +1,5 @@
<?xml version="1.0" ?>
<LOG_ROOT>
<PROJECT NAME="GateDemo">
</PROJECT>
</LOG_ROOT>

BIN
1ano/2semestre/lsd/aula01/part1/db/GateDemo.cmp.bpm Normal file
View File

Binary file not shown.

BIN
1ano/2semestre/lsd/aula01/part1/db/GateDemo.cmp.cdb Normal file
View File

Binary file not shown.

BIN
1ano/2semestre/lsd/aula01/part1/db/GateDemo.cmp.hdb Normal file
View File

Binary file not shown.

BIN
1ano/2semestre/lsd/aula01/part1/db/GateDemo.cmp.idb Normal file
View File

Binary file not shown.

45
1ano/2semestre/lsd/aula01/part1/db/GateDemo.cmp.logdb Normal file
View File

@ -0,0 +1,45 @@
v1
IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,,
IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000001;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000047;IO_000046;IO_000045;IO_000027;IO_000026;IO_000024;IO_000023;IO_000022;IO_000021;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000033;IO_000034;IO_000042,
IO_RULES_MATRIX,Total Pass,0;3;3;0;0;3;3;0;0;0;0;0;0;1;0;0;0;2;1;0;2;0;0;1;0;3;3;3;0;0,
IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
IO_RULES_MATRIX,Total Inapplicable,3;0;0;3;3;0;0;3;3;3;3;3;3;2;3;3;3;1;2;3;1;3;3;2;3;0;0;0;3;3,
IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
IO_RULES_MATRIX,LEDR[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,SW[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,SW[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_SUMMARY,Total I/O Rules,30,
IO_RULES_SUMMARY,Number of I/O Rules Passed,12,
IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,18,

BIN
1ano/2semestre/lsd/aula01/part1/db/GateDemo.cmp.rdb Normal file
View File

Binary file not shown.

BIN
1ano/2semestre/lsd/aula01/part1/db/GateDemo.cmp_merge.kpt Normal file
View File

Binary file not shown.

BIN
1ano/2semestre/lsd/aula01/part1/db/GateDemo.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd Normal file
View File

Binary file not shown.

BIN
1ano/2semestre/lsd/aula01/part1/db/GateDemo.cycloneive_io_sim_cache.45um_ii_1200mv_0c_slow.hsd Normal file
View File

Binary file not shown.

BIN
1ano/2semestre/lsd/aula01/part1/db/GateDemo.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd Normal file
View File

Binary file not shown.

3
1ano/2semestre/lsd/aula01/part1/db/GateDemo.db_info Normal file
View File

@ -0,0 +1,3 @@
Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Version_Index = 520278016
Creation_Time = Sun Feb 19 21:55:23 2023

6
1ano/2semestre/lsd/aula01/part1/db/GateDemo.eda.qmsg Normal file
View File

@ -0,0 +1,6 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1676732824988 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1676732824988 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Feb 18 15:07:04 2023 " "Processing started: Sat Feb 18 15:07:04 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1676732824988 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1676732824988 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off GateDemo -c GateDemo " "Command: quartus_eda --read_settings_files=off --write_settings_files=off GateDemo -c GateDemo" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1676732824988 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1676732825224 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "GateDemo.vho /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/simulation/modelsim/ simulation " "Generated file GateDemo.vho in folder \"/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1676732825259 ""}
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "612 " "Peak virtual memory: 612 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1676732825276 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Feb 18 15:07:05 2023 " "Processing ended: Sat Feb 18 15:07:05 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1676732825276 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1676732825276 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1676732825276 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1676732825276 ""}

48
1ano/2semestre/lsd/aula01/part1/db/GateDemo.fit.qmsg Normal file
View File

File diff suppressed because one or more lines are too long

6
1ano/2semestre/lsd/aula01/part1/db/GateDemo.hier_info Normal file
View File

@ -0,0 +1,6 @@
|GateDemo
LEDR[0] <= inst.DB_MAX_OUTPUT_PORT_TYPE
SW[0] => inst.IN0
SW[1] => inst.IN1

BIN
1ano/2semestre/lsd/aula01/part1/db/GateDemo.hif Normal file
View File

Binary file not shown.

18
1ano/2semestre/lsd/aula01/part1/db/GateDemo.lpc.html Normal file
View File

@ -0,0 +1,18 @@
<TABLE>
<TR bgcolor="#C0C0C0">
<TH>Hierarchy</TH>
<TH>Input</TH>
<TH>Constant Input</TH>
<TH>Unused Input</TH>
<TH>Floating Input</TH>
<TH>Output</TH>
<TH>Constant Output</TH>
<TH>Unused Output</TH>
<TH>Floating Output</TH>
<TH>Bidir</TH>
<TH>Constant Bidir</TH>
<TH>Unused Bidir</TH>
<TH>Input only Bidir</TH>
<TH>Output only Bidir</TH>
</TR>
</TABLE>

BIN
1ano/2semestre/lsd/aula01/part1/db/GateDemo.lpc.rdb Normal file
View File

Binary file not shown.

5
1ano/2semestre/lsd/aula01/part1/db/GateDemo.lpc.txt Normal file
View File

@ -0,0 +1,5 @@
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Legal Partition Candidates ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

BIN
1ano/2semestre/lsd/aula01/part1/db/GateDemo.map.ammdb Normal file
View File

Binary file not shown.

BIN
1ano/2semestre/lsd/aula01/part1/db/GateDemo.map.bpm Normal file
View File

Binary file not shown.

BIN
1ano/2semestre/lsd/aula01/part1/db/GateDemo.map.cdb Normal file
View File

Binary file not shown.

BIN
1ano/2semestre/lsd/aula01/part1/db/GateDemo.map.hdb Normal file
View File

Binary file not shown.

BIN
1ano/2semestre/lsd/aula01/part1/db/GateDemo.map.kpt Normal file
View File

Binary file not shown.

1
1ano/2semestre/lsd/aula01/part1/db/GateDemo.map.logdb Normal file
View File

@ -0,0 +1 @@
v1

11
1ano/2semestre/lsd/aula01/part1/db/GateDemo.map.qmsg Normal file
View File

@ -0,0 +1,11 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1676732803653 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1676732803653 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Feb 18 15:06:43 2023 " "Processing started: Sat Feb 18 15:06:43 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1676732803653 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1676732803653 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GateDemo -c GateDemo " "Command: quartus_map --read_settings_files=on --write_settings_files=off GateDemo -c GateDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1676732803653 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1676732803796 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1676732803796 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "GateDemo.bdf 1 1 " "Found 1 design units, including 1 entities, in source file GateDemo.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 GateDemo " "Found entity 1: GateDemo" { } { { "GateDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/GateDemo.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676732809130 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1676732809130 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "GateDemo " "Elaborating entity \"GateDemo\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1676732809161 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1676732809524 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1676732809918 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676732809918 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "4 " "Implemented 4 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Implemented 2 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1676732809941 ""} { "Info" "ICUT_CUT_TM_OPINS" "1 " "Implemented 1 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1676732809941 ""} { "Info" "ICUT_CUT_TM_LCELLS" "1 " "Implemented 1 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1676732809941 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1676732809941 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "403 " "Peak virtual memory: 403 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1676732809945 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Feb 18 15:06:49 2023 " "Processing ended: Sat Feb 18 15:06:49 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1676732809945 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1676732809945 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:16 " "Total CPU time (on all processors): 00:00:16" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1676732809945 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1676732809945 ""}

BIN
1ano/2semestre/lsd/aula01/part1/db/GateDemo.map.rdb Normal file
View File

Binary file not shown.

BIN
1ano/2semestre/lsd/aula01/part1/db/GateDemo.map_bb.cdb Normal file
View File

Binary file not shown.

BIN
1ano/2semestre/lsd/aula01/part1/db/GateDemo.map_bb.hdb Normal file
View File

Binary file not shown.

1
1ano/2semestre/lsd/aula01/part1/db/GateDemo.map_bb.logdb Normal file
View File

@ -0,0 +1 @@
v1

BIN
1ano/2semestre/lsd/aula01/part1/db/GateDemo.pre_map.hdb Normal file
View File

Binary file not shown.

BIN
1ano/2semestre/lsd/aula01/part1/db/GateDemo.root_partition.map.reg_db.cdb Normal file
View File

Binary file not shown.

BIN
1ano/2semestre/lsd/aula01/part1/db/GateDemo.routing.rdb Normal file
View File

Binary file not shown.

BIN
1ano/2semestre/lsd/aula01/part1/db/GateDemo.rtlv.hdb Normal file
View File

Binary file not shown.

BIN
1ano/2semestre/lsd/aula01/part1/db/GateDemo.rtlv_sg.cdb Normal file
View File

Binary file not shown.

BIN
1ano/2semestre/lsd/aula01/part1/db/GateDemo.rtlv_sg_swap.cdb Normal file
View File

Binary file not shown.

BIN
1ano/2semestre/lsd/aula01/part1/db/GateDemo.sld_design_entry.sci Normal file
View File

Binary file not shown.

BIN
1ano/2semestre/lsd/aula01/part1/db/GateDemo.sld_design_entry_dsc.sci Normal file
View File

Binary file not shown.

1
1ano/2semestre/lsd/aula01/part1/db/GateDemo.smart_action.txt Normal file
View File

@ -0,0 +1 @@
DONE

49
1ano/2semestre/lsd/aula01/part1/db/GateDemo.sta.qmsg Normal file
View File

@ -0,0 +1,49 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1676732823089 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1676732823089 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Feb 18 15:07:02 2023 " "Processing started: Sat Feb 18 15:07:02 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1676732823089 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1676732823089 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta GateDemo -c GateDemo " "Command: quartus_sta GateDemo -c GateDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1676732823089 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1676732823118 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1676732823202 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1676732823202 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1676732823266 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1676732823266 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "GateDemo.sdc " "Synopsys Design Constraints File file not found: 'GateDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1676732823673 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1676732823673 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1676732823673 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1676732823673 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1676732823674 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1676732823674 ""}
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1676732823674 ""}
{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1676732823678 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1676732823678 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676732823679 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676732823681 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676732823682 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676732823682 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676732823682 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676732823683 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1676732823685 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1676732823703 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1676732823969 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1676732823984 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1676732823984 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1676732823984 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1676732823984 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676732823985 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676732823986 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676732823986 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676732823986 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676732823987 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676732823987 ""}
{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1676732823988 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1676732824040 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1676732824040 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1676732824041 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1676732824041 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676732824041 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676732824042 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676732824042 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676732824043 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1676732824043 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1676732824313 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1676732824313 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "537 " "Peak virtual memory: 537 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1676732824324 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Feb 18 15:07:04 2023 " "Processing ended: Sat Feb 18 15:07:04 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1676732824324 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1676732824324 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1676732824324 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1676732824324 ""}

BIN
1ano/2semestre/lsd/aula01/part1/db/GateDemo.sta.rdb Normal file
View File

Binary file not shown.

BIN
1ano/2semestre/lsd/aula01/part1/db/GateDemo.sta_cmp.7_slow_1200mv_85c.tdb Normal file
View File

Binary file not shown.

BIN
1ano/2semestre/lsd/aula01/part1/db/GateDemo.tis_db_list.ddb Normal file
View File

Binary file not shown.

BIN
1ano/2semestre/lsd/aula01/part1/db/GateDemo.tiscmp.fast_1200mv_0c.ddb Normal file
View File

Binary file not shown.

BIN
1ano/2semestre/lsd/aula01/part1/db/GateDemo.tiscmp.slow_1200mv_0c.ddb Normal file
View File

Binary file not shown.

BIN
1ano/2semestre/lsd/aula01/part1/db/GateDemo.tiscmp.slow_1200mv_85c.ddb Normal file
View File

Binary file not shown.

4
1ano/2semestre/lsd/aula01/part1/db/GateDemo.tmw_info Normal file
View File

@ -0,0 +1,4 @@
start_full_compilation:s
start_assembler:s-start_full_compilation
start_timing_analyzer:s-start_full_compilation
start_eda_netlist_writer:s-start_full_compilation

BIN
1ano/2semestre/lsd/aula01/part1/db/GateDemo.vpr.ammdb Normal file
View File

Binary file not shown.

21
1ano/2semestre/lsd/aula01/part1/db/GateDemo_partition_pins.json Normal file
View File

@ -0,0 +1,21 @@
{
"partitions" : [
{
"name" : "Top",
"pins" : [
{
"name" : "LEDR[0]",
"strict" : false
},
{
"name" : "SW[1]",
"strict" : false
},
{
"name" : "SW[0]",
"strict" : false
}
]
}
]
}

11
1ano/2semestre/lsd/aula01/part1/db/prev_cmp_GateDemo.qmsg Normal file
View File

@ -0,0 +1,11 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1676731602478 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1676731602478 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat Feb 18 14:46:42 2023 " "Processing started: Sat Feb 18 14:46:42 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1676731602478 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1676731602478 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off GateDemo -c GateDemo " "Command: quartus_map --read_settings_files=on --write_settings_files=off GateDemo -c GateDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1676731602479 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1676731602588 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1676731602588 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "GateDemo.bdf 1 1 " "Found 1 design units, including 1 entities, in source file GateDemo.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 GateDemo " "Found entity 1: GateDemo" { } { { "GateDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/GateDemo.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1676731607954 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1676731607954 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "GateDemo " "Elaborating entity \"GateDemo\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1676731608001 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1676731608444 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1676731608817 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1676731608817 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "4 " "Implemented 4 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Implemented 2 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1676731608940 ""} { "Info" "ICUT_CUT_TM_OPINS" "1 " "Implemented 1 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1676731608940 ""} { "Info" "ICUT_CUT_TM_LCELLS" "1 " "Implemented 1 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1676731608940 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1676731608940 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "403 " "Peak virtual memory: 403 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1676731608944 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat Feb 18 14:46:48 2023 " "Processing ended: Sat Feb 18 14:46:48 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1676731608944 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1676731608944 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:15 " "Total CPU time (on all processors): 00:00:15" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1676731608944 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1676731608944 ""}

11
1ano/2semestre/lsd/aula01/part1/incremental_db/README Normal file
View File

@ -0,0 +1,11 @@
This folder contains data for incremental compilation.
The compiled_partitions sub-folder contains previous compilation results for each partition.
As long as this folder is preserved, incremental compilation results from earlier compiles
can be re-used. To perform a clean compilation from source files for all partitions, both
the db and incremental_db folder should be removed.
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
As long as this folder is preserved, imported partitions will be automatically re-imported
when the db or incremental_db/compiled_partitions folders are removed.

3
1ano/2semestre/lsd/aula01/part1/incremental_db/compiled_partitions/GateDemo.db_info Normal file
View File

@ -0,0 +1,3 @@
Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Version_Index = 520278016
Creation_Time = Sat Feb 18 14:46:48 2023

BIN
1ano/2semestre/lsd/aula01/part1/incremental_db/compiled_partitions/GateDemo.root_partition.cmp.ammdb Normal file
View File

Binary file not shown.

BIN
1ano/2semestre/lsd/aula01/part1/incremental_db/compiled_partitions/GateDemo.root_partition.cmp.cdb Normal file
View File

Binary file not shown.

BIN
1ano/2semestre/lsd/aula01/part1/incremental_db/compiled_partitions/GateDemo.root_partition.cmp.dfp Normal file
View File

Binary file not shown.

BIN
1ano/2semestre/lsd/aula01/part1/incremental_db/compiled_partitions/GateDemo.root_partition.cmp.hdb Normal file
View File

Binary file not shown.

1
1ano/2semestre/lsd/aula01/part1/incremental_db/compiled_partitions/GateDemo.root_partition.cmp.logdb Normal file
View File

@ -0,0 +1 @@
v1

BIN
1ano/2semestre/lsd/aula01/part1/incremental_db/compiled_partitions/GateDemo.root_partition.cmp.rcfdb Normal file
View File

Binary file not shown.

BIN
1ano/2semestre/lsd/aula01/part1/incremental_db/compiled_partitions/GateDemo.root_partition.map.cdb Normal file
View File

Binary file not shown.

BIN
1ano/2semestre/lsd/aula01/part1/incremental_db/compiled_partitions/GateDemo.root_partition.map.dpi Normal file
View File

Binary file not shown.

BIN
1ano/2semestre/lsd/aula01/part1/incremental_db/compiled_partitions/GateDemo.root_partition.map.hbdb.cdb Normal file
View File

Binary file not shown.

BIN
1ano/2semestre/lsd/aula01/part1/incremental_db/compiled_partitions/GateDemo.root_partition.map.hbdb.hb_info Normal file
View File

Binary file not shown.

BIN
1ano/2semestre/lsd/aula01/part1/incremental_db/compiled_partitions/GateDemo.root_partition.map.hbdb.hdb Normal file
View File

Binary file not shown.

1
1ano/2semestre/lsd/aula01/part1/incremental_db/compiled_partitions/GateDemo.root_partition.map.hbdb.sig Normal file
View File

@ -0,0 +1 @@
c5eb7f6cdd530884c3b884e0a3668ea4

BIN
1ano/2semestre/lsd/aula01/part1/incremental_db/compiled_partitions/GateDemo.root_partition.map.hdb Normal file
View File

Binary file not shown.

BIN
1ano/2semestre/lsd/aula01/part1/incremental_db/compiled_partitions/GateDemo.root_partition.map.kpt Normal file
View File

Binary file not shown.

BIN
1ano/2semestre/lsd/aula01/part1/incremental_db/compiled_partitions/GateDemo.rrp.hdb Normal file
View File

Binary file not shown.

92
1ano/2semestre/lsd/aula01/part1/output_files/GateDemo.asm.rpt Normal file
View File

@ -0,0 +1,92 @@
Assembler report for GateDemo
Sat Feb 18 15:07:02 2023
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Assembler Summary
3. Assembler Settings
4. Assembler Generated Files
5. Assembler Device Options: GateDemo.sof
6. Assembler Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Sat Feb 18 15:07:02 2023 ;
; Revision Name ; GateDemo ;
; Top-level Entity Name ; GateDemo ;
; Family ; Cyclone IV E ;
; Device ; EP4CE115F29C7 ;
+-----------------------+---------------------------------------+
+----------------------------------+
; Assembler Settings ;
+--------+---------+---------------+
; Option ; Setting ; Default Value ;
+--------+---------+---------------+
+--------------------------------------------------------------------------------------------+
; Assembler Generated Files ;
+--------------------------------------------------------------------------------------------+
; File Name ;
+--------------------------------------------------------------------------------------------+
; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/output_files/GateDemo.sof ;
+--------------------------------------------------------------------------------------------+
+----------------------------------------+
; Assembler Device Options: GateDemo.sof ;
+----------------+-----------------------+
; Option ; Setting ;
+----------------+-----------------------+
; JTAG usercode ; 0x00562D0A ;
; Checksum ; 0x00562D0A ;
+----------------+-----------------------+
+--------------------+
; Assembler Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus Prime Assembler
Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Info: Processing started: Sat Feb 18 15:06:59 2023
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off GateDemo -c GateDemo
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (115031): Writing out detailed assembly data for power analysis
Info (115030): Assembler is generating device programming files
Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
Info: Peak virtual memory: 367 megabytes
Info: Processing ended: Sat Feb 18 15:07:02 2023
Info: Elapsed time: 00:00:03
Info: Total CPU time (on all processors): 00:00:03

1
1ano/2semestre/lsd/aula01/part1/output_files/GateDemo.done Normal file
View File

@ -0,0 +1 @@
Sat Feb 18 15:07:05 2023

94
1ano/2semestre/lsd/aula01/part1/output_files/GateDemo.eda.rpt Normal file
View File

@ -0,0 +1,94 @@
EDA Netlist Writer report for GateDemo
Sat Feb 18 15:07:05 2023
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. EDA Netlist Writer Summary
3. Simulation Settings
4. Simulation Generated Files
5. EDA Netlist Writer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
+-------------------------------------------------------------------+
; EDA Netlist Writer Summary ;
+---------------------------+---------------------------------------+
; EDA Netlist Writer Status ; Successful - Sat Feb 18 15:07:05 2023 ;
; Revision Name ; GateDemo ;
; Top-level Entity Name ; GateDemo ;
; Family ; Cyclone IV E ;
; Simulation Files Creation ; Successful ;
+---------------------------+---------------------------------------+
+----------------------------------------------------------------------------------------------------------------------------+
; Simulation Settings ;
+---------------------------------------------------------------------------------------------------+------------------------+
; Option ; Setting ;
+---------------------------------------------------------------------------------------------------+------------------------+
; Tool Name ; ModelSim-Altera (VHDL) ;
; Generate functional simulation netlist ; On ;
; Truncate long hierarchy paths ; Off ;
; Map illegal HDL characters ; Off ;
; Flatten buses into individual nodes ; Off ;
; Maintain hierarchy ; Off ;
; Bring out device-wide set/reset signals as ports ; Off ;
; Enable glitch filtering ; Off ;
; Do not write top level VHDL entity ; Off ;
; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ;
; Architecture name in VHDL output netlist ; structure ;
; Generate third-party EDA tool command script for RTL functional simulation ; Off ;
; Generate third-party EDA tool command script for gate-level simulation ; Off ;
+---------------------------------------------------------------------------------------------------+------------------------+
+---------------------------------------------------------------------------------------------------+
; Simulation Generated Files ;
+---------------------------------------------------------------------------------------------------+
; Generated Files ;
+---------------------------------------------------------------------------------------------------+
; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/simulation/modelsim/GateDemo.vho ;
+---------------------------------------------------------------------------------------------------+
+-----------------------------+
; EDA Netlist Writer Messages ;
+-----------------------------+
Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Info: Processing started: Sat Feb 18 15:07:04 2023
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off GateDemo -c GateDemo
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (204019): Generated file GateDemo.vho in folder "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/simulation/modelsim/" for EDA simulation tool
Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
Info: Peak virtual memory: 612 megabytes
Info: Processing ended: Sat Feb 18 15:07:05 2023
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:00

2501
1ano/2semestre/lsd/aula01/part1/output_files/GateDemo.fit.rpt Normal file
View File

File diff suppressed because it is too large Load Diff

8
1ano/2semestre/lsd/aula01/part1/output_files/GateDemo.fit.smsg Normal file
View File

@ -0,0 +1,8 @@
Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
Extra Info (176236): Started Fast Input/Output/OE register processing
Extra Info (176237): Finished Fast Input/Output/OE register processing
Extra Info (176238): Start inferring scan chains for DSP blocks
Extra Info (176239): Inferring scan chains for DSP blocks is complete
Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks

16
1ano/2semestre/lsd/aula01/part1/output_files/GateDemo.fit.summary Normal file
View File

@ -0,0 +1,16 @@
Fitter Status : Successful - Sat Feb 18 15:06:58 2023
Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Revision Name : GateDemo
Top-level Entity Name : GateDemo
Family : Cyclone IV E
Device : EP4CE115F29C7
Timing Models : Final
Total logic elements : 1 / 114,480 ( < 1 % )
Total combinational functions : 1 / 114,480 ( < 1 % )
Dedicated logic registers : 0 / 114,480 ( 0 % )
Total registers : 0
Total pins : 3 / 529 ( < 1 % )
Total virtual pins : 0
Total memory bits : 0 / 3,981,312 ( 0 % )
Embedded Multiplier 9-bit elements : 0 / 532 ( 0 % )
Total PLLs : 0 / 4 ( 0 % )

134
1ano/2semestre/lsd/aula01/part1/output_files/GateDemo.flow.rpt Normal file
View File

@ -0,0 +1,134 @@
Flow report for GateDemo
Sat Feb 18 15:07:05 2023
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Non-Default Global Settings
5. Flow Elapsed Time
6. Flow OS Summary
7. Flow Log
8. Flow Messages
9. Flow Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
+----------------------------------------------------------------------------------+
; Flow Summary ;
+------------------------------------+---------------------------------------------+
; Flow Status ; Successful - Sat Feb 18 15:07:05 2023 ;
; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
; Revision Name ; GateDemo ;
; Top-level Entity Name ; GateDemo ;
; Family ; Cyclone IV E ;
; Device ; EP4CE115F29C7 ;
; Timing Models ; Final ;
; Total logic elements ; 1 / 114,480 ( < 1 % ) ;
; Total combinational functions ; 1 / 114,480 ( < 1 % ) ;
; Dedicated logic registers ; 0 / 114,480 ( 0 % ) ;
; Total registers ; 0 ;
; Total pins ; 3 / 529 ( < 1 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 / 3,981,312 ( 0 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ;
; Total PLLs ; 0 / 4 ( 0 % ) ;
+------------------------------------+---------------------------------------------+
+-----------------------------------------+
; Flow Settings ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 02/18/2023 15:06:43 ;
; Main task ; Compilation ;
; Revision Name ; GateDemo ;
+-------------------+---------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; COMPILER_SIGNATURE_ID ; 2690080394329.167673280322737 ; -- ; -- ; -- ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_symbol ;
; EDA_OUTPUT_DATA_FORMAT ; Vhdl ; -- ; -- ; eda_simulation ;
; EDA_SIMULATION_TOOL ; ModelSim-Altera (VHDL) ; <None> ; -- ; -- ;
; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; NOMINAL_CORE_SUPPLY_VOLTAGE ; 1.2V ; -- ; -- ; -- ;
; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
+--------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:06 ; 1.0 ; 399 MB ; 00:00:16 ;
; Fitter ; 00:00:08 ; 1.0 ; 1155 MB ; 00:00:12 ;
; Assembler ; 00:00:03 ; 1.0 ; 367 MB ; 00:00:03 ;
; Timing Analyzer ; 00:00:02 ; 1.0 ; 537 MB ; 00:00:01 ;
; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 612 MB ; 00:00:00 ;
; Total ; 00:00:20 ; -- ; -- ; 00:00:32 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
+----------------------------------------------------------------------------------------+
; Flow OS Summary ;
+----------------------+------------------+----------------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+----------------------+------------------+----------------+------------+----------------+
; Analysis & Synthesis ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
; Fitter ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
; Assembler ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
; Timing Analyzer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
; EDA Netlist Writer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
+----------------------+------------------+----------------+------------+----------------+
------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off GateDemo -c GateDemo
quartus_fit --read_settings_files=off --write_settings_files=off GateDemo -c GateDemo
quartus_asm --read_settings_files=off --write_settings_files=off GateDemo -c GateDemo
quartus_sta GateDemo -c GateDemo
quartus_eda --read_settings_files=off --write_settings_files=off GateDemo -c GateDemo

8
1ano/2semestre/lsd/aula01/part1/output_files/GateDemo.jdi Normal file
View File

@ -0,0 +1,8 @@
<sld_project_info>
<project>
<hash md5_digest_80b="1e768ae0ce372fcdd344"/>
</project>
<file_info>
<file device="EP4CE115F29C7" path="GateDemo.sof" usercode="0xFFFFFFFF"/>
</file_info>
</sld_project_info>

281
1ano/2semestre/lsd/aula01/part1/output_files/GateDemo.map.rpt Normal file
View File

@ -0,0 +1,281 @@
Analysis & Synthesis report for GateDemo
Sat Feb 18 15:06:49 2023
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Parallel Compilation
5. Analysis & Synthesis Source Files Read
6. Analysis & Synthesis Resource Usage Summary
7. Analysis & Synthesis Resource Utilization by Entity
8. General Register Statistics
9. Post-Synthesis Netlist Statistics for Top Partition
10. Elapsed Time Per Partition
11. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
+----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+---------------------------------------------+
; Analysis & Synthesis Status ; Successful - Sat Feb 18 15:06:49 2023 ;
; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
; Revision Name ; GateDemo ;
; Top-level Entity Name ; GateDemo ;
; Family ; Cyclone IV E ;
; Total logic elements ; 1 ;
; Total combinational functions ; 1 ;
; Dedicated logic registers ; 0 ;
; Total registers ; 0 ;
; Total pins ; 3 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 ;
; Embedded Multiplier 9-bit elements ; 0 ;
; Total PLLs ; 0 ;
+------------------------------------+---------------------------------------------+
+------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+------------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+------------------------------------------------------------------+--------------------+--------------------+
; Device ; EP4CE115F29C7 ; ;
; Top-level entity name ; GateDemo ; GateDemo ;
; Family name ; Cyclone IV E ; Cyclone V ;
; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Intel FPGA IP Evaluation Mode ; Enable ; Enable ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Infer RAMs from Raw Logic ; On ; On ;
; Parallel Synthesis ; On ; On ;
; DSP Block Balancing ; Auto ; Auto ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique ; Balanced ; Balanced ;
; Carry Chain Length ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto DSP Block Replacement ; On ; On ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Strict RAM Replacement ; Off ; Off ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto RAM Block Balancing ; On ; On ;
; Auto RAM to Logic Cell Conversion ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Timing-Driven Synthesis ; On ; On ;
; Report Parameter Settings ; On ; On ;
; Report Source Assignments ; On ; On ;
; Report Connectivity Checks ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Synchronization Register Chain Length ; 2 ; 2 ;
; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Auto Gated Clock Conversion ; Off ; Off ;
; Block Design Naming ; Auto ; Auto ;
; SDC constraint protection ; Off ; Off ;
; Synthesis Effort ; Auto ; Auto ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
; Analysis & Synthesis Message Level ; Medium ; Medium ;
; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
; Resource Aware Inference For Block RAM ; On ; On ;
+------------------------------------------------------------------+--------------------+--------------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 8 ;
; Maximum allowed ; 4 ;
; ; ;
; Average used ; 1.00 ;
; Maximum used ; 1 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
+----------------------------+-------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------------+-------------------------------------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+----------------------------------+-----------------+------------------------------------+-------------------------------------------------------------------------------+---------+
; GateDemo.bdf ; yes ; User Block Diagram/Schematic File ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/GateDemo.bdf ; ;
+----------------------------------+-----------------+------------------------------------+-------------------------------------------------------------------------------+---------+
+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+-------+
; Resource ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements ; 1 ;
; ; ;
; Total combinational functions ; 1 ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 0 ;
; -- 3 input functions ; 0 ;
; -- <=2 input functions ; 1 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 1 ;
; -- arithmetic mode ; 0 ;
; ; ;
; Total registers ; 0 ;
; -- Dedicated logic registers ; 0 ;
; -- I/O registers ; 0 ;
; ; ;
; I/O pins ; 3 ;
; ; ;
; Embedded Multiplier 9-bit elements ; 0 ;
; ; ;
; Maximum fan-out node ; inst ;
; Maximum fan-out ; 1 ;
; Total fan-out ; 6 ;
; Average fan-out ; 0.86 ;
+---------------------------------------------+-------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+---------------------+-------------+--------------+
; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+---------------------+-------------+--------------+
; |GateDemo ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 3 ; 0 ; |GateDemo ; GateDemo ; work ;
+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+---------------------+-------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 0 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-----------------------------------------------------+
; Post-Synthesis Netlist Statistics for Top Partition ;
+-----------------------+-----------------------------+
; Type ; Count ;
+-----------------------+-----------------------------+
; boundary_port ; 3 ;
; cycloneiii_lcell_comb ; 1 ;
; normal ; 1 ;
; 2 data inputs ; 1 ;
; ; ;
; Max LUT depth ; 1.00 ;
; Average LUT depth ; 1.00 ;
+-----------------------+-----------------------------+
+-------------------------------+
; Elapsed Time Per Partition ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top ; 00:00:00 ;
+----------------+--------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Info: Processing started: Sat Feb 18 15:06:43 2023
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GateDemo -c GateDemo
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
Info (12021): Found 1 design units, including 1 entities, in source file GateDemo.bdf
Info (12023): Found entity 1: GateDemo
Info (12127): Elaborating entity "GateDemo" for the top level hierarchy
Info (286030): Timing-Driven Synthesis is running
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
Info (21057): Implemented 4 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 2 input pins
Info (21059): Implemented 1 output pins
Info (21061): Implemented 1 logic cells
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning
Info: Peak virtual memory: 403 megabytes
Info: Processing ended: Sat Feb 18 15:06:49 2023
Info: Elapsed time: 00:00:06
Info: Total CPU time (on all processors): 00:00:16

14
1ano/2semestre/lsd/aula01/part1/output_files/GateDemo.map.summary Normal file
View File

@ -0,0 +1,14 @@
Analysis & Synthesis Status : Successful - Sat Feb 18 15:06:49 2023
Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Revision Name : GateDemo
Top-level Entity Name : GateDemo
Family : Cyclone IV E
Total logic elements : 1
Total combinational functions : 1
Dedicated logic registers : 0
Total registers : 0
Total pins : 3
Total virtual pins : 0
Total memory bits : 0
Embedded Multiplier 9-bit elements : 0
Total PLLs : 0

851
1ano/2semestre/lsd/aula01/part1/output_files/GateDemo.pin Normal file
View File

@ -0,0 +1,851 @@
-- Copyright (C) 2020 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details, at
-- https://fpgasoftware.intel.com/eula.
--
-- This is a Quartus Prime output file. It is for reporting purposes only, and is
-- not intended for use as a Quartus Prime input file. This file cannot be used
-- to make Quartus Prime pin assignments - for instructions on how to make pin
-- assignments, please see Quartus Prime help.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- NC : No Connect. This pin has no internal connection to the device.
-- DNU : Do Not Use. This pin MUST NOT be connected.
-- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
-- VCCIO : Dedicated power pin, which MUST be connected to VCC
-- of its bank.
-- Bank 1: 2.5V
-- Bank 2: 2.5V
-- Bank 3: 2.5V
-- Bank 4: 2.5V
-- Bank 5: 2.5V
-- Bank 6: 2.5V
-- Bank 7: 2.5V
-- Bank 8: 2.5V
-- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
-- It can also be used to report unused dedicated pins. The connection
-- on the board for unused dedicated pins depends on whether this will
-- be used in a future design. One example is device migration. When
-- using device migration, refer to the device pin-tables. If it is a
-- GND pin in the pin table or if it will not be used in a future design
-- for another purpose the it MUST be connected to GND. If it is an unused
-- dedicated pin, then it can be connected to a valid signal on the board
-- (low, high, or toggling) if that signal is required for a different
-- revision of the design.
-- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
-- This pin should be connected to GND. It may also be connected to a
-- valid signal on the board (low, high, or toggling) if that signal
-- is required for a different revision of the design.
-- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
-- or leave it unconnected.
-- RESERVED : Unused I/O pin, which MUST be left unconnected.
-- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
-- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
-- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
-- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- Pin directions (input, output or bidir) are based on device operating in user mode.
---------------------------------------------------------------------------------
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
CHIP "GateDemo" ASSIGNED TO AN: EP4CE115F29C7
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
-------------------------------------------------------------------------------------------------------------
VCCIO8 : A2 : power : : 2.5V : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8 :
VCCIO8 : A5 : power : : 2.5V : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 8 :
VCCIO8 : A9 : power : : 2.5V : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A12 : : : : 8 :
VCCIO8 : A13 : power : : 2.5V : 8 :
GND+ : A14 : : : : 8 :
GND+ : A15 : : : : 7 :
VCCIO7 : A16 : power : : 2.5V : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A17 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7 :
VCCIO7 : A20 : power : : 2.5V : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A21 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A22 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A23 : : : : 7 :
VCCIO7 : A24 : power : : 2.5V : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A25 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : A26 : : : : 7 :
VCCIO7 : A27 : power : : 2.5V : 7 :
VCCIO2 : AA1 : power : : 2.5V : 2 :
GND : AA2 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA3 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA4 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA5 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA6 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA8 : : : : 3 :
GNDA1 : AA9 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA10 : : : : 3 :
VCCIO3 : AA11 : power : : 2.5V : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA12 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA13 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA14 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA15 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA17 : : : : 4 :
VCCIO4 : AA18 : power : : 2.5V : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA19 : : : : 4 :
GNDA4 : AA20 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA22 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA23 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA24 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA25 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AA26 : : : : 5 :
GND : AA27 : gnd : : : :
VCCIO5 : AA28 : power : : 2.5V : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB1 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB2 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB3 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB4 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB5 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB6 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB7 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB8 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB9 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB10 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB11 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB13 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB14 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB16 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB18 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB19 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB20 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB21 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB22 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB23 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB24 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB25 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB26 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AB27 : : : : 5 :
SW[0] : AB28 : input : 2.5 V : : 5 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : AC1 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC2 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC3 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC4 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC5 : : : : 2 :
GND : AC6 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC7 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC8 : : : : 3 :
GND : AC9 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC10 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC11 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC12 : : : : 3 :
GND : AC13 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC14 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC15 : : : : 4 :
GND : AC16 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC17 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC18 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC19 : : : : 4 :
GND : AC20 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC21 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC22 : : : : 4 :
GND : AC23 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC24 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC25 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC26 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AC27 : : : : 5 :
SW[1] : AC28 : input : 2.5 V : : 5 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : AD1 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD2 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD3 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD4 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD5 : : : : 3 :
VCCIO3 : AD6 : power : : 2.5V : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD7 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD8 : : : : 3 :
VCCIO3 : AD9 : power : : 2.5V : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD10 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD11 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD12 : : : : 3 :
VCCIO3 : AD13 : power : : 2.5V : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD14 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD15 : : : : 4 :
VCCIO4 : AD16 : power : : 2.5V : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD17 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD18 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD19 : : : : 4 :
VCCIO4 : AD20 : power : : 2.5V : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD21 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD22 : : : : 4 :
VCCIO4 : AD23 : power : : 2.5V : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD24 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD25 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD26 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD27 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AD28 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE1 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE2 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE3 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE4 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE5 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE6 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE7 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE8 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE9 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE10 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE11 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE12 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE13 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE14 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE15 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE16 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE17 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE18 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE19 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE20 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE21 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE22 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE23 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE24 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE25 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE26 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE27 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AE28 : : : : 5 :
GND : AF1 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF2 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF3 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF4 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF5 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF6 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF7 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF8 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF9 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF10 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF11 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF12 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF13 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF14 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF15 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF16 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF17 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF18 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF19 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF20 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF21 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF22 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF23 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF24 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF25 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF26 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AF27 : : : : 5 :
GND : AF28 : gnd : : : :
VCCIO2 : AG1 : power : : 2.5V : 2 :
GND : AG2 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AG3 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AG4 : : : : 3 :
GND : AG5 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AG6 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AG7 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AG8 : : : : 3 :
GND : AG9 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AG10 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AG11 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AG12 : : : : 3 :
GND : AG13 : gnd : : : :
GND+ : AG14 : : : : 3 :
GND+ : AG15 : : : : 4 :
GND : AG16 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AG17 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AG18 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AG19 : : : : 4 :
GND : AG20 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AG21 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AG22 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AG23 : : : : 4 :
GND : AG24 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : AG25 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AG26 : : : : 4 :
GND : AG27 : gnd : : : :
VCCIO5 : AG28 : power : : 2.5V : 5 :
VCCIO3 : AH2 : power : : 2.5V : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AH3 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AH4 : : : : 3 :
VCCIO3 : AH5 : power : : 2.5V : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AH6 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AH7 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AH8 : : : : 3 :
VCCIO3 : AH9 : power : : 2.5V : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AH10 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AH11 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AH12 : : : : 3 :
VCCIO3 : AH13 : power : : 2.5V : 3 :
GND+ : AH14 : : : : 3 :
GND+ : AH15 : : : : 4 :
VCCIO4 : AH16 : power : : 2.5V : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AH17 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AH18 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AH19 : : : : 4 :
VCCIO4 : AH20 : power : : 2.5V : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AH21 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AH22 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AH23 : : : : 4 :
VCCIO4 : AH24 : power : : 2.5V : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AH25 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : AH26 : : : : 4 :
VCCIO4 : AH27 : power : : 2.5V : 4 :
VCCIO1 : B1 : power : : 2.5V : 1 :
GND : B2 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 :
GND : B5 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 8 :
GND : B9 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 8 :
GND : B12 : gnd : : : :
GND : B13 : gnd : : : :
GND+ : B14 : : : : 8 :
GND+ : B15 : : : : 7 :
GND : B16 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : B17 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B18 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B19 : : : : 7 :
GND : B20 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B23 : : : : 7 :
GND : B24 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : B25 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : B26 : : : : 7 :
GND : B27 : gnd : : : :
VCCIO6 : B28 : power : : 2.5V : 6 :
GND : C1 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C5 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C6 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C10 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C11 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C12 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C16 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C17 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C18 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C21 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C23 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C24 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C25 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C26 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : C27 : : : : 6 :
GND : C28 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : : : : 1 :
GND : D3 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : D4 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D8 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D11 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D13 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D16 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D17 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D18 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D19 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D20 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D23 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D24 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D25 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D26 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D27 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : D28 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E1 : : : : 1 :
~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : E2 : input : 2.5 V : : 1 : N
RESERVED_INPUT_WITH_WEAK_PULLUP : E3 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E4 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E5 : : : : 8 :
VCCIO8 : E6 : power : : 2.5V : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E7 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8 :
VCCIO8 : E9 : power : : 2.5V : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E12 : : : : 8 :
VCCIO8 : E13 : power : : 2.5V : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E14 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E15 : : : : 7 :
VCCIO7 : E16 : power : : 2.5V : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E17 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E18 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E19 : : : : 7 :
VCCIO7 : E20 : power : : 2.5V : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E21 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E22 : : : : 7 :
VCCIO7 : E23 : power : : 2.5V : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E24 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E25 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E26 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E27 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : E28 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : F1 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : F2 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : F3 : : : : 1 :
~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : F4 : input : 2.5 V : : 1 : N
RESERVED_INPUT_WITH_WEAK_PULLUP : F5 : : : : 1 :
GND : F6 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : F7 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : F8 : : : : 8 :
GND : F9 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : F10 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : F11 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : F12 : : : : 8 :
GND : F13 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : F14 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 7 :
GND : F16 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : F17 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : F18 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : F19 : : : : 7 :
GND : F20 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : F21 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : F22 : : : : 7 :
GND : F23 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : F24 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : F25 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : F26 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : F27 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : F28 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : G1 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : G2 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : G3 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : G4 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : G5 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : G6 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : G7 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : G8 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : G9 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : G10 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : G11 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : G12 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : G13 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : G14 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : G15 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : G16 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : G17 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : G18 : : : : 7 :
LEDR[0] : G19 : output : 2.5 V : : 7 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : G20 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : G21 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : G22 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : G23 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : G24 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : G25 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : G26 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : G27 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : G28 : : : : 6 :
VCCIO1 : H1 : power : : 2.5V : 1 :
GND : H2 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : H3 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : H4 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : H5 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : H6 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : H7 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : H8 : : : : 8 :
GNDA3 : H9 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : H10 : : : : 8 :
VCCIO8 : H11 : power : : 2.5V : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : H15 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : H16 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 7 :
VCCIO7 : H18 : power : : 2.5V : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : H19 : : : : 7 :
GNDA2 : H20 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : H21 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : H22 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : H23 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : H24 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : H25 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : H26 : : : : 6 :
GND : H27 : gnd : : : :
VCCIO6 : H28 : power : : 2.5V : 6 :
GND+ : J1 : : : : 1 :
GND : J2 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : J3 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : J4 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : J5 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : J6 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : J7 : : : : 1 :
VCCA3 : J8 : power : : 2.5V : :
VCCD_PLL3 : J9 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : J10 : : : : 8 :
GND : J11 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : J13 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : J15 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : J16 : : : : 7 :
RESERVED_INPUT_WITH_WEAK_PULLUP : J17 : : : : 7 :
GND : J18 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : J19 : : : : 7 :
VCCD_PLL2 : J20 : power : : 1.2V : :
VCCA2 : J21 : power : : 2.5V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : J22 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : J23 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : J24 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : J25 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : J26 : : : : 6 :
GND+ : J27 : : : : 6 :
GND+ : J28 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : K1 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : K2 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : K3 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : K4 : : : : 1 :
VCCIO1 : K5 : power : : 2.5V : 1 :
GND : K6 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : K7 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 1 :
VCCINT : K9 : power : : 1.2V : :
GND : K10 : gnd : : : :
VCCINT : K11 : power : : 1.2V : :
GND : K12 : gnd : : : :
VCCINT : K13 : power : : 1.2V : :
GND : K14 : gnd : : : :
VCCINT : K15 : power : : 1.2V : :
GND : K16 : gnd : : : :
VCCINT : K17 : power : : 1.2V : :
GND : K18 : gnd : : : :
VCCINT : K19 : power : : 1.2V : :
GND : K20 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : K22 : : : : 6 :
GND : K23 : gnd : : : :
VCCIO6 : K24 : power : : 2.5V : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : K25 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : K26 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : K27 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : K28 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : L1 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : L2 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : L3 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : L4 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : L5 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : L6 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : L7 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : L8 : : : : 1 :
GND : L9 : gnd : : : :
VCCINT : L10 : power : : 1.2V : :
GND : L11 : gnd : : : :
VCCINT : L12 : power : : 1.2V : :
GND : L13 : gnd : : : :
VCCINT : L14 : power : : 1.2V : :
GND : L15 : gnd : : : :
VCCINT : L16 : power : : 1.2V : :
GND : L17 : gnd : : : :
VCCINT : L18 : power : : 1.2V : :
GND : L19 : gnd : : : :
VCCINT : L20 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : L21 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : L22 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : L23 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : L24 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : L25 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : L26 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : L27 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : L28 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : M1 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : M2 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : M3 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : M4 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : M5 : : : : 1 :
nSTATUS : M6 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : M7 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : M8 : : : : 1 :
VCCINT : M9 : power : : 1.2V : :
GND : M10 : gnd : : : :
VCCINT : M11 : power : : 1.2V : :
GND : M12 : gnd : : : :
VCCINT : M13 : power : : 1.2V : :
GND : M14 : gnd : : : :
VCCINT : M15 : power : : 1.2V : :
GND : M16 : gnd : : : :
VCCINT : M17 : power : : 1.2V : :
GND : M18 : gnd : : : :
VCCINT : M19 : power : : 1.2V : :
GND : M20 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : M21 : : : : 6 :
MSEL2 : M22 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : M23 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : M24 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : M25 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : M26 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : M27 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : M28 : : : : 6 :
VCCIO1 : N1 : power : : 2.5V : 1 :
GND : N2 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : N3 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N4 : : : : 1 :
VCCIO1 : N5 : power : : 2.5V : 1 :
GND : N6 : gnd : : : :
~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : N7 : input : 2.5 V : : 1 : N
RESERVED_INPUT_WITH_WEAK_PULLUP : N8 : : : : 1 :
GND : N9 : gnd : : : :
VCCINT : N10 : power : : 1.2V : :
GND : N11 : gnd : : : :
VCCINT : N12 : power : : 1.2V : :
GND : N13 : gnd : : : :
VCCINT : N14 : power : : 1.2V : :
GND : N15 : gnd : : : :
VCCINT : N16 : power : : 1.2V : :
GND : N17 : gnd : : : :
VCCINT : N18 : power : : 1.2V : :
GND : N19 : gnd : : : :
VCCINT : N20 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : N21 : : : : 6 :
MSEL0 : N22 : : : : 6 :
GND : N23 : gnd : : : :
VCCIO6 : N24 : power : : 2.5V : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N25 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : N26 : : : : 6 :
GND : N27 : gnd : : : :
VCCIO6 : N28 : power : : 2.5V : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P1 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P2 : : : : 1 :
~ALTERA_DCLK~ : P3 : output : 2.5 V : : 1 : N
nCONFIG : P4 : : : : 1 :
TCK : P5 : input : : : 1 :
TDO : P6 : output : : : 1 :
TDI : P7 : input : : : 1 :
TMS : P8 : input : : : 1 :
VCCINT : P9 : power : : 1.2V : :
GND : P10 : gnd : : : :
VCCINT : P11 : power : : 1.2V : :
GND : P12 : gnd : : : :
VCCINT : P13 : power : : 1.2V : :
GND : P14 : gnd : : : :
VCCINT : P15 : power : : 1.2V : :
GND : P16 : gnd : : : :
VCCINT : P17 : power : : 1.2V : :
GND : P18 : gnd : : : :
VCCINT : P19 : power : : 1.2V : :
GND : P20 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : P21 : : : : 5 :
MSEL3 : P22 : : : : 6 :
MSEL1 : P23 : : : : 6 :
CONF_DONE : P24 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P25 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P26 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : P27 : : : : 6 :
~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : P28 : output : 2.5 V : : 6 : N
RESERVED_INPUT_WITH_WEAK_PULLUP : R1 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R2 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R3 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R4 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R5 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R6 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R7 : : : : 2 :
nCE : R8 : : : : 1 :
GND : R9 : gnd : : : :
VCCINT : R10 : power : : 1.2V : :
GND : R11 : gnd : : : :
VCCINT : R12 : power : : 1.2V : :
GND : R13 : gnd : : : :
VCCINT : R14 : power : : 1.2V : :
GND : R15 : gnd : : : :
VCCINT : R16 : power : : 1.2V : :
GND : R17 : gnd : : : :
VCCINT : R18 : power : : 1.2V : :
GND : R19 : gnd : : : :
VCCINT : R20 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : R21 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R22 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R23 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R24 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R25 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R26 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R27 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : R28 : : : : 5 :
VCCIO2 : T1 : power : : 2.5V : 2 :
GND : T2 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : T3 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T4 : : : : 2 :
VCCIO2 : T5 : power : : 2.5V : 2 :
GND : T6 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : T7 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T8 : : : : 2 :
VCCINT : T9 : power : : 1.2V : :
GND : T10 : gnd : : : :
VCCINT : T11 : power : : 1.2V : :
GND : T12 : gnd : : : :
VCCINT : T13 : power : : 1.2V : :
GND : T14 : gnd : : : :
VCCINT : T15 : power : : 1.2V : :
GND : T16 : gnd : : : :
VCCINT : T17 : power : : 1.2V : :
GND : T18 : gnd : : : :
VCCINT : T19 : power : : 1.2V : :
GND : T20 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : T21 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T22 : : : : 5 :
GND : T23 : gnd : : : :
VCCIO5 : T24 : power : : 2.5V : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T25 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : T26 : : : : 5 :
GND : T27 : gnd : : : :
VCCIO5 : T28 : power : : 2.5V : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U1 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U2 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U3 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U4 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U5 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U6 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U8 : : : : 2 :
GND : U9 : gnd : : : :
VCCINT : U10 : power : : 1.2V : :
GND : U11 : gnd : : : :
VCCINT : U12 : power : : 1.2V : :
GND : U13 : gnd : : : :
VCCINT : U14 : power : : 1.2V : :
GND : U15 : gnd : : : :
VCCINT : U16 : power : : 1.2V : :
GND : U17 : gnd : : : :
VCCINT : U18 : power : : 1.2V : :
GND : U19 : gnd : : : :
VCCINT : U20 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : U21 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U22 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U23 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U24 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U25 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U26 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U27 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : U28 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V1 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V2 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V3 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V4 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V5 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V6 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V7 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V8 : : : : 2 :
VCCINT : V9 : power : : 1.2V : :
GND : V10 : gnd : : : :
VCCINT : V11 : power : : 1.2V : :
GND : V12 : gnd : : : :
VCCINT : V13 : power : : 1.2V : :
GND : V14 : gnd : : : :
VCCINT : V15 : power : : 1.2V : :
GND : V16 : gnd : : : :
VCCINT : V17 : power : : 1.2V : :
GND : V18 : gnd : : : :
VCCINT : V19 : power : : 1.2V : :
GND : V20 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : V21 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V23 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V24 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V25 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V26 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V27 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : V28 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W1 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W2 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W3 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W4 : : : : 2 :
VCCIO2 : W5 : power : : 2.5V : 2 :
GND : W6 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : W7 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 2 :
GND : W9 : gnd : : : :
VCCINT : W10 : power : : 1.2V : :
GND : W11 : gnd : : : :
VCCINT : W12 : power : : 1.2V : :
GND : W13 : gnd : : : :
VCCINT : W14 : power : : 1.2V : :
GND : W15 : gnd : : : :
VCCINT : W16 : power : : 1.2V : :
GND : W17 : gnd : : : :
VCCINT : W18 : power : : 1.2V : :
GND : W19 : gnd : : : :
VCCINT : W20 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : W21 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W22 : : : : 5 :
GND : W23 : gnd : : : :
VCCIO5 : W24 : power : : 2.5V : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W25 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W26 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W27 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : W28 : : : : 5 :
GND+ : Y1 : : : : 2 :
GND+ : Y2 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y3 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y4 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y5 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y6 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y7 : : : : 2 :
VCCA1 : Y8 : power : : 2.5V : :
VCCD_PLL1 : Y9 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y10 : : : : 3 :
GND : Y11 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y12 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y14 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y15 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y17 : : : : 4 :
GND : Y18 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y19 : : : : 4 :
VCCD_PLL4 : Y20 : power : : 1.2V : :
VCCA4 : Y21 : power : : 2.5V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y22 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y23 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y24 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y25 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : Y26 : : : : 5 :
GND+ : Y27 : : : : 5 :
GND+ : Y28 : : : : 5 :

1
1ano/2semestre/lsd/aula01/part1/output_files/GateDemo.sld Normal file
View File

@ -0,0 +1 @@
<sld_project_info/>

BIN
1ano/2semestre/lsd/aula01/part1/output_files/GateDemo.sof Normal file
View File

Binary file not shown.

431
1ano/2semestre/lsd/aula01/part1/output_files/GateDemo.sta.rpt Normal file
View File

@ -0,0 +1,431 @@
Timing Analyzer report for GateDemo
Sat Feb 18 15:07:04 2023
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Parallel Compilation
4. Clocks
5. Slow 1200mV 85C Model Fmax Summary
6. Timing Closure Recommendations
7. Slow 1200mV 85C Model Setup Summary
8. Slow 1200mV 85C Model Hold Summary
9. Slow 1200mV 85C Model Recovery Summary
10. Slow 1200mV 85C Model Removal Summary
11. Slow 1200mV 85C Model Minimum Pulse Width Summary
12. Slow 1200mV 85C Model Metastability Summary
13. Slow 1200mV 0C Model Fmax Summary
14. Slow 1200mV 0C Model Setup Summary
15. Slow 1200mV 0C Model Hold Summary
16. Slow 1200mV 0C Model Recovery Summary
17. Slow 1200mV 0C Model Removal Summary
18. Slow 1200mV 0C Model Minimum Pulse Width Summary
19. Slow 1200mV 0C Model Metastability Summary
20. Fast 1200mV 0C Model Setup Summary
21. Fast 1200mV 0C Model Hold Summary
22. Fast 1200mV 0C Model Recovery Summary
23. Fast 1200mV 0C Model Removal Summary
24. Fast 1200mV 0C Model Minimum Pulse Width Summary
25. Fast 1200mV 0C Model Metastability Summary
26. Multicorner Timing Analysis Summary
27. Board Trace Model Assignments
28. Input Transition Times
29. Signal Integrity Metrics (Slow 1200mv 0c Model)
30. Signal Integrity Metrics (Slow 1200mv 85c Model)
31. Signal Integrity Metrics (Fast 1200mv 0c Model)
32. Clock Transfers
33. Report TCCS
34. Report RSKM
35. Unconstrained Paths Summary
36. Unconstrained Input Ports
37. Unconstrained Output Ports
38. Unconstrained Input Ports
39. Unconstrained Output Ports
40. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
+-----------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+-----------------------+-----------------------------------------------------+
; Quartus Prime Version ; Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
; Timing Analyzer ; Legacy Timing Analyzer ;
; Revision Name ; GateDemo ;
; Device Family ; Cyclone IV E ;
; Device Name ; EP4CE115F29C7 ;
; Timing Models ; Final ;
; Delay Model ; Combined ;
; Rise/Fall Delays ; Enabled ;
+-----------------------+-----------------------------------------------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 8 ;
; Maximum allowed ; 4 ;
; ; ;
; Average used ; 1.00 ;
; Maximum used ; 4 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
; Processors 2-4 ; 0.1% ;
+----------------------------+-------------+
----------
; Clocks ;
----------
No clocks to report.
--------------------------------------
; Slow 1200mV 85C Model Fmax Summary ;
--------------------------------------
No paths to report.
----------------------------------
; Timing Closure Recommendations ;
----------------------------------
HTML report is unavailable in plain text report export.
---------------------------------------
; Slow 1200mV 85C Model Setup Summary ;
---------------------------------------
No paths to report.
--------------------------------------
; Slow 1200mV 85C Model Hold Summary ;
--------------------------------------
No paths to report.
------------------------------------------
; Slow 1200mV 85C Model Recovery Summary ;
------------------------------------------
No paths to report.
-----------------------------------------
; Slow 1200mV 85C Model Removal Summary ;
-----------------------------------------
No paths to report.
-----------------------------------------------------
; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
-----------------------------------------------------
No paths to report.
-----------------------------------------------
; Slow 1200mV 85C Model Metastability Summary ;
-----------------------------------------------
No synchronizer chains to report.
-------------------------------------
; Slow 1200mV 0C Model Fmax Summary ;
-------------------------------------
No paths to report.
--------------------------------------
; Slow 1200mV 0C Model Setup Summary ;
--------------------------------------
No paths to report.
-------------------------------------
; Slow 1200mV 0C Model Hold Summary ;
-------------------------------------
No paths to report.
-----------------------------------------
; Slow 1200mV 0C Model Recovery Summary ;
-----------------------------------------
No paths to report.
----------------------------------------
; Slow 1200mV 0C Model Removal Summary ;
----------------------------------------
No paths to report.
----------------------------------------------------
; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
----------------------------------------------------
No paths to report.
----------------------------------------------
; Slow 1200mV 0C Model Metastability Summary ;
----------------------------------------------
No synchronizer chains to report.
--------------------------------------
; Fast 1200mV 0C Model Setup Summary ;
--------------------------------------
No paths to report.
-------------------------------------
; Fast 1200mV 0C Model Hold Summary ;
-------------------------------------
No paths to report.
-----------------------------------------
; Fast 1200mV 0C Model Recovery Summary ;
-----------------------------------------
No paths to report.
----------------------------------------
; Fast 1200mV 0C Model Removal Summary ;
----------------------------------------
No paths to report.
----------------------------------------------------
; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
----------------------------------------------------
No paths to report.
----------------------------------------------
; Fast 1200mV 0C Model Metastability Summary ;
----------------------------------------------
No synchronizer chains to report.
+----------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary ;
+------------------+-------+------+----------+---------+---------------------+
; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
+------------------+-------+------+----------+---------+---------------------+
; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; N/A ;
; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ;
+------------------+-------+------+----------+---------+---------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments ;
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; LEDR[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; ~ALTERA_DCLK~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
; ~ALTERA_nCEO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+----------------------------------------------------------------------------+
; Input Transition Times ;
+-------------------------+--------------+-----------------+-----------------+
; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+-------------------------+--------------+-----------------+-----------------+
; SW[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
; SW[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
; ~ALTERA_ASDO_DATA1~ ; 2.5 V ; 2000 ps ; 2000 ps ;
; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V ; 2000 ps ; 2000 ps ;
; ~ALTERA_DATA0~ ; 2.5 V ; 2000 ps ; 2000 ps ;
+-------------------------+--------------+-----------------+-----------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 0c Model) ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.67e-09 V ; 2.38 V ; -0.0485 V ; 0.167 V ; 0.096 V ; 2.95e-10 s ; 2.73e-10 s ; Yes ; Yes ; 2.32 V ; 2.67e-09 V ; 2.38 V ; -0.0485 V ; 0.167 V ; 0.096 V ; 2.95e-10 s ; 2.73e-10 s ; Yes ; Yes ;
; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.18e-09 V ; 2.38 V ; -0.00483 V ; 0.152 V ; 0.012 V ; 4.81e-10 s ; 6.29e-10 s ; Yes ; Yes ; 2.32 V ; 4.18e-09 V ; 2.38 V ; -0.00483 V ; 0.152 V ; 0.012 V ; 4.81e-10 s ; 6.29e-10 s ; Yes ; Yes ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 85c Model) ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.75e-07 V ; 2.35 V ; -0.0109 V ; 0.084 V ; 0.027 V ; 4.31e-10 s ; 3.61e-10 s ; Yes ; Yes ; 2.32 V ; 3.75e-07 V ; 2.35 V ; -0.0109 V ; 0.084 V ; 0.027 V ; 4.31e-10 s ; 3.61e-10 s ; Yes ; Yes ;
; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.15e-07 V ; 2.35 V ; -0.00712 V ; 0.093 V ; 0.02 V ; 6.21e-10 s ; 7.9e-10 s ; Yes ; Yes ; 2.32 V ; 6.15e-07 V ; 2.35 V ; -0.00712 V ; 0.093 V ; 0.02 V ; 6.21e-10 s ; 7.9e-10 s ; Yes ; Yes ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Fast 1200mv 0c Model) ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ;
; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-------------------
; Clock Transfers ;
-------------------
Nothing to report.
---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design
---------------
; Report RSKM ;
---------------
No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+------------------------------------------------+
; Unconstrained Paths Summary ;
+---------------------------------+-------+------+
; Property ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks ; 0 ; 0 ;
; Unconstrained Clocks ; 0 ; 0 ;
; Unconstrained Input Ports ; 2 ; 2 ;
; Unconstrained Input Port Paths ; 2 ; 2 ;
; Unconstrained Output Ports ; 1 ; 1 ;
; Unconstrained Output Port Paths ; 2 ; 2 ;
+---------------------------------+-------+------+
+---------------------------------------------------------------------------------------------------+
; Unconstrained Input Ports ;
+------------+--------------------------------------------------------------------------------------+
; Input Port ; Comment ;
+------------+--------------------------------------------------------------------------------------+
; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+------------+--------------------------------------------------------------------------------------+
+-----------------------------------------------------------------------------------------------------+
; Unconstrained Output Ports ;
+-------------+---------------------------------------------------------------------------------------+
; Output Port ; Comment ;
+-------------+---------------------------------------------------------------------------------------+
; LEDR[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+-------------+---------------------------------------------------------------------------------------+
+---------------------------------------------------------------------------------------------------+
; Unconstrained Input Ports ;
+------------+--------------------------------------------------------------------------------------+
; Input Port ; Comment ;
+------------+--------------------------------------------------------------------------------------+
; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+------------+--------------------------------------------------------------------------------------+
+-----------------------------------------------------------------------------------------------------+
; Unconstrained Output Ports ;
+-------------+---------------------------------------------------------------------------------------+
; Output Port ; Comment ;
+-------------+---------------------------------------------------------------------------------------+
; LEDR[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+-------------+---------------------------------------------------------------------------------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Timing Analyzer
Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Info: Processing started: Sat Feb 18 15:07:02 2023
Info: Command: quartus_sta GateDemo -c GateDemo
Info: qsta_default_script.tcl version: #1
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Critical Warning (332012): Synopsys Design Constraints File file not found: 'GateDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
Warning (332068): No clocks defined in design.
Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info (332159): No clocks to report
Info: Analyzing Slow 1200mV 85C Model
Info (332140): No fmax paths to report
Info (332140): No Setup paths to report
Info (332140): No Hold paths to report
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332140): No Minimum Pulse Width paths to report
Info: Analyzing Slow 1200mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
Warning (332068): No clocks defined in design.
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
Info (332140): No fmax paths to report
Info (332140): No Setup paths to report
Info (332140): No Hold paths to report
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332140): No Minimum Pulse Width paths to report
Info: Analyzing Fast 1200mV 0C Model
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
Warning (332068): No clocks defined in design.
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
Info (332140): No Setup paths to report
Info (332140): No Hold paths to report
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332140): No Minimum Pulse Width paths to report
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings
Info: Peak virtual memory: 537 megabytes
Info: Processing ended: Sat Feb 18 15:07:04 2023
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:01

5
1ano/2semestre/lsd/aula01/part1/output_files/GateDemo.sta.summary Normal file
View File

@ -0,0 +1,5 @@
------------------------------------------------------------
Timing Analyzer Summary
------------------------------------------------------------
------------------------------------------------------------

1
1ano/2semestre/lsd/aula01/part1/simulation/modelsim/GateDemo.sft Normal file
View File

@ -0,0 +1 @@
set tool_name "ModelSim-Altera (VHDL)"

180
1ano/2semestre/lsd/aula01/part1/simulation/modelsim/GateDemo.vho Normal file
View File

@ -0,0 +1,180 @@
-- Copyright (C) 2020 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details, at
-- https://fpgasoftware.intel.com/eula.
-- VENDOR "Altera"
-- PROGRAM "Quartus Prime"
-- VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
-- DATE "02/18/2023 15:07:05"
--
-- Device: Altera EP4CE115F29C7 Package FBGA780
--
--
-- This VHDL file should be used for ModelSim-Altera (VHDL) only
--
LIBRARY CYCLONEIVE;
LIBRARY IEEE;
USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY hard_block IS
PORT (
devoe : IN std_logic;
devclrn : IN std_logic;
devpor : IN std_logic
);
END hard_block;
-- Design Ports Information
-- ~ALTERA_ASDO_DATA1~ => Location: PIN_F4, I/O Standard: 2.5 V, Current Strength: Default
-- ~ALTERA_FLASH_nCE_nCSO~ => Location: PIN_E2, I/O Standard: 2.5 V, Current Strength: Default
-- ~ALTERA_DCLK~ => Location: PIN_P3, I/O Standard: 2.5 V, Current Strength: Default
-- ~ALTERA_DATA0~ => Location: PIN_N7, I/O Standard: 2.5 V, Current Strength: Default
-- ~ALTERA_nCEO~ => Location: PIN_P28, I/O Standard: 2.5 V, Current Strength: 8mA
ARCHITECTURE structure OF hard_block IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL unknown : std_logic := 'X';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL \~ALTERA_ASDO_DATA1~~padout\ : std_logic;
SIGNAL \~ALTERA_FLASH_nCE_nCSO~~padout\ : std_logic;
SIGNAL \~ALTERA_DATA0~~padout\ : std_logic;
SIGNAL \~ALTERA_ASDO_DATA1~~ibuf_o\ : std_logic;
SIGNAL \~ALTERA_FLASH_nCE_nCSO~~ibuf_o\ : std_logic;
SIGNAL \~ALTERA_DATA0~~ibuf_o\ : std_logic;
BEGIN
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;
END structure;
LIBRARY CYCLONEIVE;
LIBRARY IEEE;
USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY GateDemo IS
PORT (
LEDR : OUT std_logic_vector(0 DOWNTO 0);
SW : IN std_logic_vector(1 DOWNTO 0)
);
END GateDemo;
-- Design Ports Information
-- LEDR[0] => Location: PIN_G19, I/O Standard: 2.5 V, Current Strength: Default
-- SW[1] => Location: PIN_AC28, I/O Standard: 2.5 V, Current Strength: Default
-- SW[0] => Location: PIN_AB28, I/O Standard: 2.5 V, Current Strength: Default
ARCHITECTURE structure OF GateDemo IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL unknown : std_logic := 'X';
SIGNAL devoe : std_logic := '1';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_LEDR : std_logic_vector(0 DOWNTO 0);
SIGNAL ww_SW : std_logic_vector(1 DOWNTO 0);
SIGNAL \LEDR[0]~output_o\ : std_logic;
SIGNAL \SW[1]~input_o\ : std_logic;
SIGNAL \SW[0]~input_o\ : std_logic;
SIGNAL \inst~combout\ : std_logic;
COMPONENT hard_block
PORT (
devoe : IN std_logic;
devclrn : IN std_logic;
devpor : IN std_logic);
END COMPONENT;
BEGIN
LEDR <= ww_LEDR;
ww_SW <= SW;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;
auto_generated_inst : hard_block
PORT MAP (
devoe => ww_devoe,
devclrn => ww_devclrn,
devpor => ww_devpor);
-- Location: IOOBUF_X69_Y73_N16
\LEDR[0]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false")
-- pragma translate_on
PORT MAP (
i => \inst~combout\,
devoe => ww_devoe,
o => \LEDR[0]~output_o\);
-- Location: IOIBUF_X115_Y14_N1
\SW[1]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_SW(1),
o => \SW[1]~input_o\);
-- Location: IOIBUF_X115_Y17_N1
\SW[0]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_SW(0),
o => \SW[0]~input_o\);
-- Location: LCCOMB_X114_Y17_N8
inst : cycloneive_lcell_comb
-- Equation(s):
-- \inst~combout\ = (\SW[1]~input_o\ & \SW[0]~input_o\)
-- pragma translate_off
GENERIC MAP (
lut_mask => "1010101000000000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \SW[1]~input_o\,
datad => \SW[0]~input_o\,
combout => \inst~combout\);
ww_LEDR(0) <= \LEDR[0]~output_o\;
END structure;

9
1ano/2semestre/lsd/aula01/part1/simulation/modelsim/GateDemo_modelsim.xrf Normal file
View File

@ -0,0 +1,9 @@
vendor_name = ModelSim
source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/GateDemo.bdf
source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/GateDemo.vwf
source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part1/db/GateDemo.cbx.xml
design_name = hard_block
design_name = GateDemo
instance = comp, \LEDR[0]~output\, LEDR[0]~output, GateDemo, 1
instance = comp, \SW[1]~input\, SW[1]~input, GateDemo, 1
instance = comp, \SW[0]~input\, SW[0]~input, GateDemo, 1

17
1ano/2semestre/lsd/aula01/part1/simulation/qsim/GateDemo.do Normal file
View File

@ -0,0 +1,17 @@
onerror {exit -code 1}
vlib work
vcom -work work GateDemo.vho
vcom -work work GateDemo.vwf.vht
vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.GateDemo_vhd_vec_tst
vcd file -direction GateDemo.msim.vcd
vcd add -internal GateDemo_vhd_vec_tst/*
vcd add -internal GateDemo_vhd_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f

148
1ano/2semestre/lsd/aula01/part1/simulation/qsim/GateDemo.msim.vcd Normal file
View File

@ -0,0 +1,148 @@
$comment
File created using the following command:
vcd file GateDemo.msim.vcd -direction
$end
$date
Sat Feb 18 14:55:14 2023
$end
$version
ModelSim Version 2020.1
$end
$timescale
1ps
$end
$scope module gatedemo_vhd_vec_tst $end
$var wire 1 ! LEDR [0] $end
$var wire 1 " SW [1] $end
$var wire 1 # SW [0] $end
$scope module i1 $end
$var wire 1 $ gnd $end
$var wire 1 % vcc $end
$var wire 1 & unknown $end
$var wire 1 ' devoe $end
$var wire 1 ( devclrn $end
$var wire 1 ) devpor $end
$var wire 1 * ww_devoe $end
$var wire 1 + ww_devclrn $end
$var wire 1 , ww_devpor $end
$var wire 1 - ww_LEDR [0] $end
$var wire 1 . ww_SW [1] $end
$var wire 1 / ww_SW [0] $end
$var wire 1 0 \LEDR[0]~output_o\ $end
$var wire 1 1 \SW[1]~input_o\ $end
$var wire 1 2 \SW[0]~input_o\ $end
$var wire 1 3 \inst~combout\ $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
0$
1%
x&
1'
1(
1)
1*
1+
1,
00
01
02
03
0"
0#
0-
0.
0/
0!
$end
#80000
1#
1/
12
#180000
0#
0/
02
#240000
1"
1.
11
#340000
0"
0.
01
#420000
1#
1/
12
#480000
1"
1.
11
13
10
1-
1!
#560000
0"
0.
01
03
00
0-
0!
#620000
0#
0/
02
#660000
1#
1"
1/
1.
11
12
13
10
1-
1!
#720000
0#
0"
0/
0.
01
02
03
00
0-
0!
#760000
1"
1.
11
#800000
1#
1/
12
13
10
1-
1!
#900000
0#
0/
02
03
00
0-
0!
#960000
0"
0.
01
#1000000

1
1ano/2semestre/lsd/aula01/part1/simulation/qsim/GateDemo.sft Normal file
View File

@ -0,0 +1 @@
set tool_name "ModelSim-Altera (VHDL)"

115
1ano/2semestre/lsd/aula01/part1/simulation/qsim/GateDemo.vho Normal file
View File

@ -0,0 +1,115 @@
-- Copyright (C) 2020 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details, at
-- https://fpgasoftware.intel.com/eula.
-- VENDOR "Altera"
-- PROGRAM "Quartus Prime"
-- VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
-- DATE "02/18/2023 14:55:13"
--
-- Device: Altera EP4CE115F29C7 Package FBGA780
--
--
-- This VHDL file should be used for ModelSim-Altera (VHDL) only
--
LIBRARY CYCLONEIVE;
LIBRARY IEEE;
USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY GateDemo IS
PORT (
LEDR : OUT std_logic_vector(0 DOWNTO 0);
SW : IN std_logic_vector(1 DOWNTO 0)
);
END GateDemo;
ARCHITECTURE structure OF GateDemo IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL unknown : std_logic := 'X';
SIGNAL devoe : std_logic := '1';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_LEDR : std_logic_vector(0 DOWNTO 0);
SIGNAL ww_SW : std_logic_vector(1 DOWNTO 0);
SIGNAL \LEDR[0]~output_o\ : std_logic;
SIGNAL \SW[1]~input_o\ : std_logic;
SIGNAL \SW[0]~input_o\ : std_logic;
SIGNAL \inst~combout\ : std_logic;
BEGIN
LEDR <= ww_LEDR;
ww_SW <= SW;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;
\LEDR[0]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false")
-- pragma translate_on
PORT MAP (
i => \inst~combout\,
devoe => ww_devoe,
o => \LEDR[0]~output_o\);
\SW[1]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_SW(1),
o => \SW[1]~input_o\);
\SW[0]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_SW(0),
o => \SW[0]~input_o\);
inst : cycloneive_lcell_comb
-- Equation(s):
-- \inst~combout\ = (\SW[1]~input_o\ & \SW[0]~input_o\)
-- pragma translate_off
GENERIC MAP (
lut_mask => "1000100010001000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \SW[1]~input_o\,
datab => \SW[0]~input_o\,
combout => \inst~combout\);
ww_LEDR(0) <= \LEDR[0]~output_o\;
END structure;

Some files were not shown because too many files have changed in this diff Show More