From 4f5615bf9c4f32d484c28772785d8459fe10a24f Mon Sep 17 00:00:00 2001 From: TiagoRG <35657250+TiagoRG@users.noreply.github.com> Date: Tue, 7 Mar 2023 21:00:18 +0000 Subject: [PATCH] [LSD] pratica01 part2 block diagram version of NAND2Gate --- .../lsd/pratica01/part2/AND2Gate.bsf | 51 ++++++ .../lsd/pratica01/part2/AND2Gate.qsf | 9 +- .../lsd/pratica01/part2/AND2Gate.qws | Bin 1205 -> 1830 bytes .../lsd/pratica01/part2/NAND2Block.bdf | 137 ++++++++++++++++ .../2semestre/lsd/pratica01/part2/NOTGate.bsf | 44 ++++++ .../lsd/pratica01/part2/db/AND2Gate.asm.qmsg | 14 +- .../lsd/pratica01/part2/db/AND2Gate.asm.rdb | Bin 827 -> 827 bytes .../lsd/pratica01/part2/db/AND2Gate.cmp.bpm | Bin 586 -> 588 bytes .../lsd/pratica01/part2/db/AND2Gate.cmp.cdb | Bin 3794 -> 3797 bytes .../lsd/pratica01/part2/db/AND2Gate.cmp.hdb | Bin 26795 -> 26897 bytes .../lsd/pratica01/part2/db/AND2Gate.cmp.rdb | Bin 30759 -> 30845 bytes ...ve_io_sim_cache.45um_ff_1200mv_0c_fast.hsd | Bin 746429 -> 746768 bytes ...e_io_sim_cache.45um_ii_1200mv_85c_slow.hsd | Bin 749512 -> 750052 bytes .../lsd/pratica01/part2/db/AND2Gate.db_info | 2 +- .../lsd/pratica01/part2/db/AND2Gate.eda.qmsg | 12 +- .../lsd/pratica01/part2/db/AND2Gate.fit.qmsg | 96 ++++++------ .../lsd/pratica01/part2/db/AND2Gate.hier_info | 4 +- .../lsd/pratica01/part2/db/AND2Gate.map.bpm | Bin 566 -> 569 bytes .../lsd/pratica01/part2/db/AND2Gate.map.cdb | Bin 2501 -> 2502 bytes .../lsd/pratica01/part2/db/AND2Gate.map.hdb | Bin 25923 -> 26005 bytes .../lsd/pratica01/part2/db/AND2Gate.map.qmsg | 39 ++--- .../lsd/pratica01/part2/db/AND2Gate.map.rdb | Bin 1336 -> 1337 bytes .../pratica01/part2/db/AND2Gate.map_bb.cdb | Bin 2001 -> 2002 bytes .../pratica01/part2/db/AND2Gate.map_bb.hdb | Bin 25067 -> 25204 bytes .../pratica01/part2/db/AND2Gate.pre_map.hdb | Bin 25439 -> 25401 bytes .../lsd/pratica01/part2/db/AND2Gate.rtlv.hdb | Bin 25376 -> 25337 bytes .../pratica01/part2/db/AND2Gate.rtlv_sg.cdb | Bin 1486 -> 1477 bytes .../part2/db/AND2Gate.rtlv_sg_swap.cdb | Bin 684 -> 688 bytes .../lsd/pratica01/part2/db/AND2Gate.sta.qmsg | 98 ++++++------ .../db/AND2Gate.tiscmp.fast_1200mv_0c.ddb | Bin 107780 -> 107778 bytes .../db/AND2Gate.tiscmp.slow_1200mv_0c.ddb | Bin 108225 -> 108236 bytes .../db/AND2Gate.tiscmp.slow_1200mv_85c.ddb | Bin 107963 -> 107945 bytes .../lsd/pratica01/part2/db/AND2Gate.tmw_info | 12 +- .../pratica01/part2/db/prev_cmp_VHDLDemo.qmsg | 148 ++---------------- .../AND2Gate.root_partition.cmp.cdb | Bin 2862 -> 2864 bytes .../AND2Gate.root_partition.cmp.hdb | Bin 25427 -> 25504 bytes .../AND2Gate.root_partition.map.cdb | Bin 2309 -> 2311 bytes .../AND2Gate.root_partition.map.dpi | Bin 931 -> 933 bytes .../AND2Gate.root_partition.map.hbdb.cdb | Bin 1597 -> 1598 bytes .../AND2Gate.root_partition.map.hbdb.hdb | Bin 24768 -> 24835 bytes .../AND2Gate.root_partition.map.hdb | Bin 24777 -> 24908 bytes .../compiled_partitions/AND2Gate.rrp.hdb | Bin 26691 -> 26807 bytes .../part2/output_files/AND2Gate.asm.rpt | 28 ++-- .../part2/output_files/AND2Gate.done | 2 +- .../part2/output_files/AND2Gate.eda.rpt | 26 +-- .../part2/output_files/AND2Gate.fit.rpt | 24 +-- .../part2/output_files/AND2Gate.fit.summary | 2 +- .../part2/output_files/AND2Gate.flow.rpt | 22 +-- .../pratica01/part2/output_files/AND2Gate.jdi | 2 +- .../part2/output_files/AND2Gate.map.rpt | 64 ++++---- .../part2/output_files/AND2Gate.map.summary | 2 +- .../pratica01/part2/output_files/AND2Gate.sof | Bin 3541726 -> 3541726 bytes .../part2/output_files/AND2Gate.sta.rpt | 12 +- .../part2/simulation/modelsim/AND2Gate.vho | 4 +- .../simulation/modelsim/AND2Gate_modelsim.xrf | 13 +- 55 files changed, 493 insertions(+), 374 deletions(-) create mode 100644 1ano/2semestre/lsd/pratica01/part2/AND2Gate.bsf create mode 100644 1ano/2semestre/lsd/pratica01/part2/NAND2Block.bdf create mode 100644 1ano/2semestre/lsd/pratica01/part2/NOTGate.bsf diff --git a/1ano/2semestre/lsd/pratica01/part2/AND2Gate.bsf b/1ano/2semestre/lsd/pratica01/part2/AND2Gate.bsf new file mode 100644 index 0000000..c472162 --- /dev/null +++ b/1ano/2semestre/lsd/pratica01/part2/AND2Gate.bsf @@ -0,0 +1,51 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 16 16 176 96) + (text "AND2Gate" (rect 5 0 51 12)(font "Arial" )) + (text "inst" (rect 8 64 20 76)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "inPort0" (rect 0 0 27 12)(font "Arial" )) + (text "inPort0" (rect 21 27 48 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 0 48) + (input) + (text "inPort1" (rect 0 0 25 12)(font "Arial" )) + (text "inPort1" (rect 21 43 46 55)(font "Arial" )) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) + (port + (pt 160 32) + (output) + (text "outPort" (rect 0 0 28 12)(font "Arial" )) + (text "outPort" (rect 111 27 139 39)(font "Arial" )) + (line (pt 160 32)(pt 144 32)(line_width 1)) + ) + (drawing + (rectangle (rect 16 16 144 64)(line_width 1)) + ) +) diff --git a/1ano/2semestre/lsd/pratica01/part2/AND2Gate.qsf b/1ano/2semestre/lsd/pratica01/part2/AND2Gate.qsf index c93cb12..6f920ee 100644 --- a/1ano/2semestre/lsd/pratica01/part2/AND2Gate.qsf +++ b/1ano/2semestre/lsd/pratica01/part2/AND2Gate.qsf @@ -55,9 +55,6 @@ set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_ set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan -set_global_assignment -name VHDL_FILE AND2Gate.vhd -set_global_assignment -name VECTOR_WAVEFORM_FILE AND2Gate.vwf -set_global_assignment -name VHDL_FILE GateDemo.vhd set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top @@ -580,6 +577,12 @@ set_location_assignment PIN_H14 -to EX_IO[3] set_location_assignment PIN_F14 -to EX_IO[4] set_location_assignment PIN_E10 -to EX_IO[5] set_location_assignment PIN_D9 -to EX_IO[6] +set_global_assignment -name BDF_FILE NAND2Block.bdf +set_global_assignment -name VHDL_FILE AND2Gate.vhd +set_global_assignment -name VECTOR_WAVEFORM_FILE AND2Gate.vwf +set_global_assignment -name VHDL_FILE GateDemo.vhd set_global_assignment -name VHDL_FILE NOTGate.vhd set_global_assignment -name VHDL_FILE NAND2Gate.vhd +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/1ano/2semestre/lsd/pratica01/part2/AND2Gate.qws b/1ano/2semestre/lsd/pratica01/part2/AND2Gate.qws index e35d54ecfb4f192c6125947d0c9f6f4e8195ab56..1aadd204d5a8a47ff374d9df7f3bb2e48de53b87 100644 GIT binary patch delta 416 zcmaKoze>bF5XQevQYgZKja;D|*lHw^(|Bm3p4f=*kUtv`1)CIt$X#Raky`8y6f8u1 z2A{xMu=f!p{`M3F3wM~=`SZ=}xAQbTZe1-IZ?xPQ%sTwwRH&5X zqX#-yL?!_f$!c9ah1dj4iWegVl@Ls+E*cVjNzT2&%#7Rl7tCvGpT3Go{fE1IvoIvb z2^z_~O5Si1e#dp?of%uddz-VCe6FSe7j(hd$DVJEDe9YGZa~fPOn51VpXJpOz9E_+ z_J?PTmrhu@s$=PXm4Ys@YhVk|j_1F-F#yah1~$^i==sI?^|jfWY5(rAelv@$DeW=w WNEIF4ZXE?>XN(77@6xq${=}a&$48a` delta 167 zcmZ3+x0Q2(HY4Li9eIBy1_lNnhH8dnhC~Kq1`7sLh7=$+XV3-mO@N{xmLU+P05M3+ zfWZ=|N*72QFc<-GB10Mwg47xVX`_w1_A<)u0-Cvsfq~VMfq|(Lh*9{Hr!ZA8W=`g1 lwie6;s!L}0|NlP&1B(ezUFPHj){~Q!SmrQhOy18T1^`+gAa(!% diff --git a/1ano/2semestre/lsd/pratica01/part2/NAND2Block.bdf b/1ano/2semestre/lsd/pratica01/part2/NAND2Block.bdf new file mode 100644 index 0000000..ffdb3da --- /dev/null +++ b/1ano/2semestre/lsd/pratica01/part2/NAND2Block.bdf @@ -0,0 +1,137 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ +(header "graphic" (version "1.4")) +(pin + (input) + (rect 200 232 368 248) + (text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6))) + (text "inPort0" (rect 5 0 44 13)(font "Intel Clear" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6))) +) +(pin + (input) + (rect 200 248 368 264) + (text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6))) + (text "inPort1" (rect 5 0 43 13)(font "Intel Clear" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6))) +) +(pin + (output) + (rect 704 232 880 248) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "outPort" (rect 90 0 127 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) +) +(symbol + (rect 376 208 536 288) + (text "AND2Gate" (rect 5 0 60 11)(font "Arial" )) + (text "inst" (rect 8 64 26 75)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "inPort0" (rect 0 0 36 11)(font "Arial" )) + (text "inPort0" (rect 21 27 57 38)(font "Arial" )) + (line (pt 0 32)(pt 16 32)) + ) + (port + (pt 0 48) + (input) + (text "inPort1" (rect 0 0 36 11)(font "Arial" )) + (text "inPort1" (rect 21 43 57 54)(font "Arial" )) + (line (pt 0 48)(pt 16 48)) + ) + (port + (pt 160 32) + (output) + (text "outPort" (rect 0 0 37 11)(font "Arial" )) + (text "outPort" (rect 108 27 145 38)(font "Arial" )) + (line (pt 160 32)(pt 144 32)) + ) + (drawing + (rectangle (rect 16 16 144 64)) + ) +) +(symbol + (rect 544 208 696 288) + (text "NOTGate" (rect 5 0 53 11)(font "Arial" )) + (text "inst1" (rect 8 64 32 77)(font "Intel Clear" )) + (port + (pt 0 32) + (input) + (text "inPort" (rect 0 0 30 11)(font "Arial" )) + (text "inPort" (rect 21 27 51 38)(font "Arial" )) + (line (pt 0 32)(pt 16 32)) + ) + (port + (pt 152 32) + (output) + (text "outPort" (rect 0 0 37 11)(font "Arial" )) + (text "outPort" (rect 100 27 137 38)(font "Arial" )) + (line (pt 152 32)(pt 136 32)) + ) + (drawing + (rectangle (rect 16 16 136 64)) + ) +) +(connector + (pt 704 240) + (pt 696 240) +) +(connector + (pt 544 240) + (pt 536 240) +) +(connector + (pt 368 240) + (pt 376 240) +) +(connector + (pt 368 256) + (pt 376 256) +) diff --git a/1ano/2semestre/lsd/pratica01/part2/NOTGate.bsf b/1ano/2semestre/lsd/pratica01/part2/NOTGate.bsf new file mode 100644 index 0000000..4deb738 --- /dev/null +++ b/1ano/2semestre/lsd/pratica01/part2/NOTGate.bsf @@ -0,0 +1,44 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 16 16 168 96) + (text "NOTGate" (rect 5 0 43 12)(font "Arial" )) + (text "inst" (rect 8 64 20 76)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "inPort" (rect 0 0 22 12)(font "Arial" )) + (text "inPort" (rect 21 27 43 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 152 32) + (output) + (text "outPort" (rect 0 0 28 12)(font "Arial" )) + (text "outPort" (rect 103 27 131 39)(font "Arial" )) + (line (pt 152 32)(pt 136 32)(line_width 1)) + ) + (drawing + (rectangle (rect 16 16 136 64)(line_width 1)) + ) +) diff --git a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.asm.qmsg b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.asm.qmsg index be37ca8..7b8251a 100644 --- a/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.asm.qmsg +++ b/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.asm.qmsg @@ -1,7 +1,7 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1677672678699 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1677672678700 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 1 12:11:18 2023 " "Processing started: Wed Mar 1 12:11:18 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1677672678700 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1677672678700 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off VHDLDemo -c AND2Gate " "Command: quartus_asm --read_settings_files=off --write_settings_files=off VHDLDemo -c AND2Gate" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1677672678700 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. 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