From 3ea15be20e87e8f4b9d7d5d94bd434429e1e5211 Mon Sep 17 00:00:00 2001 From: TiagoRG <35657250+TiagoRG@users.noreply.github.com> Date: Tue, 7 Mar 2023 20:59:42 +0000 Subject: [PATCH] [LSD] pratica01 part3 simulation waveform created --- .../lsd/pratica01/part3/LogicTop.qsf | 3 +- .../lsd/pratica01/part3/LogicTop.qws | Bin 1850 -> 1255 bytes .../lsd/pratica01/part3/LogicUnit.vwf | 368 +++++++++++++ .../lsd/pratica01/part3/db/LogicTop.cmp.hdb | Bin 32571 -> 32665 bytes .../lsd/pratica01/part3/db/LogicTop.cmp.rdb | Bin 37672 -> 37854 bytes .../lsd/pratica01/part3/db/LogicTop.db_info | 2 +- .../lsd/pratica01/part3/db/LogicTop.eda.qmsg | 12 +- .../part3/db/LogicTop.smart_action.txt | 2 +- .../lsd/pratica01/part3/db/LogicTop.tmw_info | 11 +- .../part3/output_files/LogicTop.eda.rpt | 44 +- .../part3/output_files/LogicTop.flow.rpt | 12 +- .../part3/simulation/qsim/LogicDemo.do | 17 + .../part3/simulation/qsim/LogicDemo.msim.vcd | 180 +++++++ .../qsim/LogicDemo_20230307204548.sim.vwf | 365 +++++++++++++ .../part3/simulation/qsim/LogicTop.sft | 1 + .../part3/simulation/qsim/LogicTop.vho | 493 ++++++++++++++++++ .../simulation/qsim/LogicTop_modelsim.xrf | 21 + .../part3/simulation/qsim/LogicUnit.vwf.vht | 75 +++ .../part3/simulation/qsim/transcript | 46 ++ .../part3/simulation/qsim/vwf_sim_transcript | 66 +++ .../part3/simulation/qsim/work/_info | 150 ++++++ .../part3/simulation/qsim/work/_lib.qdb | Bin 0 -> 49152 bytes .../part3/simulation/qsim/work/_lib1_0.qdb | Bin 0 -> 32768 bytes .../part3/simulation/qsim/work/_lib1_0.qpg | Bin 0 -> 147456 bytes .../part3/simulation/qsim/work/_lib1_0.qtl | Bin 0 -> 39117 bytes .../part3/simulation/qsim/work/_vmake | 4 + 26 files changed, 1838 insertions(+), 34 deletions(-) create mode 100644 1ano/2semestre/lsd/pratica01/part3/LogicUnit.vwf create mode 100644 1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicDemo.do create mode 100644 1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicDemo.msim.vcd create mode 100644 1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicDemo_20230307204548.sim.vwf create mode 100644 1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicTop.sft create mode 100644 1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicTop.vho create mode 100644 1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicTop_modelsim.xrf create mode 100644 1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicUnit.vwf.vht create mode 100644 1ano/2semestre/lsd/pratica01/part3/simulation/qsim/transcript create mode 100644 1ano/2semestre/lsd/pratica01/part3/simulation/qsim/vwf_sim_transcript create mode 100644 1ano/2semestre/lsd/pratica01/part3/simulation/qsim/work/_info create mode 100644 1ano/2semestre/lsd/pratica01/part3/simulation/qsim/work/_lib.qdb create mode 100644 1ano/2semestre/lsd/pratica01/part3/simulation/qsim/work/_lib1_0.qdb create mode 100644 1ano/2semestre/lsd/pratica01/part3/simulation/qsim/work/_lib1_0.qpg create mode 100644 1ano/2semestre/lsd/pratica01/part3/simulation/qsim/work/_lib1_0.qtl create mode 100644 1ano/2semestre/lsd/pratica01/part3/simulation/qsim/work/_vmake diff --git a/1ano/2semestre/lsd/pratica01/part3/LogicTop.qsf b/1ano/2semestre/lsd/pratica01/part3/LogicTop.qsf index 6de59e9..9ed51dc 100644 --- a/1ano/2semestre/lsd/pratica01/part3/LogicTop.qsf +++ b/1ano/2semestre/lsd/pratica01/part3/LogicTop.qsf @@ -1177,4 +1177,5 @@ set_location_assignment PIN_E10 -to EX_IO[5] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[5] set_location_assignment PIN_D9 -to EX_IO[6] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[6] -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name VECTOR_WAVEFORM_FILE LogicUnit.vwf \ No newline at end of file diff --git a/1ano/2semestre/lsd/pratica01/part3/LogicTop.qws b/1ano/2semestre/lsd/pratica01/part3/LogicTop.qws index 0d675774a1a840f6368cb94973e25599a45a3126..f4fc4a793976223fdc3b15c4edd1b7f6e50395dc 100644 GIT binary patch delta 95 zcmdnR_ndQrHY3wyUS_$84e~(7UZ&>Bd93Fr^Rpb9EXOW0`7KK$8&d@X1LKm(j*KTK j+p?82I#14ENmOCl#lXO@jDdmGl7WG#6^POJKv@O=8Xy*Y delta 345 zcmaFPxr=XtwmCBc1A`GmK0_%(2}1#xjAuw=$YjW2NM$Hy&}Z-g%B2JO$qXStRsn+^ zkd?xaHc`j69;DTWp&F>r5U9lxXiOpyr!wd=7yw}sP?;`J#t=vw0a=M)F%SzR3xdf& zoC2nefNUd%TGE`N408)3BLf3tJW%t0AZGXrA{ZE0IvE(4ZckQZKFP>9c`u{QWEG|W zwg3PBe*@wlK +quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off LogicDemo -c LogicTop --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/LogicUnit.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicUnit.vwf.vht" +quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off LogicDemo -c LogicTop --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/LogicUnit.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicUnit.vwf.vht" +quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/" LogicDemo -c LogicTop +quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/" LogicDemo -c LogicTop +onerror {exit -code 1} +vlib work +vcom -work work LogicTop.vho +vcom -work work LogicUnit.vwf.vht +vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.LogicTop_vhd_vec_tst +vcd file -direction LogicDemo.msim.vcd +vcd add -internal LogicTop_vhd_vec_tst/* +vcd add -internal LogicTop_vhd_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f + +onerror {exit -code 1} +vlib work +vcom -work work LogicTop.vho +vcom -work work LogicUnit.vwf.vht +vsim -novopt -c -t 1ps -sdfmax LogicTop_vhd_vec_tst/i1=LogicTop_vhd.sdo -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.LogicTop_vhd_vec_tst +vcd file -direction LogicDemo.msim.vcd +vcd add -internal LogicTop_vhd_vec_tst/* +vcd add -internal LogicTop_vhd_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f + +vhdl +*/ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("LEDR") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 6; + LSB_INDEX = 0; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("LEDR[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("SW") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 2; + LSB_INDEX = 0; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("SW[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +TRANSITION_LIST("LEDR[5]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDR[4]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDR[3]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDR[2]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDR[1]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDR[0]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("SW[1]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 400.0; + LEVEL 1 FOR 400.0; + } + LEVEL 0 FOR 200.0; + } +} + +TRANSITION_LIST("SW[0]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 2; + LEVEL 0 FOR 200.0; + LEVEL 1 FOR 200.0; + } + LEVEL 0 FOR 200.0; + } +} + +DISPLAY_LINE +{ + CHANNEL = "SW"; + EXPAND_STATUS = EXPANDED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; + CHILDREN = 1, 2; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR"; + EXPAND_STATUS = EXPANDED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 0; + CHILDREN = 4, 5, 6, 7, 8, 9; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 1; + PARENT = 3; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 1; + PARENT = 3; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 6; + TREE_LEVEL = 1; + PARENT = 3; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 7; + TREE_LEVEL = 1; + PARENT = 3; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 8; + TREE_LEVEL = 1; + PARENT = 3; +} + +DISPLAY_LINE +{ + CHANNEL = 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Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1678221946861 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "LogicTop.vho /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim// simulation " "Generated file LogicTop.vho in folder \"/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim//\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1678221946897 ""} +{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "613 " "Peak virtual memory: 613 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678221946911 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 7 20:45:46 2023 " "Processing ended: Tue Mar 7 20:45:46 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678221946911 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678221946911 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678221946911 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1678221946911 ""} diff --git a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.smart_action.txt b/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.smart_action.txt index c8e8a13..11b531f 100644 --- a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.smart_action.txt +++ b/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.smart_action.txt @@ -1 +1 @@ -DONE +SOURCE diff --git a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.tmw_info b/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.tmw_info index cc89dbf..1bd50f7 100644 --- a/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.tmw_info +++ b/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.tmw_info @@ -1,7 +1,4 @@ -start_full_compilation:s:00:00:18 -start_analysis_synthesis:s:00:00:06-start_full_compilation -start_analysis_elaboration:s-start_full_compilation -start_fitter:s:00:00:07-start_full_compilation -start_assembler:s:00:00:03-start_full_compilation -start_timing_analyzer:s:00:00:01-start_full_compilation -start_eda_netlist_writer:s:00:00:01-start_full_compilation +start_full_compilation:s +start_assembler:s-start_full_compilation +start_timing_analyzer:s-start_full_compilation +start_eda_netlist_writer:s-start_full_compilation diff --git a/1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.eda.rpt b/1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.eda.rpt index 8788194..c5b2604 100644 --- a/1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.eda.rpt +++ b/1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.eda.rpt @@ -1,5 +1,5 @@ EDA Netlist Writer report for LogicTop -Mon Mar 6 12:05:23 2023 +Tue Mar 7 20:45:46 2023 Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition @@ -37,7 +37,7 @@ https://fpgasoftware.intel.com/eula. +-------------------------------------------------------------------+ ; EDA Netlist Writer Summary ; +---------------------------+---------------------------------------+ -; EDA Netlist Writer Status ; Successful - Mon Mar 6 12:05:23 2023 ; +; EDA Netlist Writer Status ; Successful - Tue Mar 7 20:45:46 2023 ; ; Revision Name ; LogicTop ; ; Top-level Entity Name ; LogicTop ; ; Family ; Cyclone IV E ; @@ -66,13 +66,13 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------------------------------------------+------------------------+ -+------------------------------------------------------------------------------------------------------+ -; Simulation Generated Files ; -+------------------------------------------------------------------------------------------------------+ -; Generated Files ; -+------------------------------------------------------------------------------------------------------+ -; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/modelsim/LogicTop.vho ; -+------------------------------------------------------------------------------------------------------+ ++---------------------------------------------------------------------------------------------------+ +; Simulation Generated Files ; ++---------------------------------------------------------------------------------------------------+ +; Generated Files ; ++---------------------------------------------------------------------------------------------------+ +; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim//LogicTop.vho ; ++---------------------------------------------------------------------------------------------------+ +-----------------------------+ @@ -81,14 +81,28 @@ https://fpgasoftware.intel.com/eula. Info: ******************************************************************* Info: Running Quartus Prime EDA Netlist Writer Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition - Info: Processing started: Mon Mar 6 12:05:22 2023 -Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off LogicDemo -c LogicTop + Info: Copyright (C) 2020 Intel Corporation. All rights reserved. + Info: Your use of Intel Corporation's design tools, logic functions + Info: and other software and tools, and any partner logic + Info: functions, and any output files from any of the foregoing + Info: (including device programming or simulation files), and any + Info: associated documentation or information are expressly subject + Info: to the terms and conditions of the Intel Program License + Info: Subscription Agreement, the Intel Quartus Prime License Agreement, + Info: the Intel FPGA IP License Agreement, or other applicable license + Info: agreement, including, without limitation, that your use is for + Info: the sole purpose of programming logic devices manufactured by + Info: Intel and sold by Intel or its authorized distributors. Please + Info: refer to the applicable agreement for further details, at + Info: https://fpgasoftware.intel.com/eula. + Info: Processing started: Tue Mar 7 20:45:46 2023 +Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/ LogicDemo -c LogicTop Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. -Info (204019): Generated file LogicTop.vho in folder "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file LogicTop.vho in folder "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim//" for EDA simulation tool Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning - Info: Peak virtual memory: 612 megabytes - Info: Processing ended: Mon Mar 6 12:05:23 2023 - Info: Elapsed time: 00:00:01 + Info: Peak virtual memory: 613 megabytes + Info: Processing ended: Tue Mar 7 20:45:46 2023 + Info: Elapsed time: 00:00:00 Info: Total CPU time (on all processors): 00:00:00 diff --git a/1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.flow.rpt b/1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.flow.rpt index 79d0767..213bbbd 100644 --- a/1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.flow.rpt +++ b/1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.flow.rpt @@ -1,5 +1,5 @@ Flow report for LogicTop -Mon Mar 6 12:05:23 2023 +Tue Mar 7 20:45:46 2023 Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition @@ -41,7 +41,7 @@ https://fpgasoftware.intel.com/eula. +----------------------------------------------------------------------------------+ ; Flow Summary ; +------------------------------------+---------------------------------------------+ -; Flow Status ; Successful - Mon Mar 6 12:05:23 2023 ; +; Flow Status ; Successful - Tue Mar 7 20:45:46 2023 ; ; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ; ; Revision Name ; LogicTop ; ; Top-level Entity Name ; LogicTop ; @@ -104,7 +104,9 @@ https://fpgasoftware.intel.com/eula. ; Assembler ; 00:00:01 ; 1.0 ; 366 MB ; 00:00:02 ; ; Timing Analyzer ; 00:00:01 ; 1.0 ; 540 MB ; 00:00:01 ; ; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 612 MB ; 00:00:00 ; -; Total ; 00:00:15 ; -- ; -- ; 00:00:25 ; +; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 609 MB ; 00:00:00 ; +; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 613 MB ; 00:00:00 ; +; Total ; 00:00:16 ; -- ; -- ; 00:00:25 ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ @@ -118,6 +120,8 @@ https://fpgasoftware.intel.com/eula. ; Assembler ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ; ; Timing Analyzer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ; ; EDA Netlist Writer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ; +; EDA Netlist Writer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ; +; EDA Netlist Writer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ; +----------------------+------------------+----------------+------------+----------------+ @@ -129,6 +133,8 @@ quartus_fit --read_settings_files=off --write_settings_files=off LogicDemo -c Lo quartus_asm --read_settings_files=off --write_settings_files=off LogicDemo -c LogicTop quartus_sta LogicDemo -c LogicTop quartus_eda --read_settings_files=off --write_settings_files=off LogicDemo -c LogicTop +quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off LogicDemo -c LogicTop --vector_source=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/LogicUnit.vwf --testbench_file=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicUnit.vwf.vht +quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/ LogicDemo -c LogicTop diff --git a/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicDemo.do b/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicDemo.do new file mode 100644 index 0000000..f2d400f --- /dev/null +++ b/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicDemo.do @@ -0,0 +1,17 @@ +onerror {exit -code 1} +vlib work +vcom -work work LogicTop.vho +vcom -work work LogicUnit.vwf.vht +vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.LogicTop_vhd_vec_tst +vcd file -direction LogicDemo.msim.vcd +vcd add -internal LogicTop_vhd_vec_tst/* +vcd add -internal LogicTop_vhd_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f diff --git a/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicDemo.msim.vcd b/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicDemo.msim.vcd new file mode 100644 index 0000000..e3becc2 --- /dev/null +++ b/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicDemo.msim.vcd @@ -0,0 +1,180 @@ +$comment + File created using the following command: + vcd file LogicDemo.msim.vcd -direction +$end +$date + Tue Mar 7 20:45:48 2023 +$end +$version + ModelSim Version 2020.1 +$end +$timescale + 1ps +$end + +$scope module logictop_vhd_vec_tst $end +$var wire 1 ! LEDR [5] $end +$var wire 1 " LEDR [4] $end +$var wire 1 # LEDR [3] $end +$var wire 1 $ LEDR [2] $end +$var wire 1 % LEDR [1] $end +$var wire 1 & LEDR [0] $end +$var wire 1 ' SW [1] $end +$var wire 1 ( SW [0] $end + +$scope module i1 $end +$var wire 1 ) gnd $end +$var wire 1 * vcc $end +$var wire 1 + unknown $end +$var wire 1 , devoe $end +$var wire 1 - devclrn $end +$var wire 1 . devpor $end +$var wire 1 / ww_devoe $end +$var wire 1 0 ww_devclrn $end +$var wire 1 1 ww_devpor $end +$var wire 1 2 ww_LEDR [5] $end +$var wire 1 3 ww_LEDR [4] $end +$var wire 1 4 ww_LEDR [3] $end +$var wire 1 5 ww_LEDR [2] $end +$var wire 1 6 ww_LEDR [1] $end +$var wire 1 7 ww_LEDR [0] $end +$var wire 1 8 ww_SW [1] $end +$var wire 1 9 ww_SW [0] $end +$var wire 1 : \LEDR[5]~output_o\ $end +$var wire 1 ; \LEDR[4]~output_o\ $end +$var wire 1 < \LEDR[3]~output_o\ $end +$var wire 1 = \LEDR[2]~output_o\ $end +$var wire 1 > \LEDR[1]~output_o\ $end +$var wire 1 ? \LEDR[0]~output_o\ $end +$var wire 1 @ \SW[1]~input_o\ $end +$var wire 1 A \SW[0]~input_o\ $end +$var wire 1 B \inst|norOut~0_combout\ $end +$var wire 1 C \inst|nandOut~0_combout\ $end +$var wire 1 D \inst|xorOut~combout\ $end +$var wire 1 E \ALT_INV_SW[0]~input_o\ $end +$var wire 1 F \inst|ALT_INV_nandOut~0_combout\ $end +$var wire 1 G \inst|ALT_INV_norOut~0_combout\ $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +0) +1* +x+ +1, +1- +1. +1/ +10 +11 +1: +1; +0< +0= +0> +1? +0@ +0A +0B +0C +0D +1E +1F +1G +0' +0( +12 +13 +04 +05 +06 +17 +08 +09 +1! +1" +0# +0$ +0% +1& +$end +#200000 +1( +19 +1A +0E +1B +1D +0G +0? +1< +1= +07 +0: +14 +15 +0& +02 +1$ +1# +0! +#400000 +0( +1' +09 +18 +1@ +0A +1E +1? +17 +1& +#600000 +1( +19 +1A +0E +1C +0D +0F +0? +0< +1> +07 +0; +04 +16 +0& +03 +1% +0# +0" +#800000 +0( +0' +09 +08 +0@ +0A +1E +0B +0C +1F +1G +1? +0> +0= +17 +1: +1; +06 +05 +1& +12 +13 +0% +0$ +1" +1! +#1000000 diff --git a/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicDemo_20230307204548.sim.vwf b/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicDemo_20230307204548.sim.vwf new file mode 100644 index 0000000..7eeca94 --- /dev/null +++ b/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicDemo_20230307204548.sim.vwf @@ -0,0 +1,365 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("LEDR") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 6; + LSB_INDEX = 0; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("LEDR[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("LEDR[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDR"; +} + +SIGNAL("SW") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 2; + LSB_INDEX = 0; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("SW[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +TRANSITION_LIST("LEDR[5]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 1 FOR 200.0; + LEVEL 0 FOR 600.0; + LEVEL 1 FOR 200.0; + } + } +} + +TRANSITION_LIST("LEDR[4]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 1 FOR 600.0; + LEVEL 0 FOR 200.0; + LEVEL 1 FOR 200.0; + } + } +} + +TRANSITION_LIST("LEDR[3]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 200.0; + LEVEL 1 FOR 400.0; + LEVEL 0 FOR 400.0; + } + } +} + +TRANSITION_LIST("LEDR[2]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 200.0; + LEVEL 1 FOR 600.0; + LEVEL 0 FOR 200.0; + } + } +} + +TRANSITION_LIST("LEDR[1]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 600.0; + LEVEL 1 FOR 200.0; + LEVEL 0 FOR 200.0; + } + } +} + +TRANSITION_LIST("LEDR[0]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 1 FOR 200.0; + LEVEL 0 FOR 200.0; + LEVEL 1 FOR 200.0; + LEVEL 0 FOR 200.0; + LEVEL 1 FOR 200.0; + } + } +} + +TRANSITION_LIST("SW[1]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 400.0; + LEVEL 1 FOR 400.0; + LEVEL 0 FOR 200.0; + } + } +} + +TRANSITION_LIST("SW[0]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 200.0; + LEVEL 1 FOR 200.0; + LEVEL 0 FOR 200.0; + LEVEL 1 FOR 200.0; + LEVEL 0 FOR 200.0; + } + } +} + +DISPLAY_LINE +{ + CHANNEL = "SW"; + EXPAND_STATUS = EXPANDED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; + CHILDREN = 1, 2; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR"; + EXPAND_STATUS = EXPANDED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 0; + CHILDREN = 4, 5, 6, 7, 8, 9; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 1; + PARENT = 3; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 1; + PARENT = 3; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 6; + TREE_LEVEL = 1; + PARENT = 3; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 7; + TREE_LEVEL = 1; + PARENT = 3; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 8; + TREE_LEVEL = 1; + PARENT = 3; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 9; + TREE_LEVEL = 1; + PARENT = 3; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicTop.sft b/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicTop.sft new file mode 100644 index 0000000..0c5034b --- /dev/null +++ b/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicTop.sft @@ -0,0 +1 @@ +set tool_name "ModelSim-Altera (VHDL)" diff --git a/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicTop.vho b/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicTop.vho new file mode 100644 index 0000000..884efcf --- /dev/null +++ b/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicTop.vho @@ -0,0 +1,493 @@ +-- Copyright (C) 2020 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions +-- and other software and tools, and any partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License +-- Subscription Agreement, the Intel Quartus Prime License Agreement, +-- the Intel FPGA IP License Agreement, or other applicable license +-- agreement, including, without limitation, that your use is for +-- the sole purpose of programming logic devices manufactured by +-- Intel and sold by Intel or its authorized distributors. Please +-- refer to the applicable agreement for further details, at +-- https://fpgasoftware.intel.com/eula. + +-- VENDOR "Altera" +-- PROGRAM "Quartus Prime" +-- VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" + +-- DATE "03/07/2023 20:45:46" + +-- +-- Device: Altera EP4CE115F29C7 Package FBGA780 +-- + +-- +-- This VHDL file should be used for ModelSim-Altera (VHDL) only +-- + +LIBRARY CYCLONEIVE; +LIBRARY IEEE; +USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL; +USE IEEE.STD_LOGIC_1164.ALL; + +ENTITY hard_block IS + PORT ( + devoe : IN std_logic; + devclrn : IN std_logic; + devpor : IN std_logic + ); +END hard_block; + +-- Design Ports Information +-- AUD_ADCDAT => Location: PIN_D2, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- CLOCK2_50 => Location: PIN_AG14, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- CLOCK3_50 => Location: PIN_AG15, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- CLOCK_50 => Location: PIN_Y2, I/O Standard: 2.5 V, Current Strength: Default +-- ENET0_INT_N => Location: PIN_A21, I/O Standard: 2.5 V, Current Strength: Default +-- ENET0_LINK100 => Location: PIN_C14, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- ENET0_MDIO => Location: PIN_B21, I/O Standard: 2.5 V, Current Strength: Default +-- ENET0_RX_CLK => Location: PIN_A15, I/O Standard: 2.5 V, Current Strength: Default +-- ENET0_RX_COL => Location: PIN_E15, I/O Standard: 2.5 V, Current Strength: Default +-- ENET0_RX_CRS => Location: PIN_D15, I/O Standard: 2.5 V, Current Strength: Default +-- ENET0_RX_DATA[0] => Location: PIN_C16, I/O Standard: 2.5 V, Current Strength: Default +-- ENET0_RX_DATA[1] => Location: PIN_D16, I/O Standard: 2.5 V, Current Strength: Default +-- ENET0_RX_DATA[2] => Location: PIN_D17, I/O Standard: 2.5 V, Current Strength: Default +-- ENET0_RX_DATA[3] => Location: PIN_C15, I/O Standard: 2.5 V, Current Strength: Default +-- ENET0_RX_DV => Location: PIN_C17, I/O Standard: 2.5 V, Current Strength: Default +-- ENET0_RX_ER => Location: PIN_D18, I/O Standard: 2.5 V, Current Strength: Default +-- ENET0_TX_CLK => Location: PIN_B17, I/O Standard: 2.5 V, Current Strength: Default +-- ENET1_INT_N => Location: PIN_D24, I/O Standard: 2.5 V, Current Strength: Default +-- ENET1_LINK100 => Location: PIN_D13, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- ENET1_MDIO => Location: PIN_D25, I/O Standard: 2.5 V, Current Strength: Default +-- ENET1_RX_CLK => Location: PIN_B15, I/O Standard: 2.5 V, Current Strength: Default +-- ENET1_RX_COL => Location: PIN_B22, I/O Standard: 2.5 V, Current Strength: Default +-- ENET1_RX_CRS => Location: PIN_D20, I/O Standard: 2.5 V, Current Strength: Default +-- ENET1_RX_DATA[0] => Location: PIN_B23, I/O Standard: 2.5 V, Current Strength: Default +-- ENET1_RX_DATA[1] => Location: PIN_C21, I/O Standard: 2.5 V, Current Strength: Default +-- ENET1_RX_DATA[2] => Location: PIN_A23, I/O Standard: 2.5 V, Current Strength: Default +-- ENET1_RX_DATA[3] => Location: PIN_D21, I/O Standard: 2.5 V, Current Strength: Default +-- ENET1_RX_DV => Location: PIN_A22, I/O Standard: 2.5 V, Current Strength: Default +-- ENET1_RX_ER => Location: PIN_C24, I/O Standard: 2.5 V, Current Strength: Default +-- ENET1_TX_CLK => Location: PIN_C22, I/O Standard: 2.5 V, Current Strength: Default +-- ENETCLK_25 => Location: PIN_A14, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- FL_RY => Location: PIN_Y1, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- HSMC_CLKIN0 => Location: PIN_AH15, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- IRDA_RXD => Location: PIN_Y15, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- KEY[0] => Location: PIN_M23, I/O Standard: 2.5 V, Current Strength: Default +-- KEY[1] => Location: PIN_M21, I/O Standard: 2.5 V, Current Strength: Default +-- KEY[2] => Location: PIN_N21, I/O Standard: 2.5 V, Current Strength: Default +-- KEY[3] => Location: PIN_R24, I/O Standard: 2.5 V, Current Strength: Default +-- OTG_INT => Location: PIN_D5, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- SD_WP_N => Location: PIN_AF14, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- SMA_CLKIN => Location: PIN_AH14, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- SW[10] => Location: PIN_AC24, I/O Standard: 2.5 V, Current Strength: Default +-- SW[11] => Location: PIN_AB24, I/O Standard: 2.5 V, Current Strength: Default +-- SW[12] => Location: PIN_AB23, I/O Standard: 2.5 V, Current Strength: Default +-- SW[13] => Location: PIN_AA24, I/O Standard: 2.5 V, Current Strength: Default +-- SW[14] => Location: PIN_AA23, I/O Standard: 2.5 V, Current Strength: Default +-- SW[15] => Location: PIN_AA22, I/O Standard: 2.5 V, Current Strength: Default +-- SW[16] => Location: PIN_Y24, I/O Standard: 2.5 V, Current Strength: Default +-- SW[17] => Location: PIN_Y23, I/O Standard: 2.5 V, Current Strength: Default +-- SW[2] => Location: PIN_AC27, I/O Standard: 2.5 V, Current Strength: Default +-- SW[3] => Location: PIN_AD27, I/O Standard: 2.5 V, Current Strength: Default +-- SW[4] => Location: PIN_AB27, I/O Standard: 2.5 V, Current Strength: Default +-- SW[5] => Location: PIN_AC26, I/O Standard: 2.5 V, Current Strength: Default +-- SW[6] => Location: PIN_AD26, I/O Standard: 2.5 V, Current Strength: Default +-- SW[7] => Location: PIN_AB26, I/O Standard: 2.5 V, Current Strength: Default +-- SW[8] => Location: PIN_AC25, I/O Standard: 2.5 V, Current Strength: Default +-- SW[9] => Location: PIN_AB25, I/O Standard: 2.5 V, Current Strength: Default +-- TD_CLK27 => Location: PIN_B14, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- TD_DATA[0] => Location: PIN_E8, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- TD_DATA[1] => Location: PIN_A7, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- TD_DATA[2] => Location: PIN_D8, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- TD_DATA[3] => Location: PIN_C7, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- TD_DATA[4] => Location: PIN_D7, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- TD_DATA[5] => Location: PIN_D6, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- TD_DATA[6] => Location: PIN_E7, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- TD_DATA[7] => Location: PIN_F7, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- TD_HS => Location: PIN_E5, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- TD_VS => Location: PIN_E4, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- UART_RTS => Location: PIN_J13, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- UART_RXD => Location: PIN_G12, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- ~ALTERA_ASDO_DATA1~ => Location: PIN_F4, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- ~ALTERA_FLASH_nCE_nCSO~ => Location: PIN_E2, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- ~ALTERA_DCLK~ => Location: PIN_P3, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- ~ALTERA_DATA0~ => Location: PIN_N7, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- ~ALTERA_nCEO~ => Location: PIN_P28, I/O Standard: 2.5 V, Current Strength: 8mA + + +ARCHITECTURE structure OF hard_block IS +SIGNAL gnd : std_logic := '0'; +SIGNAL vcc : std_logic := '1'; +SIGNAL unknown : std_logic := 'X'; +SIGNAL ww_devoe : std_logic; +SIGNAL ww_devclrn : std_logic; +SIGNAL ww_devpor : std_logic; +SIGNAL \AUD_ADCDAT~padout\ : std_logic; +SIGNAL \CLOCK2_50~padout\ : std_logic; +SIGNAL \CLOCK3_50~padout\ : std_logic; +SIGNAL \CLOCK_50~padout\ : std_logic; +SIGNAL \ENET0_INT_N~padout\ : std_logic; +SIGNAL \ENET0_LINK100~padout\ : std_logic; +SIGNAL \ENET0_MDIO~padout\ : std_logic; +SIGNAL \ENET0_RX_CLK~padout\ : std_logic; +SIGNAL \ENET0_RX_COL~padout\ : std_logic; +SIGNAL \ENET0_RX_CRS~padout\ : std_logic; +SIGNAL \ENET0_RX_DATA[0]~padout\ : std_logic; +SIGNAL \ENET0_RX_DATA[1]~padout\ : std_logic; +SIGNAL \ENET0_RX_DATA[2]~padout\ : std_logic; +SIGNAL \ENET0_RX_DATA[3]~padout\ : std_logic; +SIGNAL \ENET0_RX_DV~padout\ : std_logic; +SIGNAL \ENET0_RX_ER~padout\ : std_logic; +SIGNAL \ENET0_TX_CLK~padout\ : std_logic; +SIGNAL \ENET1_INT_N~padout\ : std_logic; +SIGNAL \ENET1_LINK100~padout\ : std_logic; +SIGNAL \ENET1_MDIO~padout\ : std_logic; +SIGNAL \ENET1_RX_CLK~padout\ : std_logic; +SIGNAL \ENET1_RX_COL~padout\ : std_logic; +SIGNAL \ENET1_RX_CRS~padout\ : std_logic; +SIGNAL \ENET1_RX_DATA[0]~padout\ : std_logic; +SIGNAL \ENET1_RX_DATA[1]~padout\ : std_logic; +SIGNAL \ENET1_RX_DATA[2]~padout\ : std_logic; +SIGNAL \ENET1_RX_DATA[3]~padout\ : std_logic; +SIGNAL \ENET1_RX_DV~padout\ : std_logic; +SIGNAL \ENET1_RX_ER~padout\ : std_logic; +SIGNAL \ENET1_TX_CLK~padout\ : std_logic; +SIGNAL \ENETCLK_25~padout\ : std_logic; +SIGNAL \FL_RY~padout\ : std_logic; +SIGNAL \HSMC_CLKIN0~padout\ : std_logic; +SIGNAL \IRDA_RXD~padout\ : std_logic; +SIGNAL \KEY[0]~padout\ : std_logic; +SIGNAL \KEY[1]~padout\ : std_logic; +SIGNAL \KEY[2]~padout\ : std_logic; +SIGNAL \KEY[3]~padout\ : std_logic; +SIGNAL \OTG_INT~padout\ : std_logic; +SIGNAL \SD_WP_N~padout\ : std_logic; +SIGNAL \SMA_CLKIN~padout\ : std_logic; +SIGNAL \TD_CLK27~padout\ : std_logic; +SIGNAL \TD_DATA[0]~padout\ : std_logic; +SIGNAL \TD_DATA[1]~padout\ : std_logic; +SIGNAL \TD_DATA[2]~padout\ : std_logic; +SIGNAL \TD_DATA[3]~padout\ : std_logic; +SIGNAL \TD_DATA[4]~padout\ : std_logic; +SIGNAL \TD_DATA[5]~padout\ : std_logic; +SIGNAL \TD_DATA[6]~padout\ : std_logic; +SIGNAL \TD_DATA[7]~padout\ : std_logic; +SIGNAL \TD_HS~padout\ : std_logic; +SIGNAL \TD_VS~padout\ : std_logic; +SIGNAL \UART_RTS~padout\ : std_logic; +SIGNAL \UART_RXD~padout\ : std_logic; +SIGNAL \~ALTERA_ASDO_DATA1~~padout\ : std_logic; +SIGNAL \~ALTERA_FLASH_nCE_nCSO~~padout\ : std_logic; +SIGNAL \~ALTERA_DATA0~~padout\ : std_logic; +SIGNAL \AUD_ADCDAT~ibuf_o\ : std_logic; +SIGNAL \CLOCK2_50~ibuf_o\ : std_logic; +SIGNAL \CLOCK3_50~ibuf_o\ : std_logic; +SIGNAL \CLOCK_50~ibuf_o\ : std_logic; +SIGNAL \ENET0_INT_N~ibuf_o\ : std_logic; +SIGNAL \ENET0_LINK100~ibuf_o\ : std_logic; +SIGNAL \ENET0_MDIO~ibuf_o\ : std_logic; +SIGNAL \ENET0_RX_CLK~ibuf_o\ : std_logic; +SIGNAL \ENET0_RX_COL~ibuf_o\ : std_logic; +SIGNAL \ENET0_RX_CRS~ibuf_o\ : std_logic; +SIGNAL \ENET0_RX_DATA[0]~ibuf_o\ : std_logic; +SIGNAL \ENET0_RX_DATA[1]~ibuf_o\ : std_logic; +SIGNAL \ENET0_RX_DATA[2]~ibuf_o\ : std_logic; +SIGNAL \ENET0_RX_DATA[3]~ibuf_o\ : std_logic; +SIGNAL \ENET0_RX_DV~ibuf_o\ : std_logic; +SIGNAL \ENET0_RX_ER~ibuf_o\ : std_logic; +SIGNAL \ENET0_TX_CLK~ibuf_o\ : std_logic; +SIGNAL \ENET1_INT_N~ibuf_o\ : std_logic; +SIGNAL \ENET1_LINK100~ibuf_o\ : std_logic; +SIGNAL \ENET1_MDIO~ibuf_o\ : std_logic; +SIGNAL \ENET1_RX_CLK~ibuf_o\ : std_logic; +SIGNAL \ENET1_RX_COL~ibuf_o\ : std_logic; +SIGNAL \ENET1_RX_CRS~ibuf_o\ : std_logic; +SIGNAL \ENET1_RX_DATA[0]~ibuf_o\ : std_logic; +SIGNAL \ENET1_RX_DATA[1]~ibuf_o\ : std_logic; +SIGNAL \ENET1_RX_DATA[2]~ibuf_o\ : std_logic; +SIGNAL \ENET1_RX_DATA[3]~ibuf_o\ : std_logic; +SIGNAL \ENET1_RX_DV~ibuf_o\ : std_logic; +SIGNAL \ENET1_RX_ER~ibuf_o\ : std_logic; +SIGNAL \ENET1_TX_CLK~ibuf_o\ : std_logic; +SIGNAL \ENETCLK_25~ibuf_o\ : std_logic; +SIGNAL \FL_RY~ibuf_o\ : std_logic; +SIGNAL \HSMC_CLKIN0~ibuf_o\ : std_logic; +SIGNAL \IRDA_RXD~ibuf_o\ : std_logic; +SIGNAL \KEY[0]~ibuf_o\ : std_logic; +SIGNAL \KEY[1]~ibuf_o\ : std_logic; +SIGNAL \KEY[2]~ibuf_o\ : std_logic; +SIGNAL \KEY[3]~ibuf_o\ : std_logic; +SIGNAL \OTG_INT~ibuf_o\ : std_logic; +SIGNAL \SD_WP_N~ibuf_o\ : std_logic; +SIGNAL \SMA_CLKIN~ibuf_o\ : std_logic; +SIGNAL \SW[10]~ibuf_o\ : std_logic; +SIGNAL \SW[11]~ibuf_o\ : std_logic; +SIGNAL \SW[12]~ibuf_o\ : std_logic; +SIGNAL \SW[13]~ibuf_o\ : std_logic; +SIGNAL \SW[14]~ibuf_o\ : std_logic; +SIGNAL \SW[15]~ibuf_o\ : std_logic; +SIGNAL \SW[16]~ibuf_o\ : std_logic; +SIGNAL \SW[17]~ibuf_o\ : std_logic; +SIGNAL \SW[2]~ibuf_o\ : std_logic; +SIGNAL \SW[3]~ibuf_o\ : std_logic; +SIGNAL \SW[4]~ibuf_o\ : std_logic; +SIGNAL \SW[5]~ibuf_o\ : std_logic; +SIGNAL \SW[6]~ibuf_o\ : std_logic; +SIGNAL \SW[7]~ibuf_o\ : std_logic; +SIGNAL \SW[8]~ibuf_o\ : std_logic; +SIGNAL \SW[9]~ibuf_o\ : std_logic; +SIGNAL \TD_CLK27~ibuf_o\ : std_logic; +SIGNAL \TD_DATA[0]~ibuf_o\ : std_logic; +SIGNAL \TD_DATA[1]~ibuf_o\ : std_logic; +SIGNAL \TD_DATA[2]~ibuf_o\ : std_logic; +SIGNAL \TD_DATA[3]~ibuf_o\ : std_logic; +SIGNAL \TD_DATA[4]~ibuf_o\ : std_logic; +SIGNAL \TD_DATA[5]~ibuf_o\ : std_logic; +SIGNAL \TD_DATA[6]~ibuf_o\ : std_logic; +SIGNAL \TD_DATA[7]~ibuf_o\ : std_logic; +SIGNAL \TD_HS~ibuf_o\ : std_logic; +SIGNAL \TD_VS~ibuf_o\ : std_logic; +SIGNAL \UART_RTS~ibuf_o\ : std_logic; +SIGNAL \UART_RXD~ibuf_o\ : std_logic; +SIGNAL \~ALTERA_ASDO_DATA1~~ibuf_o\ : std_logic; +SIGNAL \~ALTERA_FLASH_nCE_nCSO~~ibuf_o\ : std_logic; +SIGNAL \~ALTERA_DATA0~~ibuf_o\ : std_logic; +SIGNAL SW : std_logic_vector(1 DOWNTO 0); + +BEGIN + +ww_devoe <= devoe; +ww_devclrn <= devclrn; +ww_devpor <= devpor; +END structure; + + +LIBRARY CYCLONEIVE; +LIBRARY IEEE; +USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL; +USE IEEE.STD_LOGIC_1164.ALL; + +ENTITY LogicTop IS + PORT ( + LEDR : OUT std_logic_vector(5 DOWNTO 0); + SW : IN std_logic_vector(1 DOWNTO 0) + ); +END LogicTop; + +-- Design Ports Information +-- LEDR[5] => Location: PIN_E18, I/O Standard: 2.5 V, Current Strength: Default +-- LEDR[4] => Location: PIN_F18, I/O Standard: 2.5 V, Current Strength: Default +-- LEDR[3] => Location: PIN_F21, I/O Standard: 2.5 V, Current Strength: Default +-- LEDR[2] => Location: PIN_E19, I/O Standard: 2.5 V, Current Strength: Default +-- LEDR[1] => Location: PIN_F19, I/O Standard: 2.5 V, Current Strength: Default +-- LEDR[0] => Location: PIN_G19, I/O Standard: 2.5 V, Current Strength: Default +-- SW[1] => Location: PIN_AC28, I/O Standard: 2.5 V, Current Strength: Default +-- SW[0] => Location: PIN_AB28, I/O Standard: 2.5 V, Current Strength: Default + + +ARCHITECTURE structure OF LogicTop IS +SIGNAL gnd : std_logic := '0'; +SIGNAL vcc : std_logic := '1'; +SIGNAL unknown : std_logic := 'X'; +SIGNAL devoe : std_logic := '1'; +SIGNAL devclrn : std_logic := '1'; +SIGNAL devpor : std_logic := '1'; +SIGNAL ww_devoe : std_logic; +SIGNAL ww_devclrn : std_logic; +SIGNAL ww_devpor : std_logic; +SIGNAL ww_LEDR : std_logic_vector(5 DOWNTO 0); +SIGNAL ww_SW : std_logic_vector(1 DOWNTO 0); +SIGNAL \LEDR[5]~output_o\ : std_logic; +SIGNAL \LEDR[4]~output_o\ : std_logic; +SIGNAL \LEDR[3]~output_o\ : std_logic; +SIGNAL \LEDR[2]~output_o\ : std_logic; +SIGNAL \LEDR[1]~output_o\ : std_logic; +SIGNAL \LEDR[0]~output_o\ : std_logic; +SIGNAL \SW[1]~input_o\ : std_logic; +SIGNAL \SW[0]~input_o\ : std_logic; +SIGNAL \inst|norOut~0_combout\ : std_logic; +SIGNAL \inst|nandOut~0_combout\ : std_logic; +SIGNAL \inst|xorOut~combout\ : std_logic; +SIGNAL \ALT_INV_SW[0]~input_o\ : std_logic; +SIGNAL \inst|ALT_INV_nandOut~0_combout\ : std_logic; +SIGNAL \inst|ALT_INV_norOut~0_combout\ : std_logic; + +COMPONENT hard_block + PORT ( + devoe : IN std_logic; + devclrn : IN std_logic; + devpor : IN std_logic); +END COMPONENT; + +BEGIN + +LEDR <= ww_LEDR; +ww_SW <= SW; +ww_devoe <= devoe; +ww_devclrn <= devclrn; +ww_devpor <= devpor; +\ALT_INV_SW[0]~input_o\ <= NOT \SW[0]~input_o\; +\inst|ALT_INV_nandOut~0_combout\ <= NOT \inst|nandOut~0_combout\; +\inst|ALT_INV_norOut~0_combout\ <= NOT \inst|norOut~0_combout\; +auto_generated_inst : hard_block +PORT MAP ( + devoe => ww_devoe, + devclrn => ww_devclrn, + devpor => ww_devpor); + +-- Location: IOOBUF_X87_Y73_N9 +\LEDR[5]~output\ : cycloneive_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst|ALT_INV_norOut~0_combout\, + devoe => ww_devoe, + o => \LEDR[5]~output_o\); + +-- Location: IOOBUF_X87_Y73_N16 +\LEDR[4]~output\ : cycloneive_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst|ALT_INV_nandOut~0_combout\, + devoe => ww_devoe, + o => \LEDR[4]~output_o\); + +-- Location: IOOBUF_X107_Y73_N16 +\LEDR[3]~output\ : cycloneive_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst|xorOut~combout\, + devoe => ww_devoe, + o => \LEDR[3]~output_o\); + +-- Location: IOOBUF_X94_Y73_N9 +\LEDR[2]~output\ : cycloneive_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst|norOut~0_combout\, + devoe => ww_devoe, + o => \LEDR[2]~output_o\); + +-- Location: IOOBUF_X94_Y73_N2 +\LEDR[1]~output\ : cycloneive_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst|nandOut~0_combout\, + devoe => ww_devoe, + o => \LEDR[1]~output_o\); + +-- Location: IOOBUF_X69_Y73_N16 +\LEDR[0]~output\ : cycloneive_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \ALT_INV_SW[0]~input_o\, + devoe => ww_devoe, + o => \LEDR[0]~output_o\); + +-- Location: IOIBUF_X115_Y14_N1 +\SW[1]~input\ : cycloneive_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_SW(1), + o => \SW[1]~input_o\); + +-- Location: IOIBUF_X115_Y17_N1 +\SW[0]~input\ : cycloneive_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_SW(0), + o => \SW[0]~input_o\); + +-- Location: LCCOMB_X95_Y72_N16 +\inst|norOut~0\ : cycloneive_lcell_comb +-- Equation(s): +-- \inst|norOut~0_combout\ = (\SW[1]~input_o\) # (\SW[0]~input_o\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111111001100", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \SW[1]~input_o\, + datad => \SW[0]~input_o\, + combout => \inst|norOut~0_combout\); + +-- Location: LCCOMB_X95_Y72_N10 +\inst|nandOut~0\ : cycloneive_lcell_comb +-- Equation(s): +-- \inst|nandOut~0_combout\ = (\SW[1]~input_o\ & \SW[0]~input_o\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1100110000000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \SW[1]~input_o\, + datad => \SW[0]~input_o\, + combout => \inst|nandOut~0_combout\); + +-- Location: LCCOMB_X95_Y72_N28 +\inst|xorOut\ : cycloneive_lcell_comb +-- Equation(s): +-- \inst|xorOut~combout\ = \SW[1]~input_o\ $ (\SW[0]~input_o\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0011001111001100", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \SW[1]~input_o\, + datad => \SW[0]~input_o\, + combout => \inst|xorOut~combout\); + +ww_LEDR(5) <= \LEDR[5]~output_o\; + +ww_LEDR(4) <= \LEDR[4]~output_o\; + +ww_LEDR(3) <= \LEDR[3]~output_o\; + +ww_LEDR(2) <= \LEDR[2]~output_o\; + +ww_LEDR(1) <= \LEDR[1]~output_o\; + +ww_LEDR(0) <= \LEDR[0]~output_o\; +END structure; + + diff --git a/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicTop_modelsim.xrf b/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicTop_modelsim.xrf new file mode 100644 index 0000000..3930aec --- /dev/null +++ b/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicTop_modelsim.xrf @@ -0,0 +1,21 @@ +vendor_name = ModelSim +source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/LogicUnit.vhd +source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/LogicTop.bdf +source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_b.vhd +source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_p.vhd +source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_b.vhd +source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_p.vhd +source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.cbx.xml +design_name = hard_block +design_name = LogicTop +instance = comp, \LEDR[5]~output\, LEDR[5]~output, LogicTop, 1 +instance = comp, \LEDR[4]~output\, LEDR[4]~output, LogicTop, 1 +instance = comp, \LEDR[3]~output\, LEDR[3]~output, LogicTop, 1 +instance = comp, \LEDR[2]~output\, LEDR[2]~output, LogicTop, 1 +instance = comp, \LEDR[1]~output\, LEDR[1]~output, LogicTop, 1 +instance = comp, \LEDR[0]~output\, LEDR[0]~output, LogicTop, 1 +instance = comp, \SW[1]~input\, SW[1]~input, LogicTop, 1 +instance = comp, \SW[0]~input\, SW[0]~input, LogicTop, 1 +instance = comp, \inst|norOut~0\, inst|norOut~0, LogicTop, 1 +instance = comp, \inst|nandOut~0\, inst|nandOut~0, LogicTop, 1 +instance = comp, \inst|xorOut\, inst|xorOut, LogicTop, 1 diff --git a/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicUnit.vwf.vht b/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicUnit.vwf.vht new file mode 100644 index 0000000..dfc5416 --- /dev/null +++ b/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicUnit.vwf.vht @@ -0,0 +1,75 @@ +-- Copyright (C) 2020 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions +-- and other software and tools, and any partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License +-- Subscription Agreement, the Intel Quartus Prime License Agreement, +-- the Intel FPGA IP License Agreement, or other applicable license +-- agreement, including, without limitation, that your use is for +-- the sole purpose of programming logic devices manufactured by +-- Intel and sold by Intel or its authorized distributors. Please +-- refer to the applicable agreement for further details, at +-- https://fpgasoftware.intel.com/eula. + +-- ***************************************************************************** +-- This file contains a Vhdl test bench with test vectors .The test vectors +-- are exported from a vector file in the Quartus Waveform Editor and apply to +-- the top level entity of the current Quartus project .The user can use this +-- testbench to simulate his design using a third-party simulation tool . +-- ***************************************************************************** +-- Generated on "03/07/2023 20:45:46" + +-- Vhdl Test Bench(with test vectors) for design : LogicTop +-- +-- Simulation tool : 3rd Party +-- + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +ENTITY LogicTop_vhd_vec_tst IS +END LogicTop_vhd_vec_tst; +ARCHITECTURE LogicTop_arch OF LogicTop_vhd_vec_tst IS +-- constants +-- signals +SIGNAL LEDR : STD_LOGIC_VECTOR(5 DOWNTO 0); +SIGNAL SW : STD_LOGIC_VECTOR(1 DOWNTO 0); +COMPONENT LogicTop + PORT ( + LEDR : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); + SW : IN STD_LOGIC_VECTOR(1 DOWNTO 0) + ); +END COMPONENT; +BEGIN + i1 : LogicTop + PORT MAP ( +-- list connections between master ports and signals + LEDR => LEDR, + SW => SW + ); +-- SW[1] +t_prcs_SW_1: PROCESS +BEGIN + SW(1) <= '0'; + WAIT FOR 400000 ps; + SW(1) <= '1'; + WAIT FOR 400000 ps; + SW(1) <= '0'; +WAIT; +END PROCESS t_prcs_SW_1; +-- SW[0] +t_prcs_SW_0: PROCESS +BEGIN + FOR i IN 1 TO 2 + LOOP + SW(0) <= '0'; + WAIT FOR 200000 ps; + SW(0) <= '1'; + WAIT FOR 200000 ps; + END LOOP; + SW(0) <= '0'; +WAIT; +END PROCESS t_prcs_SW_0; +END LogicTop_arch; diff --git a/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/transcript b/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/transcript new file mode 100644 index 0000000..5901b1c --- /dev/null +++ b/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/transcript @@ -0,0 +1,46 @@ +# do LogicDemo.do +# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020 +# Start time: 20:45:47 on Mar 07,2023 +# vcom -work work LogicTop.vho +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package VITAL_Timing +# -- Loading package VITAL_Primitives +# -- Loading package cycloneive_atom_pack +# -- Loading package cycloneive_components +# -- Compiling entity hard_block +# -- Compiling architecture structure of hard_block +# -- Compiling entity LogicTop +# -- Compiling architecture structure of LogicTop +# End time: 20:45:47 on Mar 07,2023, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020 +# Start time: 20:45:47 on Mar 07,2023 +# vcom -work work LogicUnit.vwf.vht +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Compiling entity LogicTop_vhd_vec_tst +# -- Compiling architecture LogicTop_arch of LogicTop_vhd_vec_tst +# End time: 20:45:47 on Mar 07,2023, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.LogicTop_vhd_vec_tst +# Start time: 20:45:47 on Mar 07,2023 +# Loading std.standard +# Loading std.textio(body) +# Loading ieee.std_logic_1164(body) +# Loading work.logictop_vhd_vec_tst(logictop_arch) +# Loading ieee.vital_timing(body) +# Loading ieee.vital_primitives(body) +# Loading cycloneive.cycloneive_atom_pack(body) +# Loading cycloneive.cycloneive_components +# Loading work.logictop(structure) +# Loading work.hard_block(structure) +# Loading ieee.std_logic_arith(body) +# Loading cycloneive.cycloneive_io_obuf(arch) +# Loading cycloneive.cycloneive_io_ibuf(arch) +# Loading cycloneive.cycloneive_lcell_comb(vital_lcell_comb) +# after#31 +# End time: 20:45:48 on Mar 07,2023, Elapsed time: 0:00:01 +# Errors: 0, Warnings: 0 diff --git a/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/vwf_sim_transcript b/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/vwf_sim_transcript new file mode 100644 index 0000000..dc656c4 --- /dev/null +++ b/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/vwf_sim_transcript @@ -0,0 +1,66 @@ +Determining the location of the ModelSim executable... + +Using: /home/tiagorg/intelFPGA_lite/20.1/modelsim_ase/linuxaloem/ + +To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options +Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used. + +**** Generating the ModelSim Testbench **** + +quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off LogicDemo -c LogicTop --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/LogicUnit.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicUnit.vwf.vht" + +Info: *******************************************************************Info: Running Quartus Prime EDA Netlist Writer Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Info: Copyright (C) 2020 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Tue Mar 7 20:45:45 2023Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off LogicDemo -c LogicTop --vector_source=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/LogicUnit.vwf --testbench_file=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicUnit.vwf.vhtWarning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Completed successfully. + +**** Generating the functional simulation netlist **** + +quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/" LogicDemo -c LogicTop + +Info: *******************************************************************Info: Running Quartus Prime EDA Netlist Writer Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Info: Copyright (C) 2020 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Tue Mar 7 20:45:46 2023Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/ LogicDemo -c LogicTopWarning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.Info (204019): Generated file LogicTop.vho in folder "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim//" for EDA simulation toolInfo: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning Info: Peak virtual memory: 613 megabytes Info: Processing ended: Tue Mar 7 20:45:46 2023 Info: Elapsed time: 00:00:00 Info: Total CPU time (on all processors): 00:00:00 +Completed successfully. + +**** Generating the ModelSim .do script **** + +/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicDemo.do generated. + +Completed successfully. + +**** Running the ModelSim simulation **** + +/home/tiagorg/intelFPGA_lite/20.1/modelsim_ase/linuxaloem//vsim -c -do LogicDemo.do + +Reading pref.tcl +# 2020.1 +# do LogicDemo.do +# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020 +# Start time: 20:45:47 on Mar 07,2023# vcom -work work LogicTop.vho +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164# -- Loading package VITAL_Timing# -- Loading package VITAL_Primitives# -- Loading package cycloneive_atom_pack# -- Loading package cycloneive_components +# -- Compiling entity hard_block# -- Compiling architecture structure of hard_block +# -- Compiling entity LogicTop +# -- Compiling architecture structure of LogicTop +# End time: 20:45:47 on Mar 07,2023, Elapsed time: 0:00:00# Errors: 0, Warnings: 0 +# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020 +# Start time: 20:45:47 on Mar 07,2023# vcom -work work LogicUnit.vwf.vht # -- Loading package STANDARD# -- Loading package TEXTIO# -- Loading package std_logic_1164 +# -- Compiling entity LogicTop_vhd_vec_tst# -- Compiling architecture LogicTop_arch of LogicTop_vhd_vec_tst# End time: 20:45:47 on Mar 07,2023, Elapsed time: 0:00:00# Errors: 0, Warnings: 0 +# vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.LogicTop_vhd_vec_tst # Start time: 20:45:47 on Mar 07,2023# Loading std.standard# Loading std.textio(body)# Loading ieee.std_logic_1164(body)# Loading work.logictop_vhd_vec_tst(logictop_arch)# Loading ieee.vital_timing(body)# Loading ieee.vital_primitives(body)# Loading cycloneive.cycloneive_atom_pack(body)# Loading cycloneive.cycloneive_components# Loading work.logictop(structure)# Loading work.hard_block(structure)# Loading ieee.std_logic_arith(body)# Loading cycloneive.cycloneive_io_obuf(arch)# Loading cycloneive.cycloneive_io_ibuf(arch)# Loading cycloneive.cycloneive_lcell_comb(vital_lcell_comb) +# after#31 +# End time: 20:45:48 on Mar 07,2023, Elapsed time: 0:00:01# Errors: 0, Warnings: 0 +Completed successfully. + +**** Converting ModelSim VCD to vector waveform **** + +Reading /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/LogicUnit.vwf... + +Reading /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicDemo.msim.vcd... + +Processing channel transitions... + +Writing the resulting VWF to /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicDemo_20230307204548.sim.vwf + +Finished VCD to VWF conversion. + +Completed successfully. + +All completed. \ No newline at end of file diff --git a/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/work/_info b/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/work/_info new file mode 100644 index 0000000..cfadd6d --- /dev/null +++ b/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/work/_info @@ -0,0 +1,150 @@ +m255 +K4 +z2 +!s11e vcom 2020.1 2020.02, Feb 28 2020 +13 +!s112 1.1 +!i10d 8192 +!i10e 25 +!i10f 100 +cModel Technology +Z0 d/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim +Ehard_block +Z1 w1678221946 +Z2 DPx4 ieee 16 vital_primitives 0 22 G>kiXP8Q9dRClKfK1Zn7j1 +Z3 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