diff --git a/1ano/2semestre/lsd/pratica08/Chronometer/Bin7SegDecoder.vhd b/1ano/2semestre/lsd/pratica08/Chronometer/Bin7SegDecoder.vhd new file mode 100644 index 0000000..b3560fb --- /dev/null +++ b/1ano/2semestre/lsd/pratica08/Chronometer/Bin7SegDecoder.vhd @@ -0,0 +1,28 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity Bin7SegDecoder is + port(binInput : in std_logic_vector(3 downto 0); + decOut_n : out std_logic_vector(6 downto 0)); +end Bin7SegDecoder; + +architecture Behavioral of Bin7SegDecoder is +begin + with binInput select + decOut_n <= "1111001" when "0001", --1 + "0100100" when "0010", --2 + "0110000" when "0011", --3 + "0011001" when "0100", --4 + "0010010" when "0101", --5 + "0000010" when "0110", --6 + "1111000" when "0111", --7 + "0000000" when "1000", --8 + "0010000" when "1001", --9 + "0001000" when "1010", --A + "0000011" when "1011", --b + "1000110" when "1100", --C + "0100001" when "1101", --d + "0000110" when "1110", --E + "0001110" when "1111", --F + "1000000" when others; --0 +end Behavioral; diff --git a/1ano/2semestre/lsd/pratica08/Chronometer/Chronometer.bdf b/1ano/2semestre/lsd/pratica08/Chronometer/Chronometer.bdf new file mode 100644 index 0000000..a41dd84 --- /dev/null +++ b/1ano/2semestre/lsd/pratica08/Chronometer/Chronometer.bdf @@ -0,0 +1,878 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, the Altera Quartus Prime License Agreement, +the Altera MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Altera and sold by Altera or its +authorized distributors. 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+) +(connector + (pt 536 472) + (pt 560 472) +) +(connector + (pt 520 488) + (pt 520 432) +) +(connector + (pt 520 488) + (pt 560 488) +) +(connector + (pt 520 368) + (pt 520 200) +) +(junction (pt 304 472)) +(junction (pt 304 416)) +(junction (pt 176 568)) +(junction (pt 176 488)) +(junction (pt 1064 344)) +(junction (pt 1064 432)) +(junction (pt 1064 520)) +(junction (pt 1064 256)) +(junction (pt 792 304)) +(junction (pt 536 416)) +(junction (pt 536 336)) +(junction (pt 536 272)) diff --git a/1ano/2semestre/lsd/pratica08/Chronometer/ClkDividerN.vhd b/1ano/2semestre/lsd/pratica08/Chronometer/ClkDividerN.vhd new file mode 100644 index 0000000..e609bdd --- /dev/null +++ b/1ano/2semestre/lsd/pratica08/Chronometer/ClkDividerN.vhd @@ -0,0 +1,41 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +entity ClkDividerN is + generic(divFactor : positive := 2); + port(clkIn : in std_logic; + clkOut : out std_logic); +end ClkDividerN; + +architecture Behavioral of ClkDividerN is + + subtype TCounter is natural range 0 to (divFactor - 1); + + signal s_divCounter : TCounter; + +begin + assert(divFactor >= 2); + + count_proc : process(clkIn) + begin + if (rising_edge(clkIn)) then + if (s_divCounter >= divFactor - 1) then + s_divCounter <= 0; + else + s_divCounter <= s_divCounter + 1; + end if; + end if; + end process; + + out_proc : process(clkIn) + begin + if (rising_edge(clkIn)) then + if (s_divCounter >= (divFactor / 2 - 1)) then + clkOut <= '1'; + else + clkOut <= '0'; + end if; + end if; + end process; +end Behavioral; diff --git a/1ano/2semestre/lsd/pratica08/Chronometer/CntBCDUp4.vhd b/1ano/2semestre/lsd/pratica08/Chronometer/CntBCDUp4.vhd new file mode 100644 index 0000000..5128e8f --- /dev/null +++ b/1ano/2semestre/lsd/pratica08/Chronometer/CntBCDUp4.vhd @@ -0,0 +1,49 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +entity CntBCDUp4 is + port(reset : in std_logic; + clk : in std_logic; + enable1 : in std_logic; + enable2 : in std_logic; + count : out std_logic_vector(15 downto 0)); +end CntBCDUp4; + +architecture Behavioral of CntBCDUp4 is + + signal s_count : unsigned(15 downto 0); + +begin + count_proc : process(clk) + begin + if (rising_edge(clk)) then + if (reset = '1') then + s_count <= (others => '0'); + elsif ((enable1 = '1') and (enable2 = '1')) then + if (s_count(3 downto 0) = X"9") then + s_count(3 downto 0) <= X"0"; + if (s_count(7 downto 4) = X"9") then + s_count(7 downto 4) <= X"0"; + if (s_count(11 downto 8) = X"9") then + s_count(11 downto 8) <= X"0"; + if (s_count(15 downto 12) = X"9") then + s_count(15 downto 12) <= X"0"; + else + s_count(15 downto 12) <= s_count(15 downto 12) + 1; + end if; + else + s_count(11 downto 8) <= s_count(11 downto 8) + 1; + end if; + else + s_count(7 downto 4) <= s_count(7 downto 4) + 1; + end if; + else + s_count(3 downto 0) <= s_count(3 downto 0) + 1; + end if; + end if; + end if; + end process; + + count <= std_logic_vector(s_count); +end Behavioral; diff --git a/1ano/2semestre/lsd/pratica08/Chronometer/ControlUnit.smf b/1ano/2semestre/lsd/pratica08/Chronometer/ControlUnit.smf new file mode 100644 index 0000000..542cda6 --- /dev/null +++ b/1ano/2semestre/lsd/pratica08/Chronometer/ControlUnit.smf @@ -0,0 +1,209 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. + +Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, the Altera Quartus Prime License Agreement, +the Altera MegaCore Function License Agreement, or other +applicable license agreement, including, without limitation, +that your use is for the sole purpose of programming logic +devices manufactured by Altera and sold by Altera or its +authorized distributors. Please refer to the applicable +agreement for further details. + +Generated by Quartus Prime Version 15.1.1 Build 189 12/02/2015 SJ Lite Edition +Created on Mon Apr 11 16:06:33 2016 + +*/ +VERSION = "3.0"; +HEADER +( + GENERAL{ + RMODE = "S"; + RA_LEVEL = "H"; + HOPT = "VHDL"; + } + + SPORT{ + NAME = "clk"; + PTYPE = "CI"; + REG = "N"; + OUTS = "N"; + } + + SPORT{ + NAME = "reset"; + PTYPE = "RI"; + REG = "N"; + OUTS = "N"; + } + + SPORT{ + NAME = "statop"; + PTYPE = "OI"; + REG = "N"; + OUTS = "N"; + } + + SPORT{ + NAME = "laprst"; + PTYPE = "OI"; + REG = "N"; + OUTS = "N"; + } + + SPORT{ + NAME = "cntRst"; + PTYPE = "OU"; + REG = "N"; + OUTS = "C"; + } + + SPORT{ + NAME = "cntEnb"; + PTYPE = "OU"; + REG = "N"; + OUTS = "C"; + } + + SPORT{ + NAME = "regEnb"; + PTYPE = "OU"; + REG = "N"; + OUTS = "C"; + } + + STATE{ + NAME = "CLEARED"; + STYPE = "RE"; + PT = (40,80); + OUTP = "cntRst"; + OUT_VALUE = "1"; + COND = ""; + OUTP = "cntEnb"; + OUT_VALUE = "1"; + COND = ""; + OUTP = "regEnb"; + OUT_VALUE = "1"; + COND = ""; + } + + STATE{ + NAME = "STARTED"; + STYPE = "NR"; + PT = (200,80); + OUTP = "cntRst"; + OUT_VALUE = "0"; + COND = ""; + OUTP = "cntEnb"; + OUT_VALUE = "1"; + COND = ""; + OUTP = "regEnb"; + OUT_VALUE = "1"; + COND = ""; + } + + STATE{ + NAME = "STOPPED"; + STYPE = "NR"; + PT = (360,80); + OUTP = "cntRst"; + OUT_VALUE = "0"; + COND = ""; + OUTP = "cntEnb"; + OUT_VALUE = "0"; + COND = ""; + OUTP = "regEnb"; + OUT_VALUE = "1"; + COND = ""; + } + + STATE{ + NAME = "LAPVIEW"; + STYPE = "NR"; + PT = (520,80); + OUTP = "cntRst"; + OUT_VALUE = "0"; + COND = ""; + OUTP = "cntEnb"; + OUT_VALUE = "1"; + COND = ""; + OUTP = "regEnb"; + OUT_VALUE = "0"; + COND = ""; + } + + TRANS{ + SSTATE = "CLEARED"; + DSTATE = "STARTED"; + EQ = "statop"; + PT = (64,79); + PT = (64,39); + PT = (224,39); + PT = (224,79); + PT = (128,32); + } + + TRANS{ + SSTATE = "STARTED"; + DSTATE = "LAPVIEW"; + EQ = "laprst"; + PT = (224,79); + PT = (224,-1); + PT = (544,-1); + PT = (544,79); + PT = (368,0); + } + + TRANS{ + SSTATE = "STARTED"; + DSTATE = "STOPPED"; + EQ = "(~laprst) & statop"; + PT = (224,79); + PT = (224,39); + PT = (384,39); + PT = (384,79); + PT = (352,40); + } + + TRANS{ + SSTATE = "LAPVIEW"; + DSTATE = "STARTED"; + EQ = "laprst"; + PT = (544,129); + PT = (544,209); + PT = (224,209); + PT = (224,129); + PT = (440,160); + } + + TRANS{ + SSTATE = "STOPPED"; + DSTATE = "STARTED"; + EQ = "statop"; + PT = (384,129); + PT = (384,169); + PT = (224,169); + PT = (224,129); + PT = (288,136); + } + + TRANS{ + SSTATE = "STOPPED"; + DSTATE = "CLEARED"; + EQ = "(~statop) & laprst"; + PT = (384,129); + PT = (384,209); + PT = (64,209); + PT = (64,129); + PT = (120,160); + } +) +END diff --git a/1ano/2semestre/lsd/pratica08/Chronometer/ControlUnit.vhd b/1ano/2semestre/lsd/pratica08/Chronometer/ControlUnit.vhd new file mode 100644 index 0000000..4033230 --- /dev/null +++ b/1ano/2semestre/lsd/pratica08/Chronometer/ControlUnit.vhd @@ -0,0 +1,81 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity ControlUnit is + port(reset : in std_logic; + clk : in std_logic; + statop : in std_logic; + laprst : in std_logic; + cntRst : out std_logic; + cntEnb : out std_logic; + regEnb : out std_logic); +end ControlUnit; + +architecture Behavioral of ControlUnit is + + type TState is (CLEARED, STARTED, STOPPED, LAPVIEW); + signal s_currentState, s_nextState : TState; + +begin + sync_proc : process(clk) + begin + if (rising_edge(clk)) then + if (reset = '1') then + s_currentState <= CLEARED; + else + s_currentState <= s_nextState; + end if; + end if; + end process; + + comb_proc : process(s_currentState, statop, laprst) + begin + case (s_currentState) is + when CLEARED => + cntRst <= '1'; + cntEnb <= '1'; + regEnb <= '1'; + if (statop = '1') then + s_nextState <= STARTED; + else + s_nextState <= CLEARED; + end if; + + when STARTED => + cntRst <= '0'; + cntEnb <= '1'; + regEnb <= '1'; + if (laprst = '1') then + s_nextState <= LAPVIEW; + elsif (statop = '1') then + s_nextState <= STOPPED; + else + s_nextState <= STARTED; + end if; + + when STOPPED => + cntRst <= '0'; + cntEnb <= '0'; + regEnb <= '1'; + if (statop = '1') then + s_nextState <= STARTED; + elsif (laprst = '1') then + s_nextState <= CLEARED; + else + s_nextState <= STOPPED; + end if; + + when LAPVIEW => + cntRst <= '0'; + cntEnb <= '1'; + regEnb <= '0'; + if (laprst = '1') then + s_nextState <= STARTED; + else + s_nextState <= LAPVIEW; + end if; + end case; + + end process; + +end Behavioral; diff --git a/1ano/2semestre/lsd/pratica08/Chronometer/DebounceUnit.vhd b/1ano/2semestre/lsd/pratica08/Chronometer/DebounceUnit.vhd new file mode 100644 index 0000000..df5e037 --- /dev/null +++ b/1ano/2semestre/lsd/pratica08/Chronometer/DebounceUnit.vhd @@ -0,0 +1,64 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +entity DebounceUnit is + generic(kHzClkFreq : positive := 50000; + mSecMinInWidth : positive := 100; + inPolarity : std_logic := '1'; + outPolarity : std_logic := '1'); + port(refClk : in std_logic; + dirtyIn : in std_logic; + pulsedOut : out std_logic); +end DebounceUnit; + +architecture Behavioral of DebounceUnit is + + constant MIN_IN_WIDTH_CYCLES : positive := mSecMinInWidth * kHzClkFreq; + subtype TCounter is natural range 0 to MIN_IN_WIDTH_CYCLES; + + signal s_debounceCnt : TCounter := 0; + signal s_dirtyIn, s_previousIn, s_pulsedOut : std_logic; + +begin + in_sync_proc : process(refClk) + begin + if (rising_edge(refClk)) then + if (inPolarity = '1') then + s_dirtyIn <= dirtyIn; + else + s_dirtyIn <= not dirtyIn; + end if; + s_previousIn <= s_dirtyIn; + end if; + end process; + + count_proc : process(refClk) + begin + if (rising_edge(refClk)) then + if ((s_dirtyIn = '0') or + (s_debounceCnt > MIN_IN_WIDTH_CYCLES)) then + s_debounceCnt <= 0; + s_pulsedOut <= '0'; + + elsif (s_dirtyIn = '1') then + if (s_previousIn = '0') then + s_debounceCnt <= MIN_IN_WIDTH_CYCLES; + s_pulsedOut <= '0'; + else + if (s_debounceCnt >= 1) then + s_debounceCnt <= s_debounceCnt - 1; + end if; + if (s_debounceCnt = 1) then + s_pulsedOut <= '1'; + else + s_pulsedOut <= '0'; + end if; + end if; + end if; + end if; + end process; + + pulsedOut <= s_pulsedOut when (outPolarity = '1') else + not s_pulsedOut; +end Behavioral; diff --git a/1ano/2semestre/lsd/pratica08/Chronometer/PulseGeneratorN.vhd b/1ano/2semestre/lsd/pratica08/Chronometer/PulseGeneratorN.vhd new file mode 100644 index 0000000..4fb5d8a --- /dev/null +++ b/1ano/2semestre/lsd/pratica08/Chronometer/PulseGeneratorN.vhd @@ -0,0 +1,38 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +entity PulseGeneratorN is + generic(numberSteps : positive := 8; + out0CompVal : natural := 2; + out1CompVal : natural := 4); + port(clkIn : in std_logic; + pulseOut0 : out std_logic; + pulseOut1 : out std_logic); +end PulseGeneratorN; + +architecture Behavioral of PulseGeneratorN is + + subtype TCounter is natural range 0 to (numberSteps - 1); + + signal s_counter : TCounter; + +begin + count_proc : process(clkIn) + begin + if (rising_edge(clkIn)) then + if (s_counter >= (numberSteps - 1)) then + s_counter <= 0; + else + s_counter <= s_counter + 1; + end if; + end if; + end process; + + pulseOut0 <= '1' when ((s_counter rem out0CompVal) = 0) else + '0'; + + pulseOut1 <= '1' when (s_counter < out1CompVal) else + '0'; + +end Behavioral; diff --git a/1ano/2semestre/lsd/pratica08/Chronometer/RegN.vhd b/1ano/2semestre/lsd/pratica08/Chronometer/RegN.vhd new file mode 100644 index 0000000..68dd0d6 --- /dev/null +++ b/1ano/2semestre/lsd/pratica08/Chronometer/RegN.vhd @@ -0,0 +1,30 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity RegN is + generic(size : positive := 8); + port(asyncReset : in std_logic; + clk : in std_logic; + enable : in std_logic; + syncReset : in std_logic; + dataIn : in std_logic_vector((size - 1) downto 0); + dataOut : out std_logic_vector((size - 1) downto 0)); +end RegN; + +architecture Behavioral of RegN is +begin + reg_proc : process(asyncReset, clk) + begin + if (asyncReset = '1') then + dataOut <= (others => '0'); + elsif (rising_edge(clk)) then + if (enable = '1') then + if (syncReset = '1') then + dataOut <= (others => '0'); + else + dataOut <= dataIn; + end if; + end if; + end if; + end process; +end Behavioral; diff --git a/1ano/2semestre/lsd/pratica08/Chronometer/output_files/Chronometer.sof b/1ano/2semestre/lsd/pratica08/Chronometer/output_files/Chronometer.sof new file mode 100644 index 0000000..8d5b11e Binary files /dev/null and b/1ano/2semestre/lsd/pratica08/Chronometer/output_files/Chronometer.sof differ diff --git a/1ano/2semestre/lsd/pratica08/LSD_2022-23_TrabPrat08.pdf b/1ano/2semestre/lsd/pratica08/LSD_2022-23_TrabPrat08.pdf new file mode 100644 index 0000000..2142067 Binary files /dev/null and b/1ano/2semestre/lsd/pratica08/LSD_2022-23_TrabPrat08.pdf differ