Merge pull request #35 from TiagoRG/dev-tiagorg

[LSD] pratica01 part4 finished (untested)
[LSD] pratica01 part3 simulation waveform created
[LSD] pratica01 part2 block diagram version of NAND2Gate

1ano/2semestre/lsd/pratica01/part2/AND2Gate.bsf

@@ -0,0 +1,51 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 2020  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 176 96)
+	(text "AND2Gate" (rect 5 0 51 12)(font "Arial" ))
+	(text "inst" (rect 8 64 20 76)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "inPort0" (rect 0 0 27 12)(font "Arial" ))
+		(text "inPort0" (rect 21 27 48 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "inPort1" (rect 0 0 25 12)(font "Arial" ))
+		(text "inPort1" (rect 21 43 46 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 160 32)
+		(output)
+		(text "outPort" (rect 0 0 28 12)(font "Arial" ))
+		(text "outPort" (rect 111 27 139 39)(font "Arial" ))
+		(line (pt 160 32)(pt 144 32)(line_width 1))
+	)
+	(drawing
+		(rectangle (rect 16 16 144 64)(line_width 1))
+	)
+)

1ano/2semestre/lsd/pratica01/part2/AND2Gate.qsf

@@ -55,9 +55,6 @@ set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_
 set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
 set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
 set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
-set_global_assignment -name VHDL_FILE AND2Gate.vhd
-set_global_assignment -name VECTOR_WAVEFORM_FILE AND2Gate.vwf
-set_global_assignment -name VHDL_FILE GateDemo.vhd
 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
@@ -580,6 +577,12 @@ set_location_assignment PIN_H14 -to EX_IO[3]
 set_location_assignment PIN_F14 -to EX_IO[4]
 set_location_assignment PIN_E10 -to EX_IO[5]
 set_location_assignment PIN_D9 -to EX_IO[6]
+set_global_assignment -name BDF_FILE NAND2Block.bdf
+set_global_assignment -name VHDL_FILE AND2Gate.vhd
+set_global_assignment -name VECTOR_WAVEFORM_FILE AND2Gate.vwf
+set_global_assignment -name VHDL_FILE GateDemo.vhd
 set_global_assignment -name VHDL_FILE NOTGate.vhd
 set_global_assignment -name VHDL_FILE NAND2Gate.vhd
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

1ano/2semestre/lsd/pratica01/part2/NAND2Block.bdf

@@ -0,0 +1,137 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 2020  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+*/
+(header "graphic" (version "1.4"))
+(pin
+	(input)
+	(rect 200 232 368 248)
+	(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
+	(text "inPort0" (rect 5 0 44 13)(font "Intel Clear" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
+)
+(pin
+	(input)
+	(rect 200 248 368 264)
+	(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
+	(text "inPort1" (rect 5 0 43 13)(font "Intel Clear" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
+)
+(pin
+	(output)
+	(rect 704 232 880 248)
+	(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
+	(text "outPort" (rect 90 0 127 11)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+)
+(symbol
+	(rect 376 208 536 288)
+	(text "AND2Gate" (rect 5 0 60 11)(font "Arial" ))
+	(text "inst" (rect 8 64 26 75)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "inPort0" (rect 0 0 36 11)(font "Arial" ))
+		(text "inPort0" (rect 21 27 57 38)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "inPort1" (rect 0 0 36 11)(font "Arial" ))
+		(text "inPort1" (rect 21 43 57 54)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48))
+	)
+	(port
+		(pt 160 32)
+		(output)
+		(text "outPort" (rect 0 0 37 11)(font "Arial" ))
+		(text "outPort" (rect 108 27 145 38)(font "Arial" ))
+		(line (pt 160 32)(pt 144 32))
+	)
+	(drawing
+		(rectangle (rect 16 16 144 64))
+	)
+)
+(symbol
+	(rect 544 208 696 288)
+	(text "NOTGate" (rect 5 0 53 11)(font "Arial" ))
+	(text "inst1" (rect 8 64 32 77)(font "Intel Clear" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "inPort" (rect 0 0 30 11)(font "Arial" ))
+		(text "inPort" (rect 21 27 51 38)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32))
+	)
+	(port
+		(pt 152 32)
+		(output)
+		(text "outPort" (rect 0 0 37 11)(font "Arial" ))
+		(text "outPort" (rect 100 27 137 38)(font "Arial" ))
+		(line (pt 152 32)(pt 136 32))
+	)
+	(drawing
+		(rectangle (rect 16 16 136 64))
+	)
+)
+(connector
+	(pt 704 240)
+	(pt 696 240)
+)
+(connector
+	(pt 544 240)
+	(pt 536 240)
+)
+(connector
+	(pt 368 240)
+	(pt 376 240)
+)
+(connector
+	(pt 368 256)
+	(pt 376 256)
+)

1ano/2semestre/lsd/pratica01/part2/NOTGate.bsf

@@ -0,0 +1,44 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 2020  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 168 96)
+	(text "NOTGate" (rect 5 0 43 12)(font "Arial" ))
+	(text "inst" (rect 8 64 20 76)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "inPort" (rect 0 0 22 12)(font "Arial" ))
+		(text "inPort" (rect 21 27 43 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 152 32)
+		(output)
+		(text "outPort" (rect 0 0 28 12)(font "Arial" ))
+		(text "outPort" (rect 103 27 131 39)(font "Arial" ))
+		(line (pt 152 32)(pt 136 32)(line_width 1))
+	)
+	(drawing
+		(rectangle (rect 16 16 136 64)(line_width 1))
+	)
+)

1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.asm.qmsg

@@ -1,7 +1,7 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1677672678699 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678221061486 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1677672678700 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar  1 12:11:18 2023 " "Processing started: Wed Mar  1 12:11:18 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1677672678700 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1677672678700 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678221061487 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar  7 20:31:01 2023 " "Processing started: Tue Mar  7 20:31:01 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678221061487 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1678221061487 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off VHDLDemo -c AND2Gate " "Command: quartus_asm --read_settings_files=off --write_settings_files=off VHDLDemo -c AND2Gate" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1677672678700 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off VHDLDemo -c AND2Gate " "Command: quartus_asm --read_settings_files=off --write_settings_files=off VHDLDemo -c AND2Gate" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1678221061487 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1677672679054 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1678221061690 ""}
-{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1677672683204 ""}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1678221063922 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1677672683383 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1678221064018 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "366 " "Peak virtual memory: 366 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1677672683912 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar  1 12:11:23 2023 " "Processing ended: Wed Mar  1 12:11:23 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1677672683912 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1677672683912 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1677672683912 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1677672683912 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "367 " "Peak virtual memory: 367 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678221064279 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar  7 20:31:04 2023 " "Processing ended: Tue Mar  7 20:31:04 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678221064279 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678221064279 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678221064279 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1678221064279 ""}

1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.db_info

@@ -1,3 +1,3 @@
 Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 Version_Index = 520278016
-Creation_Time = Wed Mar  1 12:02:24 2023
+Creation_Time = Tue Mar  7 20:19:31 2023

1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.eda.qmsg

@@ -1,6 +1,6 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1677672688903 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678221066801 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1677672688904 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar  1 12:11:28 2023 " "Processing started: Wed Mar  1 12:11:28 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1677672688904 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1677672688904 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678221066801 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar  7 20:31:06 2023 " "Processing started: Tue Mar  7 20:31:06 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678221066801 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1678221066801 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off VHDLDemo -c AND2Gate " "Command: quartus_eda --read_settings_files=off --write_settings_files=off VHDLDemo -c AND2Gate" {  } {  } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1677672688904 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off VHDLDemo -c AND2Gate " "Command: quartus_eda --read_settings_files=off --write_settings_files=off VHDLDemo -c AND2Gate" {  } {  } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1678221066801 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1677672689345 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1678221067030 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "AND2Gate.vho /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/simulation/modelsim/ simulation " "Generated file AND2Gate.vho in folder \"/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1677672689416 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "AND2Gate.vho /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/simulation/modelsim/ simulation " "Generated file AND2Gate.vho in folder \"/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1678221067067 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1  Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "612 " "Peak virtual memory: 612 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1677672689443 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar  1 12:11:29 2023 " "Processing ended: Wed Mar  1 12:11:29 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1677672689443 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1677672689443 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1677672689443 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1677672689443 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1  Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "612 " "Peak virtual memory: 612 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678221067087 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar  7 20:31:07 2023 " "Processing ended: Tue Mar  7 20:31:07 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678221067087 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678221067087 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678221067087 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1678221067087 ""}

1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.hier_info

@@ -1,8 +1,8 @@
 |GateDemo
 SW[0] => nand2gate:system_core.inPort0
 SW[1] => nand2gate:system_core.inPort1
-LEDR[0] <= nand2gate:system_core.outPort
+LEDR[0] << nand2gate:system_core.outPort
-LEDR[1] <= <GND>
+LEDR[1] << <GND>
 
 
 |GateDemo|NAND2Gate:system_core

1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.map.qmsg

@@ -1,19 +1,20 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1677672647968 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678221044023 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1677672647968 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar  1 12:10:47 2023 " "Processing started: Wed Mar  1 12:10:47 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1677672647968 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1677672647968 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678221044024 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar  7 20:30:43 2023 " "Processing started: Tue Mar  7 20:30:43 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678221044024 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678221044024 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off VHDLDemo -c AND2Gate " "Command: quartus_map --read_settings_files=on --write_settings_files=off VHDLDemo -c AND2Gate" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1677672647968 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off VHDLDemo -c AND2Gate " "Command: quartus_map --read_settings_files=on --write_settings_files=off VHDLDemo -c AND2Gate" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678221044024 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1677672648329 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1678221044176 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1677672648330 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1678221044176 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "AND2Gate.vhd 2 1 " "Found 2 design units, including 1 entities, in source file AND2Gate.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 AND2Gate-Behavioral " "Found design unit 1: AND2Gate-Behavioral" {  } { { "AND2Gate.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/AND2Gate.vhd" 15 -1 0 } }  } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1677672658641 ""} { "Info" "ISGN_ENTITY_NAME" "1 AND2Gate " "Found entity 1: AND2Gate" {  } { { "AND2Gate.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/AND2Gate.vhd" 6 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1677672658641 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1677672658641 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "NAND2Block.bdf 1 1 " "Found 1 design units, including 1 entities, in source file NAND2Block.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 NAND2Block " "Found entity 1: NAND2Block" {  } { { "NAND2Block.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/NAND2Block.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678221049524 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678221049524 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "GateDemo.vhd 2 1 " "Found 2 design units, including 1 entities, in source file GateDemo.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 GateDemo-Shell " "Found design unit 1: GateDemo-Shell" {  } { { "GateDemo.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/GateDemo.vhd" 11 -1 0 } }  } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1677672658643 ""} { "Info" "ISGN_ENTITY_NAME" "1 GateDemo " "Found entity 1: GateDemo" {  } { { "GateDemo.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/GateDemo.vhd" 4 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1677672658643 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1677672658643 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "AND2Gate.vhd 2 1 " "Found 2 design units, including 1 entities, in source file AND2Gate.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 AND2Gate-Behavioral " "Found design unit 1: AND2Gate-Behavioral" {  } { { "AND2Gate.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/AND2Gate.vhd" 15 -1 0 } }  } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678221049760 ""} { "Info" "ISGN_ENTITY_NAME" "1 AND2Gate " "Found entity 1: AND2Gate" {  } { { "AND2Gate.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/AND2Gate.vhd" 6 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678221049760 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678221049760 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "NOTGate.vhd 2 1 " "Found 2 design units, including 1 entities, in source file NOTGate.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 NOTGate-Behavioral " "Found design unit 1: NOTGate-Behavioral" {  } { { "NOTGate.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/NOTGate.vhd" 11 -1 0 } }  } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1677672658643 ""} { "Info" "ISGN_ENTITY_NAME" "1 NOTGate " "Found entity 1: NOTGate" {  } { { "NOTGate.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/NOTGate.vhd" 4 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1677672658643 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1677672658643 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "GateDemo.vhd 2 1 " "Found 2 design units, including 1 entities, in source file GateDemo.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 GateDemo-Shell " "Found design unit 1: GateDemo-Shell" {  } { { "GateDemo.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/GateDemo.vhd" 11 -1 0 } }  } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678221049761 ""} { "Info" "ISGN_ENTITY_NAME" "1 GateDemo " "Found entity 1: GateDemo" {  } { { "GateDemo.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/GateDemo.vhd" 4 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678221049761 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678221049761 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "NAND2Gate.vhd 2 1 " "Found 2 design units, including 1 entities, in source file NAND2Gate.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 NAND2Gate-Structural " "Found design unit 1: NAND2Gate-Structural" {  } { { "NAND2Gate.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/NAND2Gate.vhd" 12 -1 0 } }  } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1677672658644 ""} { "Info" "ISGN_ENTITY_NAME" "1 NAND2Gate " "Found entity 1: NAND2Gate" {  } { { "NAND2Gate.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/NAND2Gate.vhd" 4 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1677672658644 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1677672658644 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "NOTGate.vhd 2 1 " "Found 2 design units, including 1 entities, in source file NOTGate.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 NOTGate-Behavioral " "Found design unit 1: NOTGate-Behavioral" {  } { { "NOTGate.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/NOTGate.vhd" 11 -1 0 } }  } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678221049761 ""} { "Info" "ISGN_ENTITY_NAME" "1 NOTGate " "Found entity 1: NOTGate" {  } { { "NOTGate.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/NOTGate.vhd" 4 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678221049761 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678221049761 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "GateDemo " "Elaborating entity \"GateDemo\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1677672658720 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "NAND2Gate.vhd 2 1 " "Found 2 design units, including 1 entities, in source file NAND2Gate.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 NAND2Gate-Structural " "Found design unit 1: NAND2Gate-Structural" {  } { { "NAND2Gate.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/NAND2Gate.vhd" 12 -1 0 } }  } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678221049761 ""} { "Info" "ISGN_ENTITY_NAME" "1 NAND2Gate " "Found entity 1: NAND2Gate" {  } { { "NAND2Gate.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/NAND2Gate.vhd" 4 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678221049761 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678221049761 ""}
-{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "LEDR\[1\] GateDemo.vhd(7) " "Using initial value X (don't care) for net \"LEDR\[1\]\" at GateDemo.vhd(7)" {  } { { "GateDemo.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/GateDemo.vhd" 7 0 0 } }  } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1677672658722 "|GateDemo"}
+{ "Info" "ISGN_START_ELABORATION_TOP" "GateDemo " "Elaborating entity \"GateDemo\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1678221049794 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "NAND2Gate NAND2Gate:system_core A:structural " "Elaborating entity \"NAND2Gate\" using architecture \"A:structural\" for hierarchy \"NAND2Gate:system_core\"" {  } { { "GateDemo.vhd" "system_core" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/GateDemo.vhd" 13 0 0 } }  } 0 12129 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1677672658729 ""}
+{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "LEDR\[1\] GateDemo.vhd(7) " "Using initial value X (don't care) for net \"LEDR\[1\]\" at GateDemo.vhd(7)" {  } { { "GateDemo.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/GateDemo.vhd" 7 0 0 } }  } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1678221049795 "|GateDemo"}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "AND2Gate NAND2Gate:system_core\|AND2Gate:and_gate A:behavioral " "Elaborating entity \"AND2Gate\" using architecture \"A:behavioral\" for hierarchy \"NAND2Gate:system_core\|AND2Gate:and_gate\"" {  } { { "NAND2Gate.vhd" "and_gate" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/NAND2Gate.vhd" 15 0 0 } }  } 0 12129 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1677672658731 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "NAND2Gate NAND2Gate:system_core A:structural " "Elaborating entity \"NAND2Gate\" using architecture \"A:structural\" for hierarchy \"NAND2Gate:system_core\"" {  } { { "GateDemo.vhd" "system_core" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/GateDemo.vhd" 13 0 0 } }  } 0 12129 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678221049796 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "NOTGate NAND2Gate:system_core\|NOTGate:not_gate A:behavioral " "Elaborating entity \"NOTGate\" using architecture \"A:behavioral\" for hierarchy \"NAND2Gate:system_core\|NOTGate:not_gate\"" {  } { { "NAND2Gate.vhd" "not_gate" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/NAND2Gate.vhd" 22 0 0 } }  } 0 12129 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1677672658733 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "AND2Gate NAND2Gate:system_core\|AND2Gate:and_gate A:behavioral " "Elaborating entity \"AND2Gate\" using architecture \"A:behavioral\" for hierarchy \"NAND2Gate:system_core\|AND2Gate:and_gate\"" {  } { { "NAND2Gate.vhd" "and_gate" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/NAND2Gate.vhd" 15 0 0 } }  } 0 12129 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678221049796 ""}
-{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[1\] GND " "Pin \"LEDR\[1\]\" is stuck at GND" {  } { { "GateDemo.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/GateDemo.vhd" 7 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1677672659495 "|GateDemo|LEDR[1]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1677672659495 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "NOTGate NAND2Gate:system_core\|NOTGate:not_gate A:behavioral " "Elaborating entity \"NOTGate\" using architecture \"A:behavioral\" for hierarchy \"NAND2Gate:system_core\|NOTGate:not_gate\"" {  } { { "NAND2Gate.vhd" "not_gate" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/NAND2Gate.vhd" 22 0 0 } }  } 0 12129 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678221049798 ""}
-{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1677672659651 ""}
+{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[1\] GND " "Pin \"LEDR\[1\]\" is stuck at GND" {  } { { "GateDemo.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/GateDemo.vhd" 7 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1678221050110 "|GateDemo|LEDR[1]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1678221050110 ""}
-{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1677672660481 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1677672660481 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1678221050172 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "5 " "Implemented 5 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Implemented 2 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1677672660526 ""} { "Info" "ICUT_CUT_TM_OPINS" "2 " "Implemented 2 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1677672660526 ""} { "Info" "ICUT_CUT_TM_LCELLS" "1 " "Implemented 1 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1677672660526 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1677672660526 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1678221050531 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678221050531 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "431 " "Peak virtual memory: 431 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1677672660535 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar  1 12:11:00 2023 " "Processing ended: Wed Mar  1 12:11:00 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1677672660535 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Elapsed time: 00:00:13" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1677672660535 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:34 " "Total CPU time (on all processors): 00:00:34" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1677672660535 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1677672660535 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "5 " "Implemented 5 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Implemented 2 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1678221050551 ""} { "Info" "ICUT_CUT_TM_OPINS" "2 " "Implemented 2 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1678221050551 ""} { "Info" "ICUT_CUT_TM_LCELLS" "1 " "Implemented 1 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1678221050551 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1678221050551 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "432 " "Peak virtual memory: 432 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678221050557 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar  7 20:30:50 2023 " "Processing ended: Tue Mar  7 20:30:50 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678221050557 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678221050557 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:16 " "Total CPU time (on all processors): 00:00:16" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678221050557 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1678221050557 ""}

1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.sta.qmsg

@@ -1,49 +1,49 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1677672685158 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678221064953 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1677672685159 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar  1 12:11:24 2023 " "Processing started: Wed Mar  1 12:11:24 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1677672685159 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1677672685159 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678221064953 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar  7 20:31:04 2023 " "Processing started: Tue Mar  7 20:31:04 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678221064953 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1678221064953 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta VHDLDemo -c AND2Gate " "Command: quartus_sta VHDLDemo -c AND2Gate" {  } {  } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1677672685159 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta VHDLDemo -c AND2Gate " "Command: quartus_sta VHDLDemo -c AND2Gate" {  } {  } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1678221064953 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1677672685220 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1678221064981 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1677672685387 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1678221065060 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1677672685387 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1678221065060 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1677672685509 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678221065120 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1677672685509 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678221065120 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "AND2Gate.sdc " "Synopsys Design Constraints File file not found: 'AND2Gate.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1677672686342 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "AND2Gate.sdc " "Synopsys Design Constraints File file not found: 'AND2Gate.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1678221065549 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1677672686343 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678221065550 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1677672686343 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1678221065550 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1677672686344 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1678221065551 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1677672686344 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" {  } {  } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1678221065551 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1677672686344 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678221065551 ""}
-{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1677672686345 ""}
+{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1678221065552 ""}
-{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" {  } {  } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1677672686352 ""}
+{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" {  } {  } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1678221065557 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1677672686353 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1678221065558 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677672686355 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678221065559 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677672686359 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678221065561 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677672686360 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678221065561 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677672686360 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678221065561 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677672686361 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678221065562 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677672686362 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678221065562 ""}
-{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1677672686366 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1678221065565 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1677672686404 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1678221065584 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1677672686830 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1678221065793 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1677672686860 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678221065809 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1677672686861 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1678221065809 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1677672686861 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1678221065809 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1677672686861 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678221065809 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677672686862 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678221065809 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677672686863 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678221065810 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677672686864 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678221065810 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677672686865 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678221065811 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677672686866 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678221065811 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677672686867 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678221065812 ""}
-{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1677672686870 ""}
+{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1678221065814 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1677672686971 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" {  } {  } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678221065864 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1677672686972 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." {  } {  } 0 332096 "The command derive_clocks did not find any clocks to derive.  No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1678221065864 ""}
-{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1677672686972 ""}
+{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." {  } {  } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1678221065864 ""}
-{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1677672686972 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." {  } {  } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678221065864 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677672686973 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678221065865 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677672686974 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678221065865 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677672686975 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678221065866 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677672686976 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678221065866 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1677672686976 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678221065866 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1677672687564 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1678221066143 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1677672687564 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1678221066143 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "535 " "Peak virtual memory: 535 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1677672687589 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar  1 12:11:27 2023 " "Processing ended: Wed Mar  1 12:11:27 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1677672687589 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1677672687589 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1677672687589 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1677672687589 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "533 " "Peak virtual memory: 533 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678221066155 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar  7 20:31:06 2023 " "Processing ended: Tue Mar  7 20:31:06 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678221066155 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678221066155 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678221066155 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1678221066155 ""}

1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.tmw_info

@@ -1,7 +1,7 @@
-start_full_compilation:s:00:00:43
+start_full_compilation:s:00:00:24
-start_analysis_synthesis:s:00:00:14-start_full_compilation
+start_analysis_synthesis:s:00:00:07-start_full_compilation
 start_analysis_elaboration:s-start_full_compilation
-start_fitter:s:00:00:17-start_full_compilation
+start_fitter:s:00:00:10-start_full_compilation
-start_assembler:s:00:00:07-start_full_compilation
+start_assembler:s:00:00:04-start_full_compilation
-start_timing_analyzer:s:00:00:03-start_full_compilation
+start_timing_analyzer:s:00:00:02-start_full_compilation
-start_eda_netlist_writer:s:00:00:02-start_full_compilation
+start_eda_netlist_writer:s:00:00:01-start_full_compilation

1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.asm.rpt

@@ -1,5 +1,5 @@
 Assembler report for AND2Gate
-Wed Mar  1 12:11:23 2023
+Tue Mar  7 20:31:04 2023
 Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 
 
@@ -38,7 +38,7 @@ https://fpgasoftware.intel.com/eula.
 +---------------------------------------------------------------+
 ; Assembler Summary                                             ;
 +-----------------------+---------------------------------------+
-; Assembler Status      ; Successful - Wed Mar  1 12:11:23 2023 ;
+; Assembler Status      ; Successful - Tue Mar  7 20:31:04 2023 ;
 ; Revision Name         ; AND2Gate                              ;
 ; Top-level Entity Name ; GateDemo                              ;
 ; Family                ; Cyclone IV E                          ;
@@ -53,13 +53,13 @@ https://fpgasoftware.intel.com/eula.
 +--------+---------+---------------+
 
 
-+--------------------------------------------------------------------------------------------+
++-----------------------------------------------------------------------------------------------+
 ; Assembler Generated Files                                                                     ;
-+--------------------------------------------------------------------------------------------+
++-----------------------------------------------------------------------------------------------+
 ; File Name                                                                                     ;
-+--------------------------------------------------------------------------------------------+
++-----------------------------------------------------------------------------------------------+
-; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/output_files/AND2Gate.sof ;
+; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.sof ;
-+--------------------------------------------------------------------------------------------+
++-----------------------------------------------------------------------------------------------+
 
 
 +----------------------------------------+
@@ -78,15 +78,15 @@ https://fpgasoftware.intel.com/eula.
 Info: *******************************************************************
 Info: Running Quartus Prime Assembler
     Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-    Info: Processing started: Wed Mar  1 12:11:18 2023
+    Info: Processing started: Tue Mar  7 20:31:01 2023
 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off VHDLDemo -c AND2Gate
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
 Info (115031): Writing out detailed assembly data for power analysis
 Info (115030): Assembler is generating device programming files
 Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
-    Info: Peak virtual memory: 366 megabytes
+    Info: Peak virtual memory: 367 megabytes
-    Info: Processing ended: Wed Mar  1 12:11:23 2023
+    Info: Processing ended: Tue Mar  7 20:31:04 2023
-    Info: Elapsed time: 00:00:05
+    Info: Elapsed time: 00:00:03
-    Info: Total CPU time (on all processors): 00:00:05
+    Info: Total CPU time (on all processors): 00:00:03
 
 

1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.done

@@ -1 +1 @@
-Wed Mar  1 12:11:29 2023
+Tue Mar  7 20:31:07 2023

1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.eda.rpt

@@ -1,5 +1,5 @@
 EDA Netlist Writer report for AND2Gate
-Wed Mar  1 12:11:29 2023
+Tue Mar  7 20:31:07 2023
 Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 
 
@@ -37,7 +37,7 @@ https://fpgasoftware.intel.com/eula.
 +-------------------------------------------------------------------+
 ; EDA Netlist Writer Summary                                        ;
 +---------------------------+---------------------------------------+
-; EDA Netlist Writer Status ; Successful - Wed Mar  1 12:11:29 2023 ;
+; EDA Netlist Writer Status ; Successful - Tue Mar  7 20:31:07 2023 ;
 ; Revision Name             ; AND2Gate                              ;
 ; Top-level Entity Name     ; GateDemo                              ;
 ; Family                    ; Cyclone IV E                          ;
@@ -66,13 +66,13 @@ https://fpgasoftware.intel.com/eula.
 +---------------------------------------------------------------------------------------------------+------------------------+
 
 
-+---------------------------------------------------------------------------------------------------+
++------------------------------------------------------------------------------------------------------+
 ; Simulation Generated Files                                                                           ;
-+---------------------------------------------------------------------------------------------------+
++------------------------------------------------------------------------------------------------------+
 ; Generated Files                                                                                      ;
-+---------------------------------------------------------------------------------------------------+
++------------------------------------------------------------------------------------------------------+
-; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/simulation/modelsim/AND2Gate.vho ;
+; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/simulation/modelsim/AND2Gate.vho ;
-+---------------------------------------------------------------------------------------------------+
++------------------------------------------------------------------------------------------------------+
 
 
 +-----------------------------+
@@ -81,14 +81,14 @@ https://fpgasoftware.intel.com/eula.
 Info: *******************************************************************
 Info: Running Quartus Prime EDA Netlist Writer
     Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-    Info: Processing started: Wed Mar  1 12:11:28 2023
+    Info: Processing started: Tue Mar  7 20:31:06 2023
 Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off VHDLDemo -c AND2Gate
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (204019): Generated file AND2Gate.vho in folder "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file AND2Gate.vho in folder "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/simulation/modelsim/" for EDA simulation tool
 Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
     Info: Peak virtual memory: 612 megabytes
-    Info: Processing ended: Wed Mar  1 12:11:29 2023
+    Info: Processing ended: Tue Mar  7 20:31:07 2023
     Info: Elapsed time: 00:00:01
-    Info: Total CPU time (on all processors): 00:00:01
+    Info: Total CPU time (on all processors): 00:00:00
 
 

1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.fit.rpt

@@ -1,5 +1,5 @@
 Fitter report for AND2Gate
-Wed Mar  1 12:11:17 2023
+Tue Mar  7 20:31:00 2023
 Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 
 
@@ -64,7 +64,7 @@ https://fpgasoftware.intel.com/eula.
 +----------------------------------------------------------------------------------+
 ; Fitter Summary                                                                   ;
 +------------------------------------+---------------------------------------------+
-; Fitter Status                      ; Successful - Wed Mar  1 12:11:16 2023       ;
+; Fitter Status                      ; Successful - Tue Mar  7 20:31:00 2023       ;
 ; Quartus Prime Version              ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
 ; Revision Name                      ; AND2Gate                                    ;
 ; Top-level Entity Name              ; GateDemo                                    ;
@@ -721,7 +721,7 @@ https://fpgasoftware.intel.com/eula.
 +--------------+
 ; Pin-Out File ;
 +--------------+
-The pin-out file can be found in /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/output_files/AND2Gate.pin.
+The pin-out file can be found in /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.pin.
 
 
 +---------------------------------------------------------------------+
@@ -2468,7 +2468,7 @@ Warning (15705): Ignored locations or region assignments to the following nodes
     Warning (15706): Node "VGA_R[7]" is assigned to location or region, but does not exist in design
     Warning (15706): Node "VGA_SYNC_N" is assigned to location or region, but does not exist in design
     Warning (15706): Node "VGA_VS" is assigned to location or region, but does not exist in design
-Info (171121): Fitter preparation operations ending: elapsed time is 00:00:02
+Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
 Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
 Info (170189): Fitter placement preparation operations beginning
 Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
@@ -2481,25 +2481,25 @@ Info (170195): Router estimated average interconnect usage is 0% of the availabl
 Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
     Info (170201): Optimizations that may affect the design's routability were skipped
     Info (170200): Optimizations that may affect the design's timing were skipped
-Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
+Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
-Info (11888): Total time spent on timing analysis during the Fitter is 0.03 seconds.
+Info (11888): Total time spent on timing analysis during the Fitter is 0.02 seconds.
 Info (334003): Started post-fitting delay annotation
 Info (334004): Delay annotation completed successfully
 Info (334003): Started post-fitting delay annotation
 Info (334004): Delay annotation completed successfully
 Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01
 Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
-Info (144001): Generated suppressed messages file /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/output_files/AND2Gate.fit.smsg
+Info (144001): Generated suppressed messages file /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.fit.smsg
 Info: Quartus Prime Fitter was successful. 0 errors, 522 warnings
-    Info: Peak virtual memory: 1153 megabytes
+    Info: Peak virtual memory: 1142 megabytes
-    Info: Processing ended: Wed Mar  1 12:11:17 2023
+    Info: Processing ended: Tue Mar  7 20:31:00 2023
-    Info: Elapsed time: 00:00:16
+    Info: Elapsed time: 00:00:10
-    Info: Total CPU time (on all processors): 00:00:24
+    Info: Total CPU time (on all processors): 00:00:16
 
 
 +----------------------------+
 ; Fitter Suppressed Messages ;
 +----------------------------+
-The suppressed messages can be found in /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/output_files/AND2Gate.fit.smsg.
+The suppressed messages can be found in /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.fit.smsg.
 
 

1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.fit.summary

@@ -1,4 +1,4 @@
-Fitter Status : Successful - Wed Mar  1 12:11:16 2023
+Fitter Status : Successful - Tue Mar  7 20:31:00 2023
 Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 Revision Name : AND2Gate
 Top-level Entity Name : GateDemo

1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.flow.rpt

@@ -1,5 +1,5 @@
 Flow report for AND2Gate
-Wed Mar  1 12:11:29 2023
+Tue Mar  7 20:31:07 2023
 Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 
 
@@ -41,7 +41,7 @@ https://fpgasoftware.intel.com/eula.
 +----------------------------------------------------------------------------------+
 ; Flow Summary                                                                     ;
 +------------------------------------+---------------------------------------------+
-; Flow Status                        ; Successful - Wed Mar  1 12:11:29 2023       ;
+; Flow Status                        ; Successful - Tue Mar  7 20:31:07 2023       ;
 ; Quartus Prime Version              ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
 ; Revision Name                      ; AND2Gate                                    ;
 ; Top-level Entity Name              ; GateDemo                                    ;
@@ -65,7 +65,7 @@ https://fpgasoftware.intel.com/eula.
 +-------------------+---------------------+
 ; Option            ; Setting             ;
 +-------------------+---------------------+
-; Start date & time ; 03/01/2023 12:10:48 ;
+; Start date & time ; 03/07/2023 20:30:44 ;
 ; Main task         ; Compilation         ;
 ; Revision Name     ; AND2Gate            ;
 +-------------------+---------------------+
@@ -76,7 +76,7 @@ https://fpgasoftware.intel.com/eula.
 +-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
 ; Assignment Name                     ; Value                                  ; Default Value ; Entity Name ; Section Id                        ;
 +-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
-; COMPILER_SIGNATURE_ID               ; 198516037997543.167767264809108        ; --            ; --          ; --                                ;
+; COMPILER_SIGNATURE_ID               ; 2690080394329.167822104406633          ; --            ; --          ; --                                ;
 ; EDA_GENERATE_FUNCTIONAL_NETLIST     ; Off                                    ; --            ; --          ; eda_board_design_timing           ;
 ; EDA_GENERATE_FUNCTIONAL_NETLIST     ; Off                                    ; --            ; --          ; eda_board_design_boundary_scan    ;
 ; EDA_GENERATE_FUNCTIONAL_NETLIST     ; Off                                    ; --            ; --          ; eda_board_design_signal_integrity ;
@@ -90,6 +90,8 @@ https://fpgasoftware.intel.com/eula.
 ; PARTITION_COLOR                     ; -- (Not supported for targeted family) ; --            ; GateDemo    ; Top                               ;
 ; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; --            ; GateDemo    ; Top                               ;
 ; PARTITION_NETLIST_TYPE              ; -- (Not supported for targeted family) ; --            ; GateDemo    ; Top                               ;
+; POWER_BOARD_THERMAL_MODEL           ; None (CONSERVATIVE)                    ; --            ; --          ; --                                ;
+; POWER_PRESET_COOLING_SOLUTION       ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW  ; --            ; --          ; --                                ;
 ; PROJECT_OUTPUT_DIRECTORY            ; output_files                           ; --            ; --          ; --                                ;
 ; TOP_LEVEL_ENTITY                    ; GateDemo                               ; AND2Gate      ; --          ; --                                ;
 +-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
@@ -100,12 +102,12 @@ https://fpgasoftware.intel.com/eula.
 +----------------------+--------------+-------------------------+---------------------+------------------------------------+
 ; Module Name          ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
 +----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:00:13     ; 1.0                     ; 431 MB              ; 00:00:33                           ;
+; Analysis & Synthesis ; 00:00:07     ; 1.0                     ; 432 MB              ; 00:00:16                           ;
-; Fitter               ; 00:00:15     ; 1.0                     ; 1153 MB             ; 00:00:23                           ;
+; Fitter               ; 00:00:10     ; 1.0                     ; 1142 MB             ; 00:00:15                           ;
-; Assembler            ; 00:00:05     ; 1.0                     ; 366 MB              ; 00:00:05                           ;
+; Assembler            ; 00:00:03     ; 1.0                     ; 367 MB              ; 00:00:03                           ;
-; Timing Analyzer      ; 00:00:03     ; 1.0                     ; 535 MB              ; 00:00:03                           ;
+; Timing Analyzer      ; 00:00:02     ; 1.0                     ; 533 MB              ; 00:00:01                           ;
-; EDA Netlist Writer   ; 00:00:01     ; 1.0                     ; 612 MB              ; 00:00:01                           ;
+; EDA Netlist Writer   ; 00:00:01     ; 1.0                     ; 612 MB              ; 00:00:00                           ;
-; Total                ; 00:00:37     ; --                      ; --                  ; 00:01:05                           ;
+; Total                ; 00:00:23     ; --                      ; --                  ; 00:00:35                           ;
 +----------------------+--------------+-------------------------+---------------------+------------------------------------+
 
 

1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.jdi

@@ -1,6 +1,6 @@
 <sld_project_info>
   <project>
-    <hash md5_digest_80b="46614c487aec89c3549a"/>
+    <hash md5_digest_80b="d9079237bcc89eba2aaa"/>
   </project>
   <file_info>
     <file device="EP4CE115F29C7" path="AND2Gate.sof" usercode="0xFFFFFFFF"/>

1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.map.rpt

@@ -1,5 +1,5 @@
 Analysis & Synthesis report for AND2Gate
-Wed Mar  1 12:11:00 2023
+Tue Mar  7 20:30:50 2023
 Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 
 
@@ -43,7 +43,7 @@ https://fpgasoftware.intel.com/eula.
 +----------------------------------------------------------------------------------+
 ; Analysis & Synthesis Summary                                                     ;
 +------------------------------------+---------------------------------------------+
-; Analysis & Synthesis Status        ; Successful - Wed Mar  1 12:11:00 2023       ;
+; Analysis & Synthesis Status        ; Successful - Tue Mar  7 20:30:50 2023       ;
 ; Quartus Prime Version              ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
 ; Revision Name                      ; AND2Gate                                    ;
 ; Top-level Entity Name              ; GateDemo                                    ;
@@ -162,16 +162,16 @@ https://fpgasoftware.intel.com/eula.
 +----------------------------+-------------+
 
 
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
 ; Analysis & Synthesis Source Files Read                                                                                                                             ;
-+----------------------------------+-----------------+-----------------+--------------------------------------------------------------------------------+---------+
++----------------------------------+-----------------+-----------------+-----------------------------------------------------------------------------------+---------+
 ; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path                                                      ; Library ;
-+----------------------------------+-----------------+-----------------+--------------------------------------------------------------------------------+---------+
++----------------------------------+-----------------+-----------------+-----------------------------------------------------------------------------------+---------+
-; AND2Gate.vhd                     ; yes             ; User VHDL File  ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/AND2Gate.vhd  ;         ;
+; AND2Gate.vhd                     ; yes             ; User VHDL File  ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/AND2Gate.vhd  ;         ;
-; GateDemo.vhd                     ; yes             ; User VHDL File  ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/GateDemo.vhd  ;         ;
+; GateDemo.vhd                     ; yes             ; User VHDL File  ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/GateDemo.vhd  ;         ;
-; NOTGate.vhd                      ; yes             ; User VHDL File  ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/NOTGate.vhd   ;         ;
+; NOTGate.vhd                      ; yes             ; User VHDL File  ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/NOTGate.vhd   ;         ;
-; NAND2Gate.vhd                    ; yes             ; User VHDL File  ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/NAND2Gate.vhd ;         ;
+; NAND2Gate.vhd                    ; yes             ; User VHDL File  ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/NAND2Gate.vhd ;         ;
-+----------------------------------+-----------------+-----------------+--------------------------------------------------------------------------------+---------+
++----------------------------------+-----------------+-----------------+-----------------------------------------------------------------------------------+---------+
 
 
 +-----------------------------------------------------------------------------------------------+
@@ -255,7 +255,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 +----------------+--------------+
 ; Partition Name ; Elapsed Time ;
 +----------------+--------------+
-; Top            ; 00:00:01     ;
+; Top            ; 00:00:00     ;
 +----------------+--------------+
 
 
@@ -265,29 +265,31 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
 Info: *******************************************************************
 Info: Running Quartus Prime Analysis & Synthesis
     Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-    Info: Processing started: Wed Mar  1 12:10:47 2023
+    Info: Processing started: Tue Mar  7 20:30:43 2023
 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off VHDLDemo -c AND2Gate
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
 Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info (12021): Found 1 design units, including 1 entities, in source file NAND2Block.bdf
+    Info (12023): Found entity 1: NAND2Block
 Info (12021): Found 2 design units, including 1 entities, in source file AND2Gate.vhd
-    Info (12022): Found design unit 1: AND2Gate-Behavioral File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/AND2Gate.vhd Line: 15
+    Info (12022): Found design unit 1: AND2Gate-Behavioral File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/AND2Gate.vhd Line: 15
-    Info (12023): Found entity 1: AND2Gate File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/AND2Gate.vhd Line: 6
+    Info (12023): Found entity 1: AND2Gate File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/AND2Gate.vhd Line: 6
 Info (12021): Found 2 design units, including 1 entities, in source file GateDemo.vhd
-    Info (12022): Found design unit 1: GateDemo-Shell File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/GateDemo.vhd Line: 11
+    Info (12022): Found design unit 1: GateDemo-Shell File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/GateDemo.vhd Line: 11
-    Info (12023): Found entity 1: GateDemo File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/GateDemo.vhd Line: 4
+    Info (12023): Found entity 1: GateDemo File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/GateDemo.vhd Line: 4
 Info (12021): Found 2 design units, including 1 entities, in source file NOTGate.vhd
-    Info (12022): Found design unit 1: NOTGate-Behavioral File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/NOTGate.vhd Line: 11
+    Info (12022): Found design unit 1: NOTGate-Behavioral File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/NOTGate.vhd Line: 11
-    Info (12023): Found entity 1: NOTGate File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/NOTGate.vhd Line: 4
+    Info (12023): Found entity 1: NOTGate File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/NOTGate.vhd Line: 4
 Info (12021): Found 2 design units, including 1 entities, in source file NAND2Gate.vhd
-    Info (12022): Found design unit 1: NAND2Gate-Structural File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/NAND2Gate.vhd Line: 12
+    Info (12022): Found design unit 1: NAND2Gate-Structural File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/NAND2Gate.vhd Line: 12
-    Info (12023): Found entity 1: NAND2Gate File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/NAND2Gate.vhd Line: 4
+    Info (12023): Found entity 1: NAND2Gate File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/NAND2Gate.vhd Line: 4
 Info (12127): Elaborating entity "GateDemo" for the top level hierarchy
-Warning (10873): Using initial value X (don't care) for net "LEDR[1]" at GateDemo.vhd(7) File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/GateDemo.vhd Line: 7
+Warning (10873): Using initial value X (don't care) for net "LEDR[1]" at GateDemo.vhd(7) File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/GateDemo.vhd Line: 7
-Info (12129): Elaborating entity "NAND2Gate" using architecture "A:structural" for hierarchy "NAND2Gate:system_core" File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/GateDemo.vhd Line: 13
+Info (12129): Elaborating entity "NAND2Gate" using architecture "A:structural" for hierarchy "NAND2Gate:system_core" File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/GateDemo.vhd Line: 13
-Info (12129): Elaborating entity "AND2Gate" using architecture "A:behavioral" for hierarchy "NAND2Gate:system_core|AND2Gate:and_gate" File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/NAND2Gate.vhd Line: 15
+Info (12129): Elaborating entity "AND2Gate" using architecture "A:behavioral" for hierarchy "NAND2Gate:system_core|AND2Gate:and_gate" File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/NAND2Gate.vhd Line: 15
-Info (12129): Elaborating entity "NOTGate" using architecture "A:behavioral" for hierarchy "NAND2Gate:system_core|NOTGate:not_gate" File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/NAND2Gate.vhd Line: 22
+Info (12129): Elaborating entity "NOTGate" using architecture "A:behavioral" for hierarchy "NAND2Gate:system_core|NOTGate:not_gate" File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/NAND2Gate.vhd Line: 22
 Warning (13024): Output pins are stuck at VCC or GND
-    Warning (13410): Pin "LEDR[1]" is stuck at GND File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/GateDemo.vhd Line: 7
+    Warning (13410): Pin "LEDR[1]" is stuck at GND File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/GateDemo.vhd Line: 7
 Info (286030): Timing-Driven Synthesis is running
 Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
     Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
@@ -296,9 +298,9 @@ Info (21057): Implemented 5 device resources after synthesis - the final resourc
     Info (21059): Implemented 2 output pins
     Info (21061): Implemented 1 logic cells
 Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 4 warnings
-    Info: Peak virtual memory: 431 megabytes
+    Info: Peak virtual memory: 432 megabytes
-    Info: Processing ended: Wed Mar  1 12:11:00 2023
+    Info: Processing ended: Tue Mar  7 20:30:50 2023
-    Info: Elapsed time: 00:00:13
+    Info: Elapsed time: 00:00:07
-    Info: Total CPU time (on all processors): 00:00:34
+    Info: Total CPU time (on all processors): 00:00:16
 
 

1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.map.summary

@@ -1,4 +1,4 @@
-Analysis & Synthesis Status : Successful - Wed Mar  1 12:11:00 2023
+Analysis & Synthesis Status : Successful - Tue Mar  7 20:30:50 2023
 Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 Revision Name : AND2Gate
 Top-level Entity Name : GateDemo

1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.sta.rpt

@@ -1,5 +1,5 @@
 Timing Analyzer report for AND2Gate
-Wed Mar  1 12:11:27 2023
+Tue Mar  7 20:31:06 2023
 Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 
 
@@ -379,7 +379,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
 Info: *******************************************************************
 Info: Running Quartus Prime Timing Analyzer
     Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-    Info: Processing started: Wed Mar  1 12:11:24 2023
+    Info: Processing started: Tue Mar  7 20:31:04 2023
 Info: Command: quartus_sta VHDLDemo -c AND2Gate
 Info: qsta_default_script.tcl version: #1
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
@@ -427,9 +427,9 @@ Info (332140): No Minimum Pulse Width paths to report
 Info (332102): Design is not fully constrained for setup requirements
 Info (332102): Design is not fully constrained for hold requirements
 Info: Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings
-    Info: Peak virtual memory: 535 megabytes
+    Info: Peak virtual memory: 533 megabytes
-    Info: Processing ended: Wed Mar  1 12:11:27 2023
+    Info: Processing ended: Tue Mar  7 20:31:06 2023
-    Info: Elapsed time: 00:00:03
+    Info: Elapsed time: 00:00:02
-    Info: Total CPU time (on all processors): 00:00:03
+    Info: Total CPU time (on all processors): 00:00:01
 
 

1ano/2semestre/lsd/pratica01/part2/simulation/modelsim/AND2Gate.vho

@@ -17,7 +17,7 @@
 -- PROGRAM "Quartus Prime"
 -- VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
 
--- DATE "03/01/2023 12:11:29"
+-- DATE "03/07/2023 20:31:07"
 
 -- 
 -- Device: Altera EP4CE115F29C7 Package FBGA780
@@ -78,7 +78,7 @@ USE IEEE.STD_LOGIC_1164.ALL;
 ENTITY 	GateDemo IS
     PORT (
 	SW : IN std_logic_vector(1 DOWNTO 0);
-	LEDR : OUT std_logic_vector(1 DOWNTO 0)
+	LEDR : BUFFER std_logic_vector(1 DOWNTO 0)
 	);
 END GateDemo;
 

1ano/2semestre/lsd/pratica01/part2/simulation/modelsim/AND2Gate_modelsim.xrf

@@ -1,14 +1,15 @@
 vendor_name = ModelSim
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/AND2Gate.vhd
+source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/NAND2Block.bdf
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/AND2Gate.vwf
+source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/AND2Gate.vhd
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/GateDemo.vhd
+source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/AND2Gate.vwf
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/NOTGate.vhd
+source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/GateDemo.vhd
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/NAND2Gate.vhd
+source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/NOTGate.vhd
+source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/NAND2Gate.vhd
 source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_b.vhd
 source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_p.vhd
 source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_b.vhd
 source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_p.vhd
-source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/db/AND2Gate.cbx.xml
+source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/db/AND2Gate.cbx.xml
 design_name = hard_block
 design_name = GateDemo
 instance = comp, \LEDR[0]~output\, LEDR[0]~output, GateDemo, 1

1ano/2semestre/lsd/pratica01/part3/LogicTop.qsf

@@ -1178,3 +1178,4 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[5]
 set_location_assignment PIN_D9 -to EX_IO[6]
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[6]
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_global_assignment -name VECTOR_WAVEFORM_FILE LogicUnit.vwf

1ano/2semestre/lsd/pratica01/part3/LogicUnit.vwf

@@ -0,0 +1,368 @@
+/*<simulation_settings>
+<ftestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off LogicDemo -c LogicTop --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/LogicUnit.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicUnit.vwf.vht"</ftestbench_cmd>
+<ttestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off LogicDemo -c LogicTop --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/LogicUnit.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicUnit.vwf.vht"</ttestbench_cmd>
+<fnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/" LogicDemo -c LogicTop</fnetlist_cmd>
+<tnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/" LogicDemo -c LogicTop</tnetlist_cmd>
+<modelsim_script>onerror {exit -code 1}
+vlib work
+vcom -work work LogicTop.vho
+vcom -work work LogicUnit.vwf.vht
+vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.LogicTop_vhd_vec_tst
+vcd file -direction LogicDemo.msim.vcd
+vcd add -internal LogicTop_vhd_vec_tst/*
+vcd add -internal LogicTop_vhd_vec_tst/i1/*
+proc simTimestamp {} {
+    echo "Simulation time: $::now ps"
+    if { [string equal running [runStatus]] } {
+        after 2500 simTimestamp
+    }
+}
+after 2500 simTimestamp
+run -all
+quit -f
+</modelsim_script>
+<modelsim_script_timing>onerror {exit -code 1}
+vlib work
+vcom -work work LogicTop.vho
+vcom -work work LogicUnit.vwf.vht
+vsim -novopt -c -t 1ps -sdfmax LogicTop_vhd_vec_tst/i1=LogicTop_vhd.sdo -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.LogicTop_vhd_vec_tst
+vcd file -direction LogicDemo.msim.vcd
+vcd add -internal LogicTop_vhd_vec_tst/*
+vcd add -internal LogicTop_vhd_vec_tst/i1/*
+proc simTimestamp {} {
+    echo "Simulation time: $::now ps"
+    if { [string equal running [runStatus]] } {
+        after 2500 simTimestamp
+    }
+}
+after 2500 simTimestamp
+run -all
+quit -f
+</modelsim_script_timing>
+<hdl_lang>vhdl</hdl_lang>
+</simulation_settings>*/
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+
+/*
+Copyright (C) 2020  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+*/
+
+HEADER
+{
+	VERSION = 1;
+	TIME_UNIT = ns;
+	DATA_OFFSET = 0.0;
+	DATA_DURATION = 1000.0;
+	SIMULATION_TIME = 0.0;
+	GRID_PHASE = 0.0;
+	GRID_PERIOD = 10.0;
+	GRID_DUTY_CYCLE = 50;
+}
+
+SIGNAL("LEDR")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = BUS;
+	WIDTH = 6;
+	LSB_INDEX = 0;
+	DIRECTION = OUTPUT;
+	PARENT = "";
+}
+
+SIGNAL("LEDR[5]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "LEDR";
+}
+
+SIGNAL("LEDR[4]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "LEDR";
+}
+
+SIGNAL("LEDR[3]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "LEDR";
+}
+
+SIGNAL("LEDR[2]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "LEDR";
+}
+
+SIGNAL("LEDR[1]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "LEDR";
+}
+
+SIGNAL("LEDR[0]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "LEDR";
+}
+
+SIGNAL("SW")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = BUS;
+	WIDTH = 2;
+	LSB_INDEX = 0;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("SW[1]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "SW";
+}
+
+SIGNAL("SW[0]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "SW";
+}
+
+TRANSITION_LIST("LEDR[5]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL X FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("LEDR[4]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL X FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("LEDR[3]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL X FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("LEDR[2]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL X FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("LEDR[1]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL X FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("LEDR[0]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL X FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("SW[1]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		NODE
+		{
+			REPEAT = 1;
+			LEVEL 0 FOR 400.0;
+			LEVEL 1 FOR 400.0;
+		}
+		LEVEL 0 FOR 200.0;
+	}
+}
+
+TRANSITION_LIST("SW[0]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		NODE
+		{
+			REPEAT = 2;
+			LEVEL 0 FOR 200.0;
+			LEVEL 1 FOR 200.0;
+		}
+		LEVEL 0 FOR 200.0;
+	}
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "SW";
+	EXPAND_STATUS = EXPANDED;
+	RADIX = Binary;
+	TREE_INDEX = 0;
+	TREE_LEVEL = 0;
+	CHILDREN = 1, 2;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "SW[1]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 1;
+	TREE_LEVEL = 1;
+	PARENT = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "SW[0]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 2;
+	TREE_LEVEL = 1;
+	PARENT = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "LEDR";
+	EXPAND_STATUS = EXPANDED;
+	RADIX = Binary;
+	TREE_INDEX = 3;
+	TREE_LEVEL = 0;
+	CHILDREN = 4, 5, 6, 7, 8, 9;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "LEDR[5]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 4;
+	TREE_LEVEL = 1;
+	PARENT = 3;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "LEDR[4]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 5;
+	TREE_LEVEL = 1;
+	PARENT = 3;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "LEDR[3]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 6;
+	TREE_LEVEL = 1;
+	PARENT = 3;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "LEDR[2]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 7;
+	TREE_LEVEL = 1;
+	PARENT = 3;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "LEDR[1]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 8;
+	TREE_LEVEL = 1;
+	PARENT = 3;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "LEDR[0]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 9;
+	TREE_LEVEL = 1;
+	PARENT = 3;
+}
+
+TIME_BAR
+{
+	TIME = 0;
+	MASTER = TRUE;
+}
+;

1ano/2semestre/lsd/pratica01/part3/db/LogicTop.db_info

@@ -1,3 +1,3 @@
 Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 Version_Index = 520278016
-Creation_Time = Mon Mar  6 11:43:53 2023
+Creation_Time = Tue Mar  7 20:31:43 2023

1ano/2semestre/lsd/pratica01/part3/db/LogicTop.eda.qmsg

@@ -1,6 +1,6 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678104322872 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678221946677 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678104322872 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar  6 12:05:22 2023 " "Processing started: Mon Mar  6 12:05:22 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678104322872 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1678104322872 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678221946677 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Copyright (C) 2020  Intel Corporation. All rights reserved. " "Copyright (C) 2020  Intel Corporation. All rights reserved." {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678221946677 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Your use of Intel Corporation's design tools, logic functions  " "Your use of Intel Corporation's design tools, logic functions " {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678221946677 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "and other software and tools, and any partner logic  " "and other software and tools, and any partner logic " {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678221946677 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "functions, and any output files from any of the foregoing  " "functions, and any output files from any of the foregoing " {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678221946677 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "(including device programming or simulation files), and any  " "(including device programming or simulation files), and any " {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678221946677 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "associated documentation or information are expressly subject  " "associated documentation or information are expressly subject " {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678221946677 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "to the terms and conditions of the Intel Program License  " "to the terms and conditions of the Intel Program License " {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678221946677 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Subscription Agreement, the Intel Quartus Prime License Agreement, " "Subscription Agreement, the Intel Quartus Prime License Agreement," {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678221946677 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "the Intel FPGA IP License Agreement, or other applicable license " "the Intel FPGA IP License Agreement, or other applicable license" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678221946677 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "agreement, including, without limitation, that your use is for " "agreement, including, without limitation, that your use is for" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678221946677 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "the sole purpose of programming logic devices manufactured by " "the sole purpose of programming logic devices manufactured by" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678221946677 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Intel and sold by Intel or its authorized distributors.  Please " "Intel and sold by Intel or its authorized distributors.  Please" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678221946677 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "refer to the applicable agreement for further details, at " "refer to the applicable agreement for further details, at" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678221946677 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "https://fpgasoftware.intel.com/eula. " "https://fpgasoftware.intel.com/eula." {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678221946677 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar  7 20:45:46 2023 " "Processing started: Tue Mar  7 20:45:46 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678221946677 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1678221946677 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off LogicDemo -c LogicTop " "Command: quartus_eda --read_settings_files=off --write_settings_files=off LogicDemo -c LogicTop" {  } {  } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1678104322872 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/ LogicDemo -c LogicTop " "Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/ LogicDemo -c LogicTop" {  } {  } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1678221946677 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1678104323026 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1678221946861 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "LogicTop.vho /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/modelsim/ simulation " "Generated file LogicTop.vho in folder \"/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1678104323054 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "LogicTop.vho /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim// simulation " "Generated file LogicTop.vho in folder \"/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim//\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1678221946897 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1  Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "612 " "Peak virtual memory: 612 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678104323067 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar  6 12:05:23 2023 " "Processing ended: Mon Mar  6 12:05:23 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678104323067 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678104323067 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678104323067 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1678104323067 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1  Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "613 " "Peak virtual memory: 613 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678221946911 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar  7 20:45:46 2023 " "Processing ended: Tue Mar  7 20:45:46 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678221946911 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678221946911 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678221946911 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1678221946911 ""}

1ano/2semestre/lsd/pratica01/part3/db/LogicTop.smart_action.txt

@@ -1 +1 @@
-DONE
+SOURCE

1ano/2semestre/lsd/pratica01/part3/db/LogicTop.tmw_info

@@ -1,7 +1,4 @@
-start_full_compilation:s:00:00:18
+start_full_compilation:s
-start_analysis_synthesis:s:00:00:06-start_full_compilation
+start_assembler:s-start_full_compilation
-start_analysis_elaboration:s-start_full_compilation
+start_timing_analyzer:s-start_full_compilation
-start_fitter:s:00:00:07-start_full_compilation
+start_eda_netlist_writer:s-start_full_compilation
-start_assembler:s:00:00:03-start_full_compilation
-start_timing_analyzer:s:00:00:01-start_full_compilation
-start_eda_netlist_writer:s:00:00:01-start_full_compilation

1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.eda.rpt

@@ -1,5 +1,5 @@
 EDA Netlist Writer report for LogicTop
-Mon Mar  6 12:05:23 2023
+Tue Mar  7 20:45:46 2023
 Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 
 
@@ -37,7 +37,7 @@ https://fpgasoftware.intel.com/eula.
 +-------------------------------------------------------------------+
 ; EDA Netlist Writer Summary                                        ;
 +---------------------------+---------------------------------------+
-; EDA Netlist Writer Status ; Successful - Mon Mar  6 12:05:23 2023 ;
+; EDA Netlist Writer Status ; Successful - Tue Mar  7 20:45:46 2023 ;
 ; Revision Name             ; LogicTop                              ;
 ; Top-level Entity Name     ; LogicTop                              ;
 ; Family                    ; Cyclone IV E                          ;
@@ -66,13 +66,13 @@ https://fpgasoftware.intel.com/eula.
 +---------------------------------------------------------------------------------------------------+------------------------+
 
 
-+------------------------------------------------------------------------------------------------------+
++---------------------------------------------------------------------------------------------------+
 ; Simulation Generated Files                                                                        ;
-+------------------------------------------------------------------------------------------------------+
++---------------------------------------------------------------------------------------------------+
 ; Generated Files                                                                                   ;
-+------------------------------------------------------------------------------------------------------+
++---------------------------------------------------------------------------------------------------+
-; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/modelsim/LogicTop.vho ;
+; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim//LogicTop.vho ;
-+------------------------------------------------------------------------------------------------------+
++---------------------------------------------------------------------------------------------------+
 
 
 +-----------------------------+
@@ -81,14 +81,28 @@ https://fpgasoftware.intel.com/eula.
 Info: *******************************************************************
 Info: Running Quartus Prime EDA Netlist Writer
     Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
-    Info: Processing started: Mon Mar  6 12:05:22 2023
+    Info: Copyright (C) 2020  Intel Corporation. All rights reserved.
-Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off LogicDemo -c LogicTop
+    Info: Your use of Intel Corporation's design tools, logic functions 
+    Info: and other software and tools, and any partner logic 
+    Info: functions, and any output files from any of the foregoing 
+    Info: (including device programming or simulation files), and any 
+    Info: associated documentation or information are expressly subject 
+    Info: to the terms and conditions of the Intel Program License 
+    Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
+    Info: the Intel FPGA IP License Agreement, or other applicable license
+    Info: agreement, including, without limitation, that your use is for
+    Info: the sole purpose of programming logic devices manufactured by
+    Info: Intel and sold by Intel or its authorized distributors.  Please
+    Info: refer to the applicable agreement for further details, at
+    Info: https://fpgasoftware.intel.com/eula.
+    Info: Processing started: Tue Mar  7 20:45:46 2023
+Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/ LogicDemo -c LogicTop
 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (204019): Generated file LogicTop.vho in folder "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/modelsim/" for EDA simulation tool
+Info (204019): Generated file LogicTop.vho in folder "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim//" for EDA simulation tool
 Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
-    Info: Peak virtual memory: 612 megabytes
+    Info: Peak virtual memory: 613 megabytes
-    Info: Processing ended: Mon Mar  6 12:05:23 2023
+    Info: Processing ended: Tue Mar  7 20:45:46 2023
-    Info: Elapsed time: 00:00:01
+    Info: Elapsed time: 00:00:00
     Info: Total CPU time (on all processors): 00:00:00
 
 

1ano/2semestre/lsd/pratica01/part3/output_files/LogicTop.flow.rpt

@@ -1,5 +1,5 @@
 Flow report for LogicTop
-Mon Mar  6 12:05:23 2023
+Tue Mar  7 20:45:46 2023
 Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
 
 
@@ -41,7 +41,7 @@ https://fpgasoftware.intel.com/eula.
 +----------------------------------------------------------------------------------+
 ; Flow Summary                                                                     ;
 +------------------------------------+---------------------------------------------+
-; Flow Status                        ; Successful - Mon Mar  6 12:05:23 2023       ;
+; Flow Status                        ; Successful - Tue Mar  7 20:45:46 2023       ;
 ; Quartus Prime Version              ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
 ; Revision Name                      ; LogicTop                                    ;
 ; Top-level Entity Name              ; LogicTop                                    ;
@@ -104,7 +104,9 @@ https://fpgasoftware.intel.com/eula.
 ; Assembler            ; 00:00:01     ; 1.0                     ; 366 MB              ; 00:00:02                           ;
 ; Timing Analyzer      ; 00:00:01     ; 1.0                     ; 540 MB              ; 00:00:01                           ;
 ; EDA Netlist Writer   ; 00:00:01     ; 1.0                     ; 612 MB              ; 00:00:00                           ;
-; Total                ; 00:00:15     ; --                      ; --                  ; 00:00:25                           ;
+; EDA Netlist Writer   ; 00:00:01     ; 1.0                     ; 609 MB              ; 00:00:00                           ;
+; EDA Netlist Writer   ; 00:00:00     ; 1.0                     ; 613 MB              ; 00:00:00                           ;
+; Total                ; 00:00:16     ; --                      ; --                  ; 00:00:25                           ;
 +----------------------+--------------+-------------------------+---------------------+------------------------------------+
 
 
@@ -118,6 +120,8 @@ https://fpgasoftware.intel.com/eula.
 ; Assembler            ; rendlaptop       ; Ubuntu 22.04.2 ; 22         ; x86_64         ;
 ; Timing Analyzer      ; rendlaptop       ; Ubuntu 22.04.2 ; 22         ; x86_64         ;
 ; EDA Netlist Writer   ; rendlaptop       ; Ubuntu 22.04.2 ; 22         ; x86_64         ;
+; EDA Netlist Writer   ; rendlaptop       ; Ubuntu 22.04.2 ; 22         ; x86_64         ;
+; EDA Netlist Writer   ; rendlaptop       ; Ubuntu 22.04.2 ; 22         ; x86_64         ;
 +----------------------+------------------+----------------+------------+----------------+
 
 
@@ -129,6 +133,8 @@ quartus_fit --read_settings_files=off --write_settings_files=off LogicDemo -c Lo
 quartus_asm --read_settings_files=off --write_settings_files=off LogicDemo -c LogicTop
 quartus_sta LogicDemo -c LogicTop
 quartus_eda --read_settings_files=off --write_settings_files=off LogicDemo -c LogicTop
+quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off LogicDemo -c LogicTop --vector_source=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/LogicUnit.vwf --testbench_file=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicUnit.vwf.vht
+quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/ LogicDemo -c LogicTop
 
 
 

1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicDemo.do

@@ -0,0 +1,17 @@
+onerror {exit -code 1}
+vlib work
+vcom -work work LogicTop.vho
+vcom -work work LogicUnit.vwf.vht
+vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.LogicTop_vhd_vec_tst
+vcd file -direction LogicDemo.msim.vcd
+vcd add -internal LogicTop_vhd_vec_tst/*
+vcd add -internal LogicTop_vhd_vec_tst/i1/*
+proc simTimestamp {} {
+    echo "Simulation time: $::now ps"
+    if { [string equal running [runStatus]] } {
+        after 2500 simTimestamp
+    }
+}
+after 2500 simTimestamp
+run -all
+quit -f

1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicDemo.msim.vcd

@@ -0,0 +1,180 @@
+$comment
+	File created using the following command:
+		vcd file LogicDemo.msim.vcd -direction
+$end
+$date
+	Tue Mar  7 20:45:48 2023
+$end
+$version
+	ModelSim Version 2020.1
+$end
+$timescale
+	1ps
+$end
+
+$scope module logictop_vhd_vec_tst $end
+$var wire 1 ! LEDR [5] $end
+$var wire 1 " LEDR [4] $end
+$var wire 1 # LEDR [3] $end
+$var wire 1 $ LEDR [2] $end
+$var wire 1 % LEDR [1] $end
+$var wire 1 & LEDR [0] $end
+$var wire 1 ' SW [1] $end
+$var wire 1 ( SW [0] $end
+
+$scope module i1 $end
+$var wire 1 ) gnd $end
+$var wire 1 * vcc $end
+$var wire 1 + unknown $end
+$var wire 1 , devoe $end
+$var wire 1 - devclrn $end
+$var wire 1 . devpor $end
+$var wire 1 / ww_devoe $end
+$var wire 1 0 ww_devclrn $end
+$var wire 1 1 ww_devpor $end
+$var wire 1 2 ww_LEDR [5] $end
+$var wire 1 3 ww_LEDR [4] $end
+$var wire 1 4 ww_LEDR [3] $end
+$var wire 1 5 ww_LEDR [2] $end
+$var wire 1 6 ww_LEDR [1] $end
+$var wire 1 7 ww_LEDR [0] $end
+$var wire 1 8 ww_SW [1] $end
+$var wire 1 9 ww_SW [0] $end
+$var wire 1 : \LEDR[5]~output_o\ $end
+$var wire 1 ; \LEDR[4]~output_o\ $end
+$var wire 1 < \LEDR[3]~output_o\ $end
+$var wire 1 = \LEDR[2]~output_o\ $end
+$var wire 1 > \LEDR[1]~output_o\ $end
+$var wire 1 ? \LEDR[0]~output_o\ $end
+$var wire 1 @ \SW[1]~input_o\ $end
+$var wire 1 A \SW[0]~input_o\ $end
+$var wire 1 B \inst|norOut~0_combout\ $end
+$var wire 1 C \inst|nandOut~0_combout\ $end
+$var wire 1 D \inst|xorOut~combout\ $end
+$var wire 1 E \ALT_INV_SW[0]~input_o\ $end
+$var wire 1 F \inst|ALT_INV_nandOut~0_combout\ $end
+$var wire 1 G \inst|ALT_INV_norOut~0_combout\ $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+0)
+1*
+x+
+1,
+1-
+1.
+1/
+10
+11
+1:
+1;
+0<
+0=
+0>
+1?
+0@
+0A
+0B
+0C
+0D
+1E
+1F
+1G
+0'
+0(
+12
+13
+04
+05
+06
+17
+08
+09
+1!
+1"
+0#
+0$
+0%
+1&
+$end
+#200000
+1(
+19
+1A
+0E
+1B
+1D
+0G
+0?
+1<
+1=
+07
+0:
+14
+15
+0&
+02
+1$
+1#
+0!
+#400000
+0(
+1'
+09
+18
+1@
+0A
+1E
+1?
+17
+1&
+#600000
+1(
+19
+1A
+0E
+1C
+0D
+0F
+0?
+0<
+1>
+07
+0;
+04
+16
+0&
+03
+1%
+0#
+0"
+#800000
+0(
+0'
+09
+08
+0@
+0A
+1E
+0B
+0C
+1F
+1G
+1?
+0>
+0=
+17
+1:
+1;
+06
+05
+1&
+12
+13
+0%
+0$
+1"
+1!
+#1000000

1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicDemo_20230307204548.sim.vwf

@@ -0,0 +1,365 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+
+/*
+Copyright (C) 2020  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+*/
+
+HEADER
+{
+	VERSION = 1;
+	TIME_UNIT = ns;
+	DATA_OFFSET = 0.0;
+	DATA_DURATION = 1000.0;
+	SIMULATION_TIME = 0.0;
+	GRID_PHASE = 0.0;
+	GRID_PERIOD = 10.0;
+	GRID_DUTY_CYCLE = 50;
+}
+
+SIGNAL("LEDR")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = BUS;
+	WIDTH = 6;
+	LSB_INDEX = 0;
+	DIRECTION = OUTPUT;
+	PARENT = "";
+}
+
+SIGNAL("LEDR[5]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "LEDR";
+}
+
+SIGNAL("LEDR[4]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "LEDR";
+}
+
+SIGNAL("LEDR[3]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "LEDR";
+}
+
+SIGNAL("LEDR[2]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "LEDR";
+}
+
+SIGNAL("LEDR[1]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "LEDR";
+}
+
+SIGNAL("LEDR[0]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "LEDR";
+}
+
+SIGNAL("SW")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = BUS;
+	WIDTH = 2;
+	LSB_INDEX = 0;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("SW[1]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "SW";
+}
+
+SIGNAL("SW[0]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "SW";
+}
+
+TRANSITION_LIST("LEDR[5]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		NODE
+		{
+			REPEAT = 1;
+			LEVEL 1 FOR 200.0;
+			LEVEL 0 FOR 600.0;
+			LEVEL 1 FOR 200.0;
+		}
+	}
+}
+
+TRANSITION_LIST("LEDR[4]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		NODE
+		{
+			REPEAT = 1;
+			LEVEL 1 FOR 600.0;
+			LEVEL 0 FOR 200.0;
+			LEVEL 1 FOR 200.0;
+		}
+	}
+}
+
+TRANSITION_LIST("LEDR[3]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		NODE
+		{
+			REPEAT = 1;
+			LEVEL 0 FOR 200.0;
+			LEVEL 1 FOR 400.0;
+			LEVEL 0 FOR 400.0;
+		}
+	}
+}
+
+TRANSITION_LIST("LEDR[2]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		NODE
+		{
+			REPEAT = 1;
+			LEVEL 0 FOR 200.0;
+			LEVEL 1 FOR 600.0;
+			LEVEL 0 FOR 200.0;
+		}
+	}
+}
+
+TRANSITION_LIST("LEDR[1]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		NODE
+		{
+			REPEAT = 1;
+			LEVEL 0 FOR 600.0;
+			LEVEL 1 FOR 200.0;
+			LEVEL 0 FOR 200.0;
+		}
+	}
+}
+
+TRANSITION_LIST("LEDR[0]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		NODE
+		{
+			REPEAT = 1;
+			LEVEL 1 FOR 200.0;
+			LEVEL 0 FOR 200.0;
+			LEVEL 1 FOR 200.0;
+			LEVEL 0 FOR 200.0;
+			LEVEL 1 FOR 200.0;
+		}
+	}
+}
+
+TRANSITION_LIST("SW[1]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		NODE
+		{
+			REPEAT = 1;
+			LEVEL 0 FOR 400.0;
+			LEVEL 1 FOR 400.0;
+			LEVEL 0 FOR 200.0;
+		}
+	}
+}
+
+TRANSITION_LIST("SW[0]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		NODE
+		{
+			REPEAT = 1;
+			LEVEL 0 FOR 200.0;
+			LEVEL 1 FOR 200.0;
+			LEVEL 0 FOR 200.0;
+			LEVEL 1 FOR 200.0;
+			LEVEL 0 FOR 200.0;
+		}
+	}
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "SW";
+	EXPAND_STATUS = EXPANDED;
+	RADIX = Binary;
+	TREE_INDEX = 0;
+	TREE_LEVEL = 0;
+	CHILDREN = 1, 2;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "SW[1]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 1;
+	TREE_LEVEL = 1;
+	PARENT = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "SW[0]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 2;
+	TREE_LEVEL = 1;
+	PARENT = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "LEDR";
+	EXPAND_STATUS = EXPANDED;
+	RADIX = Binary;
+	TREE_INDEX = 3;
+	TREE_LEVEL = 0;
+	CHILDREN = 4, 5, 6, 7, 8, 9;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "LEDR[5]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 4;
+	TREE_LEVEL = 1;
+	PARENT = 3;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "LEDR[4]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 5;
+	TREE_LEVEL = 1;
+	PARENT = 3;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "LEDR[3]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 6;
+	TREE_LEVEL = 1;
+	PARENT = 3;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "LEDR[2]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 7;
+	TREE_LEVEL = 1;
+	PARENT = 3;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "LEDR[1]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 8;
+	TREE_LEVEL = 1;
+	PARENT = 3;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "LEDR[0]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 9;
+	TREE_LEVEL = 1;
+	PARENT = 3;
+}
+
+TIME_BAR
+{
+	TIME = 0;
+	MASTER = TRUE;
+}
+;

1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicTop.sft

@@ -0,0 +1 @@
+set tool_name "ModelSim-Altera (VHDL)"

1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicTop.vho

@@ -0,0 +1,493 @@
+-- Copyright (C) 2020  Intel Corporation. All rights reserved.
+-- Your use of Intel Corporation's design tools, logic functions 
+-- and other software and tools, and any partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Intel Program License 
+-- Subscription Agreement, the Intel Quartus Prime License Agreement,
+-- the Intel FPGA IP License Agreement, or other applicable license
+-- agreement, including, without limitation, that your use is for
+-- the sole purpose of programming logic devices manufactured by
+-- Intel and sold by Intel or its authorized distributors.  Please
+-- refer to the applicable agreement for further details, at
+-- https://fpgasoftware.intel.com/eula.
+
+-- VENDOR "Altera"
+-- PROGRAM "Quartus Prime"
+-- VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
+
+-- DATE "03/07/2023 20:45:46"
+
+-- 
+-- Device: Altera EP4CE115F29C7 Package FBGA780
+-- 
+
+-- 
+-- This VHDL file should be used for ModelSim-Altera (VHDL) only
+-- 
+
+LIBRARY CYCLONEIVE;
+LIBRARY IEEE;
+USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY 	hard_block IS
+    PORT (
+	devoe : IN std_logic;
+	devclrn : IN std_logic;
+	devpor : IN std_logic
+	);
+END hard_block;
+
+-- Design Ports Information
+-- AUD_ADCDAT	=>  Location: PIN_D2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- CLOCK2_50	=>  Location: PIN_AG14,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- CLOCK3_50	=>  Location: PIN_AG15,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- CLOCK_50	=>  Location: PIN_Y2,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- ENET0_INT_N	=>  Location: PIN_A21,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- ENET0_LINK100	=>  Location: PIN_C14,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- ENET0_MDIO	=>  Location: PIN_B21,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- ENET0_RX_CLK	=>  Location: PIN_A15,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- ENET0_RX_COL	=>  Location: PIN_E15,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- ENET0_RX_CRS	=>  Location: PIN_D15,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- ENET0_RX_DATA[0]	=>  Location: PIN_C16,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- ENET0_RX_DATA[1]	=>  Location: PIN_D16,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- ENET0_RX_DATA[2]	=>  Location: PIN_D17,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- ENET0_RX_DATA[3]	=>  Location: PIN_C15,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- ENET0_RX_DV	=>  Location: PIN_C17,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- ENET0_RX_ER	=>  Location: PIN_D18,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- ENET0_TX_CLK	=>  Location: PIN_B17,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- ENET1_INT_N	=>  Location: PIN_D24,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- ENET1_LINK100	=>  Location: PIN_D13,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- ENET1_MDIO	=>  Location: PIN_D25,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- ENET1_RX_CLK	=>  Location: PIN_B15,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- ENET1_RX_COL	=>  Location: PIN_B22,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- ENET1_RX_CRS	=>  Location: PIN_D20,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- ENET1_RX_DATA[0]	=>  Location: PIN_B23,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- ENET1_RX_DATA[1]	=>  Location: PIN_C21,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- ENET1_RX_DATA[2]	=>  Location: PIN_A23,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- ENET1_RX_DATA[3]	=>  Location: PIN_D21,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- ENET1_RX_DV	=>  Location: PIN_A22,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- ENET1_RX_ER	=>  Location: PIN_C24,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- ENET1_TX_CLK	=>  Location: PIN_C22,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- ENETCLK_25	=>  Location: PIN_A14,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- FL_RY	=>  Location: PIN_Y1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- HSMC_CLKIN0	=>  Location: PIN_AH15,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- IRDA_RXD	=>  Location: PIN_Y15,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- KEY[0]	=>  Location: PIN_M23,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- KEY[1]	=>  Location: PIN_M21,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- KEY[2]	=>  Location: PIN_N21,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- KEY[3]	=>  Location: PIN_R24,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- OTG_INT	=>  Location: PIN_D5,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- SD_WP_N	=>  Location: PIN_AF14,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- SMA_CLKIN	=>  Location: PIN_AH14,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- SW[10]	=>  Location: PIN_AC24,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- SW[11]	=>  Location: PIN_AB24,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- SW[12]	=>  Location: PIN_AB23,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- SW[13]	=>  Location: PIN_AA24,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- SW[14]	=>  Location: PIN_AA23,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- SW[15]	=>  Location: PIN_AA22,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- SW[16]	=>  Location: PIN_Y24,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- SW[17]	=>  Location: PIN_Y23,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- SW[2]	=>  Location: PIN_AC27,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- SW[3]	=>  Location: PIN_AD27,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- SW[4]	=>  Location: PIN_AB27,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- SW[5]	=>  Location: PIN_AC26,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- SW[6]	=>  Location: PIN_AD26,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- SW[7]	=>  Location: PIN_AB26,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- SW[8]	=>  Location: PIN_AC25,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- SW[9]	=>  Location: PIN_AB25,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- TD_CLK27	=>  Location: PIN_B14,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- TD_DATA[0]	=>  Location: PIN_E8,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- TD_DATA[1]	=>  Location: PIN_A7,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- TD_DATA[2]	=>  Location: PIN_D8,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- TD_DATA[3]	=>  Location: PIN_C7,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- TD_DATA[4]	=>  Location: PIN_D7,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- TD_DATA[5]	=>  Location: PIN_D6,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- TD_DATA[6]	=>  Location: PIN_E7,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- TD_DATA[7]	=>  Location: PIN_F7,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- TD_HS	=>  Location: PIN_E5,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- TD_VS	=>  Location: PIN_E4,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- UART_RTS	=>  Location: PIN_J13,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- UART_RXD	=>  Location: PIN_G12,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- ~ALTERA_ASDO_DATA1~	=>  Location: PIN_F4,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- ~ALTERA_FLASH_nCE_nCSO~	=>  Location: PIN_E2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- ~ALTERA_DCLK~	=>  Location: PIN_P3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- ~ALTERA_DATA0~	=>  Location: PIN_N7,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
+-- ~ALTERA_nCEO~	=>  Location: PIN_P28,	 I/O Standard: 2.5 V,	 Current Strength: 8mA
+
+
+ARCHITECTURE structure OF hard_block IS
+SIGNAL gnd : std_logic := '0';
+SIGNAL vcc : std_logic := '1';
+SIGNAL unknown : std_logic := 'X';
+SIGNAL ww_devoe : std_logic;
+SIGNAL ww_devclrn : std_logic;
+SIGNAL ww_devpor : std_logic;
+SIGNAL \AUD_ADCDAT~padout\ : std_logic;
+SIGNAL \CLOCK2_50~padout\ : std_logic;
+SIGNAL \CLOCK3_50~padout\ : std_logic;
+SIGNAL \CLOCK_50~padout\ : std_logic;
+SIGNAL \ENET0_INT_N~padout\ : std_logic;
+SIGNAL \ENET0_LINK100~padout\ : std_logic;
+SIGNAL \ENET0_MDIO~padout\ : std_logic;
+SIGNAL \ENET0_RX_CLK~padout\ : std_logic;
+SIGNAL \ENET0_RX_COL~padout\ : std_logic;
+SIGNAL \ENET0_RX_CRS~padout\ : std_logic;
+SIGNAL \ENET0_RX_DATA[0]~padout\ : std_logic;
+SIGNAL \ENET0_RX_DATA[1]~padout\ : std_logic;
+SIGNAL \ENET0_RX_DATA[2]~padout\ : std_logic;
+SIGNAL \ENET0_RX_DATA[3]~padout\ : std_logic;
+SIGNAL \ENET0_RX_DV~padout\ : std_logic;
+SIGNAL \ENET0_RX_ER~padout\ : std_logic;
+SIGNAL \ENET0_TX_CLK~padout\ : std_logic;
+SIGNAL \ENET1_INT_N~padout\ : std_logic;
+SIGNAL \ENET1_LINK100~padout\ : std_logic;
+SIGNAL \ENET1_MDIO~padout\ : std_logic;
+SIGNAL \ENET1_RX_CLK~padout\ : std_logic;
+SIGNAL \ENET1_RX_COL~padout\ : std_logic;
+SIGNAL \ENET1_RX_CRS~padout\ : std_logic;
+SIGNAL \ENET1_RX_DATA[0]~padout\ : std_logic;
+SIGNAL \ENET1_RX_DATA[1]~padout\ : std_logic;
+SIGNAL \ENET1_RX_DATA[2]~padout\ : std_logic;
+SIGNAL \ENET1_RX_DATA[3]~padout\ : std_logic;
+SIGNAL \ENET1_RX_DV~padout\ : std_logic;
+SIGNAL \ENET1_RX_ER~padout\ : std_logic;
+SIGNAL \ENET1_TX_CLK~padout\ : std_logic;
+SIGNAL \ENETCLK_25~padout\ : std_logic;
+SIGNAL \FL_RY~padout\ : std_logic;
+SIGNAL \HSMC_CLKIN0~padout\ : std_logic;
+SIGNAL \IRDA_RXD~padout\ : std_logic;
+SIGNAL \KEY[0]~padout\ : std_logic;
+SIGNAL \KEY[1]~padout\ : std_logic;
+SIGNAL \KEY[2]~padout\ : std_logic;
+SIGNAL \KEY[3]~padout\ : std_logic;
+SIGNAL \OTG_INT~padout\ : std_logic;
+SIGNAL \SD_WP_N~padout\ : std_logic;
+SIGNAL \SMA_CLKIN~padout\ : std_logic;
+SIGNAL \TD_CLK27~padout\ : std_logic;
+SIGNAL \TD_DATA[0]~padout\ : std_logic;
+SIGNAL \TD_DATA[1]~padout\ : std_logic;
+SIGNAL \TD_DATA[2]~padout\ : std_logic;
+SIGNAL \TD_DATA[3]~padout\ : std_logic;
+SIGNAL \TD_DATA[4]~padout\ : std_logic;
+SIGNAL \TD_DATA[5]~padout\ : std_logic;
+SIGNAL \TD_DATA[6]~padout\ : std_logic;
+SIGNAL \TD_DATA[7]~padout\ : std_logic;
+SIGNAL \TD_HS~padout\ : std_logic;
+SIGNAL \TD_VS~padout\ : std_logic;
+SIGNAL \UART_RTS~padout\ : std_logic;
+SIGNAL \UART_RXD~padout\ : std_logic;
+SIGNAL \~ALTERA_ASDO_DATA1~~padout\ : std_logic;
+SIGNAL \~ALTERA_FLASH_nCE_nCSO~~padout\ : std_logic;
+SIGNAL \~ALTERA_DATA0~~padout\ : std_logic;
+SIGNAL \AUD_ADCDAT~ibuf_o\ : std_logic;
+SIGNAL \CLOCK2_50~ibuf_o\ : std_logic;
+SIGNAL \CLOCK3_50~ibuf_o\ : std_logic;
+SIGNAL \CLOCK_50~ibuf_o\ : std_logic;
+SIGNAL \ENET0_INT_N~ibuf_o\ : std_logic;
+SIGNAL \ENET0_LINK100~ibuf_o\ : std_logic;
+SIGNAL \ENET0_MDIO~ibuf_o\ : std_logic;
+SIGNAL \ENET0_RX_CLK~ibuf_o\ : std_logic;
+SIGNAL \ENET0_RX_COL~ibuf_o\ : std_logic;
+SIGNAL \ENET0_RX_CRS~ibuf_o\ : std_logic;
+SIGNAL \ENET0_RX_DATA[0]~ibuf_o\ : std_logic;
+SIGNAL \ENET0_RX_DATA[1]~ibuf_o\ : std_logic;
+SIGNAL \ENET0_RX_DATA[2]~ibuf_o\ : std_logic;
+SIGNAL \ENET0_RX_DATA[3]~ibuf_o\ : std_logic;
+SIGNAL \ENET0_RX_DV~ibuf_o\ : std_logic;
+SIGNAL \ENET0_RX_ER~ibuf_o\ : std_logic;
+SIGNAL \ENET0_TX_CLK~ibuf_o\ : std_logic;
+SIGNAL \ENET1_INT_N~ibuf_o\ : std_logic;
+SIGNAL \ENET1_LINK100~ibuf_o\ : std_logic;
+SIGNAL \ENET1_MDIO~ibuf_o\ : std_logic;
+SIGNAL \ENET1_RX_CLK~ibuf_o\ : std_logic;
+SIGNAL \ENET1_RX_COL~ibuf_o\ : std_logic;
+SIGNAL \ENET1_RX_CRS~ibuf_o\ : std_logic;
+SIGNAL \ENET1_RX_DATA[0]~ibuf_o\ : std_logic;
+SIGNAL \ENET1_RX_DATA[1]~ibuf_o\ : std_logic;
+SIGNAL \ENET1_RX_DATA[2]~ibuf_o\ : std_logic;
+SIGNAL \ENET1_RX_DATA[3]~ibuf_o\ : std_logic;
+SIGNAL \ENET1_RX_DV~ibuf_o\ : std_logic;
+SIGNAL \ENET1_RX_ER~ibuf_o\ : std_logic;
+SIGNAL \ENET1_TX_CLK~ibuf_o\ : std_logic;
+SIGNAL \ENETCLK_25~ibuf_o\ : std_logic;
+SIGNAL \FL_RY~ibuf_o\ : std_logic;
+SIGNAL \HSMC_CLKIN0~ibuf_o\ : std_logic;
+SIGNAL \IRDA_RXD~ibuf_o\ : std_logic;
+SIGNAL \KEY[0]~ibuf_o\ : std_logic;
+SIGNAL \KEY[1]~ibuf_o\ : std_logic;
+SIGNAL \KEY[2]~ibuf_o\ : std_logic;
+SIGNAL \KEY[3]~ibuf_o\ : std_logic;
+SIGNAL \OTG_INT~ibuf_o\ : std_logic;
+SIGNAL \SD_WP_N~ibuf_o\ : std_logic;
+SIGNAL \SMA_CLKIN~ibuf_o\ : std_logic;
+SIGNAL \SW[10]~ibuf_o\ : std_logic;
+SIGNAL \SW[11]~ibuf_o\ : std_logic;
+SIGNAL \SW[12]~ibuf_o\ : std_logic;
+SIGNAL \SW[13]~ibuf_o\ : std_logic;
+SIGNAL \SW[14]~ibuf_o\ : std_logic;
+SIGNAL \SW[15]~ibuf_o\ : std_logic;
+SIGNAL \SW[16]~ibuf_o\ : std_logic;
+SIGNAL \SW[17]~ibuf_o\ : std_logic;
+SIGNAL \SW[2]~ibuf_o\ : std_logic;
+SIGNAL \SW[3]~ibuf_o\ : std_logic;
+SIGNAL \SW[4]~ibuf_o\ : std_logic;
+SIGNAL \SW[5]~ibuf_o\ : std_logic;
+SIGNAL \SW[6]~ibuf_o\ : std_logic;
+SIGNAL \SW[7]~ibuf_o\ : std_logic;
+SIGNAL \SW[8]~ibuf_o\ : std_logic;
+SIGNAL \SW[9]~ibuf_o\ : std_logic;
+SIGNAL \TD_CLK27~ibuf_o\ : std_logic;
+SIGNAL \TD_DATA[0]~ibuf_o\ : std_logic;
+SIGNAL \TD_DATA[1]~ibuf_o\ : std_logic;
+SIGNAL \TD_DATA[2]~ibuf_o\ : std_logic;
+SIGNAL \TD_DATA[3]~ibuf_o\ : std_logic;
+SIGNAL \TD_DATA[4]~ibuf_o\ : std_logic;
+SIGNAL \TD_DATA[5]~ibuf_o\ : std_logic;
+SIGNAL \TD_DATA[6]~ibuf_o\ : std_logic;
+SIGNAL \TD_DATA[7]~ibuf_o\ : std_logic;
+SIGNAL \TD_HS~ibuf_o\ : std_logic;
+SIGNAL \TD_VS~ibuf_o\ : std_logic;
+SIGNAL \UART_RTS~ibuf_o\ : std_logic;
+SIGNAL \UART_RXD~ibuf_o\ : std_logic;
+SIGNAL \~ALTERA_ASDO_DATA1~~ibuf_o\ : std_logic;
+SIGNAL \~ALTERA_FLASH_nCE_nCSO~~ibuf_o\ : std_logic;
+SIGNAL \~ALTERA_DATA0~~ibuf_o\ : std_logic;
+SIGNAL SW : std_logic_vector(1 DOWNTO 0);
+
+BEGIN
+
+ww_devoe <= devoe;
+ww_devclrn <= devclrn;
+ww_devpor <= devpor;
+END structure;
+
+
+LIBRARY CYCLONEIVE;
+LIBRARY IEEE;
+USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY 	LogicTop IS
+    PORT (
+	LEDR : OUT std_logic_vector(5 DOWNTO 0);
+	SW : IN std_logic_vector(1 DOWNTO 0)
+	);
+END LogicTop;
+
+-- Design Ports Information
+-- LEDR[5]	=>  Location: PIN_E18,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- LEDR[4]	=>  Location: PIN_F18,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- LEDR[3]	=>  Location: PIN_F21,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- LEDR[2]	=>  Location: PIN_E19,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- LEDR[1]	=>  Location: PIN_F19,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- LEDR[0]	=>  Location: PIN_G19,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- SW[1]	=>  Location: PIN_AC28,	 I/O Standard: 2.5 V,	 Current Strength: Default
+-- SW[0]	=>  Location: PIN_AB28,	 I/O Standard: 2.5 V,	 Current Strength: Default
+
+
+ARCHITECTURE structure OF LogicTop IS
+SIGNAL gnd : std_logic := '0';
+SIGNAL vcc : std_logic := '1';
+SIGNAL unknown : std_logic := 'X';
+SIGNAL devoe : std_logic := '1';
+SIGNAL devclrn : std_logic := '1';
+SIGNAL devpor : std_logic := '1';
+SIGNAL ww_devoe : std_logic;
+SIGNAL ww_devclrn : std_logic;
+SIGNAL ww_devpor : std_logic;
+SIGNAL ww_LEDR : std_logic_vector(5 DOWNTO 0);
+SIGNAL ww_SW : std_logic_vector(1 DOWNTO 0);
+SIGNAL \LEDR[5]~output_o\ : std_logic;
+SIGNAL \LEDR[4]~output_o\ : std_logic;
+SIGNAL \LEDR[3]~output_o\ : std_logic;
+SIGNAL \LEDR[2]~output_o\ : std_logic;
+SIGNAL \LEDR[1]~output_o\ : std_logic;
+SIGNAL \LEDR[0]~output_o\ : std_logic;
+SIGNAL \SW[1]~input_o\ : std_logic;
+SIGNAL \SW[0]~input_o\ : std_logic;
+SIGNAL \inst|norOut~0_combout\ : std_logic;
+SIGNAL \inst|nandOut~0_combout\ : std_logic;
+SIGNAL \inst|xorOut~combout\ : std_logic;
+SIGNAL \ALT_INV_SW[0]~input_o\ : std_logic;
+SIGNAL \inst|ALT_INV_nandOut~0_combout\ : std_logic;
+SIGNAL \inst|ALT_INV_norOut~0_combout\ : std_logic;
+
+COMPONENT hard_block
+    PORT (
+	devoe : IN std_logic;
+	devclrn : IN std_logic;
+	devpor : IN std_logic);
+END COMPONENT;
+
+BEGIN
+
+LEDR <= ww_LEDR;
+ww_SW <= SW;
+ww_devoe <= devoe;
+ww_devclrn <= devclrn;
+ww_devpor <= devpor;
+\ALT_INV_SW[0]~input_o\ <= NOT \SW[0]~input_o\;
+\inst|ALT_INV_nandOut~0_combout\ <= NOT \inst|nandOut~0_combout\;
+\inst|ALT_INV_norOut~0_combout\ <= NOT \inst|norOut~0_combout\;
+auto_generated_inst : hard_block
+PORT MAP (
+	devoe => ww_devoe,
+	devclrn => ww_devclrn,
+	devpor => ww_devpor);
+
+-- Location: IOOBUF_X87_Y73_N9
+\LEDR[5]~output\ : cycloneive_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst|ALT_INV_norOut~0_combout\,
+	devoe => ww_devoe,
+	o => \LEDR[5]~output_o\);
+
+-- Location: IOOBUF_X87_Y73_N16
+\LEDR[4]~output\ : cycloneive_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst|ALT_INV_nandOut~0_combout\,
+	devoe => ww_devoe,
+	o => \LEDR[4]~output_o\);
+
+-- Location: IOOBUF_X107_Y73_N16
+\LEDR[3]~output\ : cycloneive_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst|xorOut~combout\,
+	devoe => ww_devoe,
+	o => \LEDR[3]~output_o\);
+
+-- Location: IOOBUF_X94_Y73_N9
+\LEDR[2]~output\ : cycloneive_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst|norOut~0_combout\,
+	devoe => ww_devoe,
+	o => \LEDR[2]~output_o\);
+
+-- Location: IOOBUF_X94_Y73_N2
+\LEDR[1]~output\ : cycloneive_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \inst|nandOut~0_combout\,
+	devoe => ww_devoe,
+	o => \LEDR[1]~output_o\);
+
+-- Location: IOOBUF_X69_Y73_N16
+\LEDR[0]~output\ : cycloneive_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+	i => \ALT_INV_SW[0]~input_o\,
+	devoe => ww_devoe,
+	o => \LEDR[0]~output_o\);
+
+-- Location: IOIBUF_X115_Y14_N1
+\SW[1]~input\ : cycloneive_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_SW(1),
+	o => \SW[1]~input_o\);
+
+-- Location: IOIBUF_X115_Y17_N1
+\SW[0]~input\ : cycloneive_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+	bus_hold => "false",
+	simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+	i => ww_SW(0),
+	o => \SW[0]~input_o\);
+
+-- Location: LCCOMB_X95_Y72_N16
+\inst|norOut~0\ : cycloneive_lcell_comb
+-- Equation(s):
+-- \inst|norOut~0_combout\ = (\SW[1]~input_o\) # (\SW[0]~input_o\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1111111111001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \SW[1]~input_o\,
+	datad => \SW[0]~input_o\,
+	combout => \inst|norOut~0_combout\);
+
+-- Location: LCCOMB_X95_Y72_N10
+\inst|nandOut~0\ : cycloneive_lcell_comb
+-- Equation(s):
+-- \inst|nandOut~0_combout\ = (\SW[1]~input_o\ & \SW[0]~input_o\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "1100110000000000",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \SW[1]~input_o\,
+	datad => \SW[0]~input_o\,
+	combout => \inst|nandOut~0_combout\);
+
+-- Location: LCCOMB_X95_Y72_N28
+\inst|xorOut\ : cycloneive_lcell_comb
+-- Equation(s):
+-- \inst|xorOut~combout\ = \SW[1]~input_o\ $ (\SW[0]~input_o\)
+
+-- pragma translate_off
+GENERIC MAP (
+	lut_mask => "0011001111001100",
+	sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+	datab => \SW[1]~input_o\,
+	datad => \SW[0]~input_o\,
+	combout => \inst|xorOut~combout\);
+
+ww_LEDR(5) <= \LEDR[5]~output_o\;
+
+ww_LEDR(4) <= \LEDR[4]~output_o\;
+
+ww_LEDR(3) <= \LEDR[3]~output_o\;
+
+ww_LEDR(2) <= \LEDR[2]~output_o\;
+
+ww_LEDR(1) <= \LEDR[1]~output_o\;
+
+ww_LEDR(0) <= \LEDR[0]~output_o\;
+END structure;
+
+

1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicTop_modelsim.xrf

@@ -0,0 +1,21 @@
+vendor_name = ModelSim
+source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/LogicUnit.vhd
+source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/LogicTop.bdf
+source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_b.vhd
+source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_p.vhd
+source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_b.vhd
+source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_p.vhd
+source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.cbx.xml
+design_name = hard_block
+design_name = LogicTop
+instance = comp, \LEDR[5]~output\, LEDR[5]~output, LogicTop, 1
+instance = comp, \LEDR[4]~output\, LEDR[4]~output, LogicTop, 1
+instance = comp, \LEDR[3]~output\, LEDR[3]~output, LogicTop, 1
+instance = comp, \LEDR[2]~output\, LEDR[2]~output, LogicTop, 1
+instance = comp, \LEDR[1]~output\, LEDR[1]~output, LogicTop, 1
+instance = comp, \LEDR[0]~output\, LEDR[0]~output, LogicTop, 1
+instance = comp, \SW[1]~input\, SW[1]~input, LogicTop, 1
+instance = comp, \SW[0]~input\, SW[0]~input, LogicTop, 1
+instance = comp, \inst|norOut~0\, inst|norOut~0, LogicTop, 1
+instance = comp, \inst|nandOut~0\, inst|nandOut~0, LogicTop, 1
+instance = comp, \inst|xorOut\, inst|xorOut, LogicTop, 1

1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicUnit.vwf.vht

@@ -0,0 +1,75 @@
+-- Copyright (C) 2020  Intel Corporation. All rights reserved.
+-- Your use of Intel Corporation's design tools, logic functions 
+-- and other software and tools, and any partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Intel Program License 
+-- Subscription Agreement, the Intel Quartus Prime License Agreement,
+-- the Intel FPGA IP License Agreement, or other applicable license
+-- agreement, including, without limitation, that your use is for
+-- the sole purpose of programming logic devices manufactured by
+-- Intel and sold by Intel or its authorized distributors.  Please
+-- refer to the applicable agreement for further details, at
+-- https://fpgasoftware.intel.com/eula.
+
+-- *****************************************************************************
+-- This file contains a Vhdl test bench with test vectors .The test vectors     
+-- are exported from a vector file in the Quartus Waveform Editor and apply to  
+-- the top level entity of the current Quartus project .The user can use this   
+-- testbench to simulate his design using a third-party simulation tool .       
+-- *****************************************************************************
+-- Generated on "03/07/2023 20:45:46"
+                                                             
+-- Vhdl Test Bench(with test vectors) for design  :          LogicTop
+-- 
+-- Simulation tool : 3rd Party
+-- 
+
+LIBRARY ieee;                                               
+USE ieee.std_logic_1164.all;                                
+
+ENTITY LogicTop_vhd_vec_tst IS
+END LogicTop_vhd_vec_tst;
+ARCHITECTURE LogicTop_arch OF LogicTop_vhd_vec_tst IS
+-- constants                                                 
+-- signals                                                   
+SIGNAL LEDR : STD_LOGIC_VECTOR(5 DOWNTO 0);
+SIGNAL SW : STD_LOGIC_VECTOR(1 DOWNTO 0);
+COMPONENT LogicTop
+	PORT (
+	LEDR : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
+	SW : IN STD_LOGIC_VECTOR(1 DOWNTO 0)
+	);
+END COMPONENT;
+BEGIN
+	i1 : LogicTop
+	PORT MAP (
+-- list connections between master ports and signals
+	LEDR => LEDR,
+	SW => SW
+	);
+-- SW[1]
+t_prcs_SW_1: PROCESS
+BEGIN
+	SW(1) <= '0';
+	WAIT FOR 400000 ps;
+	SW(1) <= '1';
+	WAIT FOR 400000 ps;
+	SW(1) <= '0';
+WAIT;
+END PROCESS t_prcs_SW_1;
+-- SW[0]
+t_prcs_SW_0: PROCESS
+BEGIN
+	FOR i IN 1 TO 2
+	LOOP
+		SW(0) <= '0';
+		WAIT FOR 200000 ps;
+		SW(0) <= '1';
+		WAIT FOR 200000 ps;
+	END LOOP;
+	SW(0) <= '0';
+WAIT;
+END PROCESS t_prcs_SW_0;
+END LogicTop_arch;

1ano/2semestre/lsd/pratica01/part3/simulation/qsim/transcript

@@ -0,0 +1,46 @@
+# do LogicDemo.do
+# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
+# Start time: 20:45:47 on Mar 07,2023
+# vcom -work work LogicTop.vho 
+# -- Loading package STANDARD
+# -- Loading package TEXTIO
+# -- Loading package std_logic_1164
+# -- Loading package VITAL_Timing
+# -- Loading package VITAL_Primitives
+# -- Loading package cycloneive_atom_pack
+# -- Loading package cycloneive_components
+# -- Compiling entity hard_block
+# -- Compiling architecture structure of hard_block
+# -- Compiling entity LogicTop
+# -- Compiling architecture structure of LogicTop
+# End time: 20:45:47 on Mar 07,2023, Elapsed time: 0:00:00
+# Errors: 0, Warnings: 0
+# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
+# Start time: 20:45:47 on Mar 07,2023
+# vcom -work work LogicUnit.vwf.vht 
+# -- Loading package STANDARD
+# -- Loading package TEXTIO
+# -- Loading package std_logic_1164
+# -- Compiling entity LogicTop_vhd_vec_tst
+# -- Compiling architecture LogicTop_arch of LogicTop_vhd_vec_tst
+# End time: 20:45:47 on Mar 07,2023, Elapsed time: 0:00:00
+# Errors: 0, Warnings: 0
+# vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.LogicTop_vhd_vec_tst 
+# Start time: 20:45:47 on Mar 07,2023
+# Loading std.standard
+# Loading std.textio(body)
+# Loading ieee.std_logic_1164(body)
+# Loading work.logictop_vhd_vec_tst(logictop_arch)
+# Loading ieee.vital_timing(body)
+# Loading ieee.vital_primitives(body)
+# Loading cycloneive.cycloneive_atom_pack(body)
+# Loading cycloneive.cycloneive_components
+# Loading work.logictop(structure)
+# Loading work.hard_block(structure)
+# Loading ieee.std_logic_arith(body)
+# Loading cycloneive.cycloneive_io_obuf(arch)
+# Loading cycloneive.cycloneive_io_ibuf(arch)
+# Loading cycloneive.cycloneive_lcell_comb(vital_lcell_comb)
+# after#31
+# End time: 20:45:48 on Mar 07,2023, Elapsed time: 0:00:01
+# Errors: 0, Warnings: 0

1ano/2semestre/lsd/pratica01/part3/simulation/qsim/vwf_sim_transcript

@@ -0,0 +1,66 @@
+Determining the location of the ModelSim executable...
+
+Using: /home/tiagorg/intelFPGA_lite/20.1/modelsim_ase/linuxaloem/
+
+To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options
+Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used.
+
+**** Generating the ModelSim Testbench ****
+
+quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off LogicDemo -c LogicTop --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/LogicUnit.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicUnit.vwf.vht"
+
+Info: *******************************************************************Info: Running Quartus Prime EDA Netlist Writer    Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition    Info: Copyright (C) 2020  Intel Corporation. All rights reserved.    Info: Your use of Intel Corporation's design tools, logic functions     Info: and other software and tools, and any partner logic     Info: functions, and any output files from any of the foregoing     Info: (including device programming or simulation files), and any     Info: associated documentation or information are expressly subject     Info: to the terms and conditions of the Intel Program License     Info: Subscription Agreement, the Intel Quartus Prime License Agreement,    Info: the Intel FPGA IP License Agreement, or other applicable license    Info: agreement, including, without limitation, that your use is for    Info: the sole purpose of programming logic devices manufactured by    Info: Intel and sold by Intel or its authorized distributors.  Please    Info: refer to the applicable agreement for further details, at    Info: https://fpgasoftware.intel.com/eula.    Info: Processing started: Tue Mar  7 20:45:45 2023Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off LogicDemo -c LogicTop --vector_source=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/LogicUnit.vwf --testbench_file=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicUnit.vwf.vhtWarning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Completed successfully. 
+
+**** Generating the functional simulation netlist ****
+
+quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/" LogicDemo -c LogicTop
+
+Info: *******************************************************************Info: Running Quartus Prime EDA Netlist Writer    Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition    Info: Copyright (C) 2020  Intel Corporation. All rights reserved.    Info: Your use of Intel Corporation's design tools, logic functions     Info: and other software and tools, and any partner logic     Info: functions, and any output files from any of the foregoing     Info: (including device programming or simulation files), and any     Info: associated documentation or information are expressly subject     Info: to the terms and conditions of the Intel Program License     Info: Subscription Agreement, the Intel Quartus Prime License Agreement,    Info: the Intel FPGA IP License Agreement, or other applicable license    Info: agreement, including, without limitation, that your use is for    Info: the sole purpose of programming logic devices manufactured by    Info: Intel and sold by Intel or its authorized distributors.  Please    Info: refer to the applicable agreement for further details, at    Info: https://fpgasoftware.intel.com/eula.    Info: Processing started: Tue Mar  7 20:45:46 2023Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/ LogicDemo -c LogicTopWarning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.Info (204019): Generated file LogicTop.vho in folder "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim//" for EDA simulation toolInfo: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning    Info: Peak virtual memory: 613 megabytes    Info: Processing ended: Tue Mar  7 20:45:46 2023    Info: Elapsed time: 00:00:00    Info: Total CPU time (on all processors): 00:00:00
+Completed successfully. 
+
+**** Generating the ModelSim .do script ****
+
+/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicDemo.do generated.
+
+Completed successfully. 
+
+**** Running the ModelSim simulation ****
+
+/home/tiagorg/intelFPGA_lite/20.1/modelsim_ase/linuxaloem//vsim -c -do LogicDemo.do
+
+Reading pref.tcl
+# 2020.1
+# do LogicDemo.do
+# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
+# Start time: 20:45:47 on Mar 07,2023# vcom -work work LogicTop.vho 
+# -- Loading package STANDARD
+# -- Loading package TEXTIO
+# -- Loading package std_logic_1164# -- Loading package VITAL_Timing# -- Loading package VITAL_Primitives# -- Loading package cycloneive_atom_pack# -- Loading package cycloneive_components
+# -- Compiling entity hard_block# -- Compiling architecture structure of hard_block
+# -- Compiling entity LogicTop
+# -- Compiling architecture structure of LogicTop
+# End time: 20:45:47 on Mar 07,2023, Elapsed time: 0:00:00# Errors: 0, Warnings: 0
+# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
+# Start time: 20:45:47 on Mar 07,2023# vcom -work work LogicUnit.vwf.vht # -- Loading package STANDARD# -- Loading package TEXTIO# -- Loading package std_logic_1164
+# -- Compiling entity LogicTop_vhd_vec_tst# -- Compiling architecture LogicTop_arch of LogicTop_vhd_vec_tst# End time: 20:45:47 on Mar 07,2023, Elapsed time: 0:00:00# Errors: 0, Warnings: 0
+# vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.LogicTop_vhd_vec_tst # Start time: 20:45:47 on Mar 07,2023# Loading std.standard# Loading std.textio(body)# Loading ieee.std_logic_1164(body)# Loading work.logictop_vhd_vec_tst(logictop_arch)# Loading ieee.vital_timing(body)# Loading ieee.vital_primitives(body)# Loading cycloneive.cycloneive_atom_pack(body)# Loading cycloneive.cycloneive_components# Loading work.logictop(structure)# Loading work.hard_block(structure)# Loading ieee.std_logic_arith(body)# Loading cycloneive.cycloneive_io_obuf(arch)# Loading cycloneive.cycloneive_io_ibuf(arch)# Loading cycloneive.cycloneive_lcell_comb(vital_lcell_comb)
+# after#31
+# End time: 20:45:48 on Mar 07,2023, Elapsed time: 0:00:01# Errors: 0, Warnings: 0
+Completed successfully. 
+
+**** Converting ModelSim VCD to vector waveform ****
+
+Reading /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/LogicUnit.vwf...
+
+Reading /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicDemo.msim.vcd...
+
+Processing channel transitions... 
+
+Writing the resulting VWF to /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/simulation/qsim/LogicDemo_20230307204548.sim.vwf
+
+Finished VCD to VWF conversion.
+
+Completed successfully. 
+
+All completed.

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+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
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+		(text "IN4" (rect 2 55 23 66)(font "Courier New" (bold))(invisible))
+		(text "IN4" (rect 2 55 23 66)(font "Courier New" (bold))(invisible))
+		(line (pt 0 64)(pt 18 64))
+	)
+	(port
+		(pt 64 40)
+		(output)
+		(text "OUT" (rect 48 31 69 42)(font "Courier New" (bold))(invisible))
+		(text "OUT" (rect 48 31 69 42)(font "Courier New" (bold))(invisible))
+		(line (pt 46 40)(pt 64 40))
+	)
+	(drawing
+		(line (pt 18 28)(pt 34 28))
+		(line (pt 18 52)(pt 18 28))
+		(line (pt 18 67)(pt 18 13))
+		(line (pt 34 53)(pt 18 53))
+		(arc (pt 34 52)(pt 34 28)(rect 22 28 47 53))
+	)
+)
+(connector
+	(pt 592 304)
+	(pt 600 304)
+)
+(connector
+	(pt 512 248)
+	(pt 512 280)
+)
+(connector
+	(pt 512 280)
+	(pt 528 280)
+)
+(connector
+	(pt 448 248)
+	(pt 448 296)
+)
+(connector
+	(pt 448 296)
+	(pt 528 296)
+)
+(connector
+	(pt 384 248)
+	(pt 384 312)
+)
+(connector
+	(pt 384 312)
+	(pt 528 312)
+)
+(connector
+	(pt 320 248)
+	(pt 320 328)
+)
+(connector
+	(pt 320 328)
+	(pt 528 328)
+)
+(connector
+	(pt 288 160)
+	(pt 312 160)
+	(bus)
+)
+(connector
+	(pt 312 160)
+	(pt 376 160)
+	(bus)
+)
+(connector
+	(pt 376 160)
+	(pt 440 160)
+	(bus)
+)
+(connector
+	(pt 440 160)
+	(pt 504 160)
+	(bus)
+)
+(connector
+	(text "input1[3]" (rect 296 127 309 175)(font "Intel Clear" )(vertical))
+	(pt 312 184)
+	(pt 312 160)
+)
+(connector
+	(text "input1[2]" (rect 360 127 373 175)(font "Intel Clear" )(vertical))
+	(pt 376 184)
+	(pt 376 160)
+)
+(connector
+	(text "input1[1]" (rect 424 127 437 175)(font "Intel Clear" )(vertical))
+	(pt 440 184)
+	(pt 440 160)
+)
+(connector
+	(text "input1[0]" (rect 488 127 501 175)(font "Intel Clear" )(vertical))
+	(pt 504 184)
+	(pt 504 160)
+)
+(connector
+	(pt 456 136)
+	(pt 520 136)
+	(bus)
+)
+(connector
+	(pt 392 136)
+	(pt 456 136)
+	(bus)
+)
+(connector
+	(pt 288 136)
+	(pt 328 136)
+	(bus)
+)
+(connector
+	(pt 328 136)
+	(pt 392 136)
+	(bus)
+)
+(connector
+	(text "input0[3]" (rect 312 127 325 175)(font "Intel Clear" )(vertical))
+	(pt 328 184)
+	(pt 328 136)
+)
+(connector
+	(text "input0[2]" (rect 376 127 389 175)(font "Intel Clear" )(vertical))
+	(pt 392 184)
+	(pt 392 136)
+)
+(connector
+	(text "input0[1]" (rect 440 127 453 175)(font "Intel Clear" )(vertical))
+	(pt 456 184)
+	(pt 456 136)
+)
+(connector
+	(text "input0[0]" (rect 504 127 517 175)(font "Intel Clear" )(vertical))
+	(pt 520 184)
+	(pt 520 136)
+)
+(junction (pt 312 160))
+(junction (pt 376 160))
+(junction (pt 440 160))
+(junction (pt 456 136))
+(junction (pt 392 136))
+(junction (pt 328 136))

1ano/2semestre/lsd/pratica01/part4/EqCmp4.bsf

@@ -0,0 +1,51 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 2020  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+*/
+(header "symbol" (version "1.2"))
+(symbol
+	(rect 16 16 184 112)
+	(text "EqCmp4" (rect 5 0 55 15)(font "Intel Clear" (font_size 8)))
+	(text "inst" (rect 8 79 28 92)(font "Intel Clear" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "input0[3..0]" (rect 0 0 67 15)(font "Intel Clear" (font_size 8)))
+		(text "input0[3..0]" (rect 21 27 88 42)(font "Intel Clear" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "input1[3..0]" (rect 0 0 67 15)(font "Intel Clear" (font_size 8)))
+		(text "input1[3..0]" (rect 21 43 88 58)(font "Intel Clear" (font_size 8)))
+		(line (pt 0 48)(pt 16 48)(line_width 3))
+	)
+	(port
+		(pt 168 32)
+		(output)
+		(text "cmpOut" (rect 0 0 47 15)(font "Intel Clear" (font_size 8)))
+		(text "cmpOut" (rect 100 27 147 42)(font "Intel Clear" (font_size 8)))
+		(line (pt 168 32)(pt 152 32))
+	)
+	(drawing
+		(rectangle (rect 16 16 152 80))
+	)
+)

1ano/2semestre/lsd/pratica01/part4/EqCmp4.vwf

@@ -0,0 +1,435 @@
+/*<simulation_settings>
+<ftestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off EqCmpDemo -c EqCmpDemo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmp4.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmp4.vwf.vht"</ftestbench_cmd>
+<ttestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off EqCmpDemo -c EqCmpDemo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmp4.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmp4.vwf.vht"</ttestbench_cmd>
+<fnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/" EqCmpDemo -c EqCmpDemo</fnetlist_cmd>
+<tnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/" EqCmpDemo -c EqCmpDemo</tnetlist_cmd>
+<modelsim_script>onerror {exit -code 1}
+vlib work
+vcom -work work EqCmpDemo.vho
+vcom -work work EqCmp4.vwf.vht
+vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.EqCmpDemo_vhd_vec_tst
+vcd file -direction EqCmpDemo.msim.vcd
+vcd add -internal EqCmpDemo_vhd_vec_tst/*
+vcd add -internal EqCmpDemo_vhd_vec_tst/i1/*
+proc simTimestamp {} {
+    echo "Simulation time: $::now ps"
+    if { [string equal running [runStatus]] } {
+        after 2500 simTimestamp
+    }
+}
+after 2500 simTimestamp
+run -all
+quit -f
+</modelsim_script>
+<modelsim_script_timing>onerror {exit -code 1}
+vlib work
+vcom -work work EqCmpDemo.vho
+vcom -work work EqCmp4.vwf.vht
+vsim -novopt -c -t 1ps -sdfmax EqCmpDemo_vhd_vec_tst/i1=EqCmpDemo_vhd.sdo -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.EqCmpDemo_vhd_vec_tst
+vcd file -direction EqCmpDemo.msim.vcd
+vcd add -internal EqCmpDemo_vhd_vec_tst/*
+vcd add -internal EqCmpDemo_vhd_vec_tst/i1/*
+proc simTimestamp {} {
+    echo "Simulation time: $::now ps"
+    if { [string equal running [runStatus]] } {
+        after 2500 simTimestamp
+    }
+}
+after 2500 simTimestamp
+run -all
+quit -f
+</modelsim_script_timing>
+<hdl_lang>vhdl</hdl_lang>
+</simulation_settings>*/
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+
+/*
+Copyright (C) 2020  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+*/
+
+HEADER
+{
+	VERSION = 1;
+	TIME_UNIT = ns;
+	DATA_OFFSET = 0.0;
+	DATA_DURATION = 1000.0;
+	SIMULATION_TIME = 0.0;
+	GRID_PHASE = 0.0;
+	GRID_PERIOD = 10.0;
+	GRID_DUTY_CYCLE = 50;
+}
+
+SIGNAL("LEDG")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "";
+}
+
+SIGNAL("LEDG[0]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "";
+}
+
+SIGNAL("SW")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = BUS;
+	WIDTH = 8;
+	LSB_INDEX = 0;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("SW[7]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "SW";
+}
+
+SIGNAL("SW[6]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "SW";
+}
+
+SIGNAL("SW[5]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "SW";
+}
+
+SIGNAL("SW[4]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "SW";
+}
+
+SIGNAL("SW[3]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "SW";
+}
+
+SIGNAL("SW[2]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "SW";
+}
+
+SIGNAL("SW[1]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "SW";
+}
+
+SIGNAL("SW[0]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "SW";
+}
+
+TRANSITION_LIST("LEDG")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL X FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("LEDG[0]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL X FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("SW[7]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		NODE
+		{
+			REPEAT = 1;
+			LEVEL 0 FOR 400.0;
+			LEVEL 1 FOR 400.0;
+		}
+		LEVEL 0 FOR 200.0;
+	}
+}
+
+TRANSITION_LIST("SW[6]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		NODE
+		{
+			REPEAT = 2;
+			LEVEL 0 FOR 200.0;
+			LEVEL 1 FOR 200.0;
+		}
+		LEVEL 0 FOR 200.0;
+	}
+}
+
+TRANSITION_LIST("SW[5]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		NODE
+		{
+			REPEAT = 5;
+			LEVEL 0 FOR 100.0;
+			LEVEL 1 FOR 100.0;
+		}
+	}
+}
+
+TRANSITION_LIST("SW[4]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		NODE
+		{
+			REPEAT = 10;
+			LEVEL 0 FOR 50.0;
+			LEVEL 1 FOR 50.0;
+		}
+	}
+}
+
+TRANSITION_LIST("SW[3]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		NODE
+		{
+			REPEAT = 20;
+			LEVEL 0 FOR 25.0;
+			LEVEL 1 FOR 25.0;
+		}
+	}
+}
+
+TRANSITION_LIST("SW[2]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		NODE
+		{
+			REPEAT = 40;
+			LEVEL 0 FOR 12.5;
+			LEVEL 1 FOR 12.5;
+		}
+	}
+}
+
+TRANSITION_LIST("SW[1]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		NODE
+		{
+			REPEAT = 80;
+			LEVEL 0 FOR 6.25;
+			LEVEL 1 FOR 6.25;
+		}
+	}
+}
+
+TRANSITION_LIST("SW[0]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		NODE
+		{
+			REPEAT = 148;
+			LEVEL 0 FOR 3.375;
+			LEVEL 1 FOR 3.375;
+		}
+		LEVEL 0 FOR 1.0;
+	}
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "SW";
+	EXPAND_STATUS = EXPANDED;
+	RADIX = Binary;
+	TREE_INDEX = 0;
+	TREE_LEVEL = 0;
+	CHILDREN = 1, 2, 3, 4, 5, 6, 7, 8;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "SW[7]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 1;
+	TREE_LEVEL = 1;
+	PARENT = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "SW[6]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 2;
+	TREE_LEVEL = 1;
+	PARENT = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "SW[5]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 3;
+	TREE_LEVEL = 1;
+	PARENT = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "SW[4]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 4;
+	TREE_LEVEL = 1;
+	PARENT = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "SW[3]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 5;
+	TREE_LEVEL = 1;
+	PARENT = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "SW[2]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 6;
+	TREE_LEVEL = 1;
+	PARENT = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "SW[1]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 7;
+	TREE_LEVEL = 1;
+	PARENT = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "SW[0]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 8;
+	TREE_LEVEL = 1;
+	PARENT = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "LEDG";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 9;
+	TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+	CHANNEL = "LEDG[0]";
+	EXPAND_STATUS = COLLAPSED;
+	RADIX = Binary;
+	TREE_INDEX = 10;
+	TREE_LEVEL = 0;
+}
+
+TIME_BAR
+{
+	TIME = 0;
+	MASTER = TRUE;
+}
+;

1ano/2semestre/lsd/pratica01/part4/EqCmp8.bsf

@@ -0,0 +1,51 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 2020  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 192 96)
+	(text "EqCmp8" (rect 5 0 41 12)(font "Arial" ))
+	(text "inst" (rect 8 64 20 76)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "input0[7..0]" (rect 0 0 42 12)(font "Arial" ))
+		(text "input0[7..0]" (rect 21 27 63 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "input1[7..0]" (rect 0 0 41 12)(font "Arial" ))
+		(text "input1[7..0]" (rect 21 43 62 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 3))
+	)
+	(port
+		(pt 176 32)
+		(output)
+		(text "cmpOut" (rect 0 0 31 12)(font "Arial" ))
+		(text "cmpOut" (rect 124 27 155 39)(font "Arial" ))
+		(line (pt 176 32)(pt 160 32)(line_width 1))
+	)
+	(drawing
+		(rectangle (rect 16 16 160 64)(line_width 1))
+	)
+)

1ano/2semestre/lsd/pratica01/part4/EqCmp8.vhd

@@ -0,0 +1,16 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+entity EqCmp8 is
+	port
+	(
+		input0 : in std_logic_vector(7 downto 0);
+		input1 : in std_logic_vector(7 downto 0);
+		cmpOut : out std_logic
+	);
+end EqCmp8;
+
+architecture Behavioral of EqCmp8 is
+begin
+	cmpOut <= '1' when (input0 = input1) else '0';
+end Behavioral;

1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.bdf

@@ -0,0 +1,116 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 2020  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+*/
+(header "graphic" (version "1.4"))
+(pin
+	(input)
+	(rect 296 200 464 216)
+	(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
+	(text "SW[3..0]" (rect 5 0 49 13)(font "Intel Clear" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 232 216 296 232))
+)
+(pin
+	(input)
+	(rect 296 216 464 232)
+	(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
+	(text "SW[7..4]" (rect 5 0 49 13)(font "Intel Clear" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 232 232 296 248))
+)
+(pin
+	(output)
+	(rect 656 200 832 216)
+	(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
+	(text "LEDG[0]" (rect 90 0 132 11)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 832 216 888 232))
+)
+(symbol
+	(rect 472 176 640 272)
+	(text "EqCmp4" (rect 5 0 55 15)(font "Intel Clear" (font_size 8)))
+	(text "inst1" (rect 8 79 32 92)(font "Intel Clear" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "input0[3..0]" (rect 0 0 67 15)(font "Intel Clear" (font_size 8)))
+		(text "input0[3..0]" (rect 21 27 88 42)(font "Intel Clear" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "input1[3..0]" (rect 0 0 67 15)(font "Intel Clear" (font_size 8)))
+		(text "input1[3..0]" (rect 21 43 88 58)(font "Intel Clear" (font_size 8)))
+		(line (pt 0 48)(pt 16 48)(line_width 3))
+	)
+	(port
+		(pt 168 32)
+		(output)
+		(text "cmpOut" (rect 0 0 47 15)(font "Intel Clear" (font_size 8)))
+		(text "cmpOut" (rect 100 27 147 42)(font "Intel Clear" (font_size 8)))
+		(line (pt 168 32)(pt 152 32))
+	)
+	(drawing
+		(rectangle (rect 16 16 152 80))
+	)
+)
+(connector
+	(pt 464 208)
+	(pt 472 208)
+	(bus)
+)
+(connector
+	(pt 464 224)
+	(pt 472 224)
+	(bus)
+)
+(connector
+	(pt 656 208)
+	(pt 640 208)
+)

1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.qpf

@@ -0,0 +1,31 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2020  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and any partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+# Date created = 17:39:56  March 07, 2023
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "20.1"
+DATE = "17:39:56  March 07, 2023"
+
+# Revisions
+
+PROJECT_REVISION = "EqCmpDemo"

1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.asm.qmsg

@@ -0,0 +1,7 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678222514063 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678222514063 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar  7 20:55:13 2023 " "Processing started: Tue Mar  7 20:55:13 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678222514063 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1678222514063 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off EqCmpDemo -c EqCmpDemo " "Command: quartus_asm --read_settings_files=off --write_settings_files=off EqCmpDemo -c EqCmpDemo" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1678222514063 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1678222514271 ""}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1678222516408 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1678222516505 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "366 " "Peak virtual memory: 366 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678222516764 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar  7 20:55:16 2023 " "Processing ended: Tue Mar  7 20:55:16 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678222516764 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678222516764 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678222516764 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1678222516764 ""}