diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/Register.vhd.bak b/1ano/2semestre/lsd/pratica04/RegisterDemo/Register.vhd.bak
new file mode 100644
index 0000000..aac5b72
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica04/RegisterDemo/Register.vhd.bak
@@ -0,0 +1,11 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+entity Register8 is
+ port
+ (
+ dataIn : in std_logic_vector(7 downto 0);
+ clk : in std_logic;
+ dataOut : out std_logic_vector(7 downto 0)
+ );
+end Register8;
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/Register8.bsf b/1ano/2semestre/lsd/pratica04/RegisterDemo/Register8.bsf
new file mode 100644
index 0000000..cdbd775
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica04/RegisterDemo/Register8.bsf
@@ -0,0 +1,58 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 2020 Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions
+and other software and tools, and any partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Intel Program License
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors. Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+ (rect 16 16 208 128)
+ (text "Register8" (rect 5 0 43 12)(font "Arial" ))
+ (text "inst" (rect 8 96 20 108)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "dataIn[7..0]" (rect 0 0 43 12)(font "Arial" ))
+ (text "dataIn[7..0]" (rect 21 27 64 39)(font "Arial" ))
+ (line (pt 0 32)(pt 16 32)(line_width 3))
+ )
+ (port
+ (pt 0 48)
+ (input)
+ (text "clk" (rect 0 0 10 12)(font "Arial" ))
+ (text "clk" (rect 21 43 31 55)(font "Arial" ))
+ (line (pt 0 48)(pt 16 48)(line_width 1))
+ )
+ (port
+ (pt 0 64)
+ (input)
+ (text "wrEn" (rect 0 0 21 12)(font "Arial" ))
+ (text "wrEn" (rect 21 59 42 71)(font "Arial" ))
+ (line (pt 0 64)(pt 16 64)(line_width 1))
+ )
+ (port
+ (pt 192 32)
+ (output)
+ (text "dataOut[7..0]" (rect 0 0 50 12)(font "Arial" ))
+ (text "dataOut[7..0]" (rect 121 27 171 39)(font "Arial" ))
+ (line (pt 192 32)(pt 176 32)(line_width 3))
+ )
+ (drawing
+ (rectangle (rect 16 16 176 96)(line_width 1))
+ )
+)
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/Register8.vhd b/1ano/2semestre/lsd/pratica04/RegisterDemo/Register8.vhd
new file mode 100644
index 0000000..e20439d
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica04/RegisterDemo/Register8.vhd
@@ -0,0 +1,24 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+entity Register8 is
+ port
+ (
+ dataIn : in std_logic_vector(7 downto 0);
+ clk : in std_logic;
+ wrEn : in std_logic;
+ dataOut : out std_logic_vector(7 downto 0)
+ );
+end Register8;
+
+architecture Behavioral of Register8 is
+begin
+ process (clk)
+ begin
+ if (rising_edge(clk)) then
+ if (wrEn = '1') then
+ dataOut <= dataIn;
+ end if;
+ end if;
+ end process;
+end Behavioral;
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/Register8.vwf b/1ano/2semestre/lsd/pratica04/RegisterDemo/Register8.vwf
new file mode 100644
index 0000000..ead81da
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica04/RegisterDemo/Register8.vwf
@@ -0,0 +1,760 @@
+/*
+quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off RegisterDemo -c RegisterDemo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/Register8.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/Register8.vwf.vht"
+quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off RegisterDemo -c RegisterDemo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/Register8.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/Register8.vwf.vht"
+quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/" RegisterDemo -c RegisterDemo
+quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/" RegisterDemo -c RegisterDemo
+onerror {exit -code 1}
+vlib work
+vcom -work work RegisterDemo.vho
+vcom -work work Register8.vwf.vht
+vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.Register8_vhd_vec_tst
+vcd file -direction RegisterDemo.msim.vcd
+vcd add -internal Register8_vhd_vec_tst/*
+vcd add -internal Register8_vhd_vec_tst/i1/*
+proc simTimestamp {} {
+ echo "Simulation time: $::now ps"
+ if { [string equal running [runStatus]] } {
+ after 2500 simTimestamp
+ }
+}
+after 2500 simTimestamp
+run -all
+quit -f
+
+onerror {exit -code 1}
+vlib work
+vcom -work work RegisterDemo.vho
+vcom -work work Register8.vwf.vht
+vsim -novopt -c -t 1ps -sdfmax Register8_vhd_vec_tst/i1=RegisterDemo_vhd.sdo -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.Register8_vhd_vec_tst
+vcd file -direction RegisterDemo.msim.vcd
+vcd add -internal Register8_vhd_vec_tst/*
+vcd add -internal Register8_vhd_vec_tst/i1/*
+proc simTimestamp {} {
+ echo "Simulation time: $::now ps"
+ if { [string equal running [runStatus]] } {
+ after 2500 simTimestamp
+ }
+}
+after 2500 simTimestamp
+run -all
+quit -f
+
+vhdl
+*/
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+
+/*
+Copyright (C) 2020 Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions
+and other software and tools, and any partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Intel Program License
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors. Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+*/
+
+HEADER
+{
+ VERSION = 1;
+ TIME_UNIT = ns;
+ DATA_OFFSET = 0.0;
+ DATA_DURATION = 1000.0;
+ SIMULATION_TIME = 0.0;
+ GRID_PHASE = 0.0;
+ GRID_PERIOD = 10.0;
+ GRID_DUTY_CYCLE = 50;
+}
+
+SIGNAL("clk")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = INPUT;
+ PARENT = "";
+}
+
+SIGNAL("dataIn")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = BUS;
+ WIDTH = 8;
+ LSB_INDEX = 0;
+ DIRECTION = INPUT;
+ PARENT = "";
+}
+
+SIGNAL("dataIn[7]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = INPUT;
+ PARENT = "dataIn";
+}
+
+SIGNAL("dataIn[6]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = INPUT;
+ PARENT = "dataIn";
+}
+
+SIGNAL("dataIn[5]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = INPUT;
+ PARENT = "dataIn";
+}
+
+SIGNAL("dataIn[4]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = INPUT;
+ PARENT = "dataIn";
+}
+
+SIGNAL("dataIn[3]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = INPUT;
+ PARENT = "dataIn";
+}
+
+SIGNAL("dataIn[2]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = INPUT;
+ PARENT = "dataIn";
+}
+
+SIGNAL("dataIn[1]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = INPUT;
+ PARENT = "dataIn";
+}
+
+SIGNAL("dataIn[0]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = INPUT;
+ PARENT = "dataIn";
+}
+
+SIGNAL("dataOut")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = BUS;
+ WIDTH = 8;
+ LSB_INDEX = 0;
+ DIRECTION = OUTPUT;
+ PARENT = "";
+}
+
+SIGNAL("dataOut[7]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "dataOut";
+}
+
+SIGNAL("dataOut[6]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "dataOut";
+}
+
+SIGNAL("dataOut[5]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "dataOut";
+}
+
+SIGNAL("dataOut[4]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "dataOut";
+}
+
+SIGNAL("dataOut[3]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "dataOut";
+}
+
+SIGNAL("dataOut[2]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "dataOut";
+}
+
+SIGNAL("dataOut[1]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "dataOut";
+}
+
+SIGNAL("dataOut[0]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "dataOut";
+}
+
+SIGNAL("wrEn")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = INPUT;
+ PARENT = "";
+}
+
+TRANSITION_LIST("clk")
+{
+ NODE
+ {
+ REPEAT = 1;
+ NODE
+ {
+ REPEAT = 25;
+ LEVEL 0 FOR 20.0;
+ LEVEL 1 FOR 20.0;
+ }
+ }
+}
+
+TRANSITION_LIST("dataIn[7]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL 1 FOR 200.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 120.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 120.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 120.0;
+ LEVEL 1 FOR 40.0;
+ }
+}
+
+TRANSITION_LIST("dataIn[6]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL 0 FOR 80.0;
+ LEVEL 1 FOR 80.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 120.0;
+ LEVEL 1 FOR 120.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 80.0;
+ LEVEL 0 FOR 120.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 120.0;
+ LEVEL 1 FOR 40.0;
+ }
+}
+
+TRANSITION_LIST("dataIn[5]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL 0 FOR 80.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 120.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 80.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 80.0;
+ LEVEL 1 FOR 80.0;
+ LEVEL 0 FOR 120.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 80.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 40.0;
+ }
+}
+
+TRANSITION_LIST("dataIn[4]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL 0 FOR 200.0;
+ LEVEL 1 FOR 160.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 320.0;
+ LEVEL 0 FOR 160.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 80.0;
+ }
+}
+
+TRANSITION_LIST("dataIn[3]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL 1 FOR 160.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 120.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 80.0;
+ LEVEL 0 FOR 80.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 160.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 120.0;
+ LEVEL 0 FOR 80.0;
+ }
+}
+
+TRANSITION_LIST("dataIn[2]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL 0 FOR 80.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 120.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 120.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 80.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 80.0;
+ LEVEL 0 FOR 80.0;
+ LEVEL 1 FOR 80.0;
+ }
+}
+
+TRANSITION_LIST("dataIn[1]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL 1 FOR 80.0;
+ LEVEL 0 FOR 80.0;
+ LEVEL 1 FOR 80.0;
+ LEVEL 0 FOR 80.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 80.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 120.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 40.0;
+ }
+}
+
+TRANSITION_LIST("dataIn[0]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL 1 FOR 160.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 120.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 160.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 80.0;
+ LEVEL 1 FOR 80.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 40.0;
+ }
+}
+
+TRANSITION_LIST("dataOut[7]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 1000.0;
+ }
+}
+
+TRANSITION_LIST("dataOut[6]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 1000.0;
+ }
+}
+
+TRANSITION_LIST("dataOut[5]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 1000.0;
+ }
+}
+
+TRANSITION_LIST("dataOut[4]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 1000.0;
+ }
+}
+
+TRANSITION_LIST("dataOut[3]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 1000.0;
+ }
+}
+
+TRANSITION_LIST("dataOut[2]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 1000.0;
+ }
+}
+
+TRANSITION_LIST("dataOut[1]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 1000.0;
+ }
+}
+
+TRANSITION_LIST("dataOut[0]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 1000.0;
+ }
+}
+
+TRANSITION_LIST("wrEn")
+{
+ NODE
+ {
+ REPEAT = 1;
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL 0 FOR 400.0;
+ LEVEL 1 FOR 400.0;
+ }
+ LEVEL 0 FOR 200.0;
+ }
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "wrEn";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Binary;
+ TREE_INDEX = 0;
+ TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "clk";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Binary;
+ TREE_INDEX = 1;
+ TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dataIn";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Binary;
+ TREE_INDEX = 2;
+ TREE_LEVEL = 0;
+ CHILDREN = 3, 4, 5, 6, 7, 8, 9, 10;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dataIn[7]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Binary;
+ TREE_INDEX = 3;
+ TREE_LEVEL = 1;
+ PARENT = 2;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dataIn[6]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Binary;
+ TREE_INDEX = 4;
+ TREE_LEVEL = 1;
+ PARENT = 2;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dataIn[5]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Binary;
+ TREE_INDEX = 5;
+ TREE_LEVEL = 1;
+ PARENT = 2;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dataIn[4]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Binary;
+ TREE_INDEX = 6;
+ TREE_LEVEL = 1;
+ PARENT = 2;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dataIn[3]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Binary;
+ TREE_INDEX = 7;
+ TREE_LEVEL = 1;
+ PARENT = 2;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dataIn[2]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Binary;
+ TREE_INDEX = 8;
+ TREE_LEVEL = 1;
+ PARENT = 2;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dataIn[1]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Binary;
+ TREE_INDEX = 9;
+ TREE_LEVEL = 1;
+ PARENT = 2;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dataIn[0]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Binary;
+ TREE_INDEX = 10;
+ TREE_LEVEL = 1;
+ PARENT = 2;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dataOut";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Binary;
+ TREE_INDEX = 11;
+ TREE_LEVEL = 0;
+ CHILDREN = 12, 13, 14, 15, 16, 17, 18, 19;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dataOut[7]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Binary;
+ TREE_INDEX = 12;
+ TREE_LEVEL = 1;
+ PARENT = 11;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dataOut[6]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Binary;
+ TREE_INDEX = 13;
+ TREE_LEVEL = 1;
+ PARENT = 11;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dataOut[5]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Binary;
+ TREE_INDEX = 14;
+ TREE_LEVEL = 1;
+ PARENT = 11;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dataOut[4]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Binary;
+ TREE_INDEX = 15;
+ TREE_LEVEL = 1;
+ PARENT = 11;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dataOut[3]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Binary;
+ TREE_INDEX = 16;
+ TREE_LEVEL = 1;
+ PARENT = 11;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dataOut[2]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Binary;
+ TREE_INDEX = 17;
+ TREE_LEVEL = 1;
+ PARENT = 11;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dataOut[1]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Binary;
+ TREE_INDEX = 18;
+ TREE_LEVEL = 1;
+ PARENT = 11;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dataOut[0]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Binary;
+ TREE_INDEX = 19;
+ TREE_LEVEL = 1;
+ PARENT = 11;
+}
+
+TIME_BAR
+{
+ TIME = 0;
+ MASTER = TRUE;
+}
+;
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/RegisterDemo.bdf b/1ano/2semestre/lsd/pratica04/RegisterDemo/RegisterDemo.bdf
new file mode 100644
index 0000000..86c8ccb
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica04/RegisterDemo/RegisterDemo.bdf
@@ -0,0 +1,140 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 2020 Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions
+and other software and tools, and any partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Intel Program License
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors. Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+*/
+(header "graphic" (version "1.4"))
+(pin
+ (input)
+ (rect 232 208 400 224)
+ (text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
+ (text "SW[7..0]" (rect 5 0 48 11)(font "Arial" ))
+ (pt 168 8)
+ (drawing
+ (line (pt 84 12)(pt 109 12))
+ (line (pt 84 4)(pt 109 4))
+ (line (pt 113 8)(pt 168 8))
+ (line (pt 84 12)(pt 84 4))
+ (line (pt 109 4)(pt 113 8))
+ (line (pt 109 12)(pt 113 8))
+ )
+ (text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
+)
+(pin
+ (input)
+ (rect 232 224 400 240)
+ (text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
+ (text "KEY[0]" (rect 5 0 41 13)(font "Intel Clear" ))
+ (pt 168 8)
+ (drawing
+ (line (pt 84 12)(pt 109 12))
+ (line (pt 84 4)(pt 109 4))
+ (line (pt 113 8)(pt 168 8))
+ (line (pt 84 12)(pt 84 4))
+ (line (pt 109 4)(pt 113 8))
+ (line (pt 109 12)(pt 113 8))
+ )
+ (text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
+)
+(pin
+ (input)
+ (rect 232 240 400 256)
+ (text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
+ (text "SW[8]" (rect 5 0 39 13)(font "Intel Clear" ))
+ (pt 168 8)
+ (drawing
+ (line (pt 84 12)(pt 109 12))
+ (line (pt 84 4)(pt 109 4))
+ (line (pt 113 8)(pt 168 8))
+ (line (pt 84 12)(pt 84 4))
+ (line (pt 109 4)(pt 113 8))
+ (line (pt 109 12)(pt 113 8))
+ )
+ (text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
+)
+(pin
+ (output)
+ (rect 608 208 784 224)
+ (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
+ (text "LEDR[7..0]" (rect 90 0 144 11)(font "Arial" ))
+ (pt 0 8)
+ (drawing
+ (line (pt 0 8)(pt 52 8))
+ (line (pt 52 4)(pt 78 4))
+ (line (pt 52 12)(pt 78 12))
+ (line (pt 52 12)(pt 52 4))
+ (line (pt 78 4)(pt 82 8))
+ (line (pt 82 8)(pt 78 12))
+ (line (pt 78 12)(pt 82 8))
+ )
+)
+(symbol
+ (rect 408 184 600 296)
+ (text "Register8" (rect 5 0 53 11)(font "Arial" ))
+ (text "inst" (rect 8 96 26 107)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "dataIn[7..0]" (rect 0 0 55 11)(font "Arial" ))
+ (text "dataIn[7..0]" (rect 21 27 76 38)(font "Arial" ))
+ (line (pt 0 32)(pt 16 32)(line_width 3))
+ )
+ (port
+ (pt 0 48)
+ (input)
+ (text "clk" (rect 0 0 15 11)(font "Arial" ))
+ (text "clk" (rect 21 43 36 54)(font "Arial" ))
+ (line (pt 0 48)(pt 16 48))
+ )
+ (port
+ (pt 0 64)
+ (input)
+ (text "wrEn" (rect 0 0 27 11)(font "Arial" ))
+ (text "wrEn" (rect 21 59 48 70)(font "Arial" ))
+ (line (pt 0 64)(pt 16 64))
+ )
+ (port
+ (pt 192 32)
+ (output)
+ (text "dataOut[7..0]" (rect 0 0 63 11)(font "Arial" ))
+ (text "dataOut[7..0]" (rect 118 27 181 38)(font "Arial" ))
+ (line (pt 192 32)(pt 176 32)(line_width 3))
+ )
+ (drawing
+ (rectangle (rect 16 16 176 96))
+ )
+)
+(connector
+ (pt 600 216)
+ (pt 608 216)
+ (bus)
+)
+(connector
+ (pt 408 216)
+ (pt 400 216)
+ (bus)
+)
+(connector
+ (pt 408 232)
+ (pt 400 232)
+)
+(connector
+ (pt 408 248)
+ (pt 400 248)
+)
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/RegisterDemo.qpf b/1ano/2semestre/lsd/pratica04/RegisterDemo/RegisterDemo.qpf
new file mode 100644
index 0000000..94cb36f
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica04/RegisterDemo/RegisterDemo.qpf
@@ -0,0 +1,31 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2020 Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions
+# and other software and tools, and any partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Intel Program License
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors. Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+# Date created = 12:32:20 March 15, 2023
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "20.1"
+DATE = "12:32:20 March 15, 2023"
+
+# Revisions
+
+PROJECT_REVISION = "RegisterDemo"
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/RegisterDemo.qsf b/1ano/2semestre/lsd/pratica04/RegisterDemo/RegisterDemo.qsf
new file mode 100644
index 0000000..de52557
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica04/RegisterDemo/RegisterDemo.qsf
@@ -0,0 +1,585 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2020 Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions
+# and other software and tools, and any partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Intel Program License
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors. Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+# Date created = 12:32:20 March 15, 2023
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+# RegisterDemo_assignment_defaults.qdf
+# If this file doesn't exist, see file:
+# assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus Prime software
+# and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone IV E"
+set_global_assignment -name DEVICE EP4CE115F29C7
+set_global_assignment -name TOP_LEVEL_ENTITY RegisterDemo
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:32:20 MARCH 15, 2023"
+set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
+set_global_assignment -name VHDL_FILE Register8.vhd
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name VECTOR_WAVEFORM_FILE Register8.vwf
+set_global_assignment -name BDF_FILE RegisterDemo.bdf
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_location_assignment PIN_Y2 -to CLOCK_50
+set_location_assignment PIN_AG14 -to CLOCK2_50
+set_location_assignment PIN_AG15 -to CLOCK3_50
+set_location_assignment PIN_AH14 -to SMA_CLKIN
+set_location_assignment PIN_AE23 -to SMA_CLKOUT
+set_location_assignment PIN_M23 -to KEY[0]
+set_location_assignment PIN_M21 -to KEY[1]
+set_location_assignment PIN_N21 -to KEY[2]
+set_location_assignment PIN_R24 -to KEY[3]
+set_location_assignment PIN_AB28 -to SW[0]
+set_location_assignment PIN_AC28 -to SW[1]
+set_location_assignment PIN_AC27 -to SW[2]
+set_location_assignment PIN_AD27 -to SW[3]
+set_location_assignment PIN_AB27 -to SW[4]
+set_location_assignment PIN_AC26 -to SW[5]
+set_location_assignment PIN_AD26 -to SW[6]
+set_location_assignment PIN_AB26 -to SW[7]
+set_location_assignment PIN_AC25 -to SW[8]
+set_location_assignment PIN_AB25 -to SW[9]
+set_location_assignment PIN_AC24 -to SW[10]
+set_location_assignment PIN_AB24 -to SW[11]
+set_location_assignment PIN_AB23 -to SW[12]
+set_location_assignment PIN_AA24 -to SW[13]
+set_location_assignment PIN_AA23 -to SW[14]
+set_location_assignment PIN_AA22 -to SW[15]
+set_location_assignment PIN_Y24 -to SW[16]
+set_location_assignment PIN_Y23 -to SW[17]
+set_location_assignment PIN_G19 -to LEDR[0]
+set_location_assignment PIN_F19 -to LEDR[1]
+set_location_assignment PIN_E19 -to LEDR[2]
+set_location_assignment PIN_F21 -to LEDR[3]
+set_location_assignment PIN_F18 -to LEDR[4]
+set_location_assignment PIN_E18 -to LEDR[5]
+set_location_assignment PIN_J19 -to LEDR[6]
+set_location_assignment PIN_H19 -to LEDR[7]
+set_location_assignment PIN_J17 -to LEDR[8]
+set_location_assignment PIN_G17 -to LEDR[9]
+set_location_assignment PIN_J15 -to LEDR[10]
+set_location_assignment PIN_H16 -to LEDR[11]
+set_location_assignment PIN_J16 -to LEDR[12]
+set_location_assignment PIN_H17 -to LEDR[13]
+set_location_assignment PIN_F15 -to LEDR[14]
+set_location_assignment PIN_G15 -to LEDR[15]
+set_location_assignment PIN_G16 -to LEDR[16]
+set_location_assignment PIN_H15 -to LEDR[17]
+set_location_assignment PIN_E21 -to LEDG[0]
+set_location_assignment PIN_E22 -to LEDG[1]
+set_location_assignment PIN_E25 -to LEDG[2]
+set_location_assignment PIN_E24 -to LEDG[3]
+set_location_assignment PIN_H21 -to LEDG[4]
+set_location_assignment PIN_G20 -to LEDG[5]
+set_location_assignment PIN_G22 -to LEDG[6]
+set_location_assignment PIN_G21 -to LEDG[7]
+set_location_assignment PIN_F17 -to LEDG[8]
+set_location_assignment PIN_G18 -to HEX0[0]
+set_location_assignment PIN_F22 -to HEX0[1]
+set_location_assignment PIN_E17 -to HEX0[2]
+set_location_assignment PIN_L26 -to HEX0[3]
+set_location_assignment PIN_L25 -to HEX0[4]
+set_location_assignment PIN_J22 -to HEX0[5]
+set_location_assignment PIN_H22 -to HEX0[6]
+set_location_assignment PIN_M24 -to HEX1[0]
+set_location_assignment PIN_Y22 -to HEX1[1]
+set_location_assignment PIN_W21 -to HEX1[2]
+set_location_assignment PIN_W22 -to HEX1[3]
+set_location_assignment PIN_W25 -to HEX1[4]
+set_location_assignment PIN_U23 -to HEX1[5]
+set_location_assignment PIN_U24 -to HEX1[6]
+set_location_assignment PIN_AA25 -to HEX2[0]
+set_location_assignment PIN_AA26 -to HEX2[1]
+set_location_assignment PIN_Y25 -to HEX2[2]
+set_location_assignment PIN_W26 -to HEX2[3]
+set_location_assignment PIN_Y26 -to HEX2[4]
+set_location_assignment PIN_W27 -to HEX2[5]
+set_location_assignment PIN_W28 -to HEX2[6]
+set_location_assignment PIN_V21 -to HEX3[0]
+set_location_assignment PIN_U21 -to HEX3[1]
+set_location_assignment PIN_AB20 -to HEX3[2]
+set_location_assignment PIN_AA21 -to HEX3[3]
+set_location_assignment PIN_AD24 -to HEX3[4]
+set_location_assignment PIN_AF23 -to HEX3[5]
+set_location_assignment PIN_Y19 -to HEX3[6]
+set_location_assignment PIN_AB19 -to HEX4[0]
+set_location_assignment PIN_AA19 -to HEX4[1]
+set_location_assignment PIN_AG21 -to HEX4[2]
+set_location_assignment PIN_AH21 -to HEX4[3]
+set_location_assignment PIN_AE19 -to HEX4[4]
+set_location_assignment PIN_AF19 -to HEX4[5]
+set_location_assignment PIN_AE18 -to HEX4[6]
+set_location_assignment PIN_AD18 -to HEX5[0]
+set_location_assignment PIN_AC18 -to HEX5[1]
+set_location_assignment PIN_AB18 -to HEX5[2]
+set_location_assignment PIN_AH19 -to HEX5[3]
+set_location_assignment PIN_AG19 -to HEX5[4]
+set_location_assignment PIN_AF18 -to HEX5[5]
+set_location_assignment PIN_AH18 -to HEX5[6]
+set_location_assignment PIN_AA17 -to HEX6[0]
+set_location_assignment PIN_AB16 -to HEX6[1]
+set_location_assignment PIN_AA16 -to HEX6[2]
+set_location_assignment PIN_AB17 -to HEX6[3]
+set_location_assignment PIN_AB15 -to HEX6[4]
+set_location_assignment PIN_AA15 -to HEX6[5]
+set_location_assignment PIN_AC17 -to HEX6[6]
+set_location_assignment PIN_AD17 -to HEX7[0]
+set_location_assignment PIN_AE17 -to HEX7[1]
+set_location_assignment PIN_AG17 -to HEX7[2]
+set_location_assignment PIN_AH17 -to HEX7[3]
+set_location_assignment PIN_AF17 -to HEX7[4]
+set_location_assignment PIN_AG18 -to HEX7[5]
+set_location_assignment PIN_AA14 -to HEX7[6]
+set_location_assignment PIN_L3 -to LCD_DATA[0]
+set_location_assignment PIN_L1 -to LCD_DATA[1]
+set_location_assignment PIN_L2 -to LCD_DATA[2]
+set_location_assignment PIN_K7 -to LCD_DATA[3]
+set_location_assignment PIN_K1 -to LCD_DATA[4]
+set_location_assignment PIN_K2 -to LCD_DATA[5]
+set_location_assignment PIN_M3 -to LCD_DATA[6]
+set_location_assignment PIN_M5 -to LCD_DATA[7]
+set_location_assignment PIN_L6 -to LCD_BLON
+set_location_assignment PIN_M1 -to LCD_RW
+set_location_assignment PIN_L4 -to LCD_EN
+set_location_assignment PIN_M2 -to LCD_RS
+set_location_assignment PIN_L5 -to LCD_ON
+set_location_assignment PIN_G9 -to UART_TXD
+set_location_assignment PIN_G12 -to UART_RXD
+set_location_assignment PIN_G14 -to UART_CTS
+set_location_assignment PIN_J13 -to UART_RTS
+set_location_assignment PIN_G6 -to PS2_CLK
+set_location_assignment PIN_H5 -to PS2_DAT
+set_location_assignment PIN_G5 -to PS2_CLK2
+set_location_assignment PIN_F5 -to PS2_DAT2
+set_location_assignment PIN_AE13 -to SD_CLK
+set_location_assignment PIN_AD14 -to SD_CMD
+set_location_assignment PIN_AF14 -to SD_WP_N
+set_location_assignment PIN_AE14 -to SD_DAT[0]
+set_location_assignment PIN_AF13 -to SD_DAT[1]
+set_location_assignment PIN_AB14 -to SD_DAT[2]
+set_location_assignment PIN_AC14 -to SD_DAT[3]
+set_location_assignment PIN_G13 -to VGA_HS
+set_location_assignment PIN_C13 -to VGA_VS
+set_location_assignment PIN_C10 -to VGA_SYNC_N
+set_location_assignment PIN_A12 -to VGA_CLK
+set_location_assignment PIN_F11 -to VGA_BLANK_N
+set_location_assignment PIN_E12 -to VGA_R[0]
+set_location_assignment PIN_E11 -to VGA_R[1]
+set_location_assignment PIN_D10 -to VGA_R[2]
+set_location_assignment PIN_F12 -to VGA_R[3]
+set_location_assignment PIN_G10 -to VGA_R[4]
+set_location_assignment PIN_J12 -to VGA_R[5]
+set_location_assignment PIN_H8 -to VGA_R[6]
+set_location_assignment PIN_H10 -to VGA_R[7]
+set_location_assignment PIN_G8 -to VGA_G[0]
+set_location_assignment PIN_G11 -to VGA_G[1]
+set_location_assignment PIN_F8 -to VGA_G[2]
+set_location_assignment PIN_H12 -to VGA_G[3]
+set_location_assignment PIN_C8 -to VGA_G[4]
+set_location_assignment PIN_B8 -to VGA_G[5]
+set_location_assignment PIN_F10 -to VGA_G[6]
+set_location_assignment PIN_C9 -to VGA_G[7]
+set_location_assignment PIN_B10 -to VGA_B[0]
+set_location_assignment PIN_A10 -to VGA_B[1]
+set_location_assignment PIN_C11 -to VGA_B[2]
+set_location_assignment PIN_B11 -to VGA_B[3]
+set_location_assignment PIN_A11 -to VGA_B[4]
+set_location_assignment PIN_C12 -to VGA_B[5]
+set_location_assignment PIN_D11 -to VGA_B[6]
+set_location_assignment PIN_D12 -to VGA_B[7]
+set_location_assignment PIN_C2 -to AUD_ADCLRCK
+set_location_assignment PIN_D2 -to AUD_ADCDAT
+set_location_assignment PIN_E3 -to AUD_DACLRCK
+set_location_assignment PIN_D1 -to AUD_DACDAT
+set_location_assignment PIN_E1 -to AUD_XCK
+set_location_assignment PIN_F2 -to AUD_BCLK
+set_location_assignment PIN_D14 -to EEP_I2C_SCLK
+set_location_assignment PIN_E14 -to EEP_I2C_SDAT
+set_location_assignment PIN_B7 -to I2C_SCLK
+set_location_assignment PIN_A8 -to I2C_SDAT
+set_location_assignment PIN_A14 -to ENETCLK_25
+set_location_assignment PIN_C14 -to ENET0_LINK100
+set_location_assignment PIN_A17 -to ENET0_GTX_CLK
+set_location_assignment PIN_C19 -to ENET0_RST_N
+set_location_assignment PIN_C20 -to ENET0_MDC
+set_location_assignment PIN_B21 -to ENET0_MDIO
+set_location_assignment PIN_A21 -to ENET0_INT_N
+set_location_assignment PIN_C18 -to ENET0_TX_DATA[0]
+set_location_assignment PIN_D19 -to ENET0_TX_DATA[1]
+set_location_assignment PIN_A19 -to ENET0_TX_DATA[2]
+set_location_assignment PIN_B19 -to ENET0_TX_DATA[3]
+set_location_assignment PIN_B17 -to ENET0_TX_CLK
+set_location_assignment PIN_A18 -to ENET0_TX_EN
+set_location_assignment PIN_B18 -to ENET0_TX_ER
+set_location_assignment PIN_C16 -to ENET0_RX_DATA[0]
+set_location_assignment PIN_D16 -to ENET0_RX_DATA[1]
+set_location_assignment PIN_D17 -to ENET0_RX_DATA[2]
+set_location_assignment PIN_C15 -to ENET0_RX_DATA[3]
+set_location_assignment PIN_A15 -to ENET0_RX_CLK
+set_location_assignment PIN_C17 -to ENET0_RX_DV
+set_location_assignment PIN_D18 -to ENET0_RX_ER
+set_location_assignment PIN_D15 -to ENET0_RX_CRS
+set_location_assignment PIN_E15 -to ENET0_RX_COL
+set_location_assignment PIN_D13 -to ENET1_LINK100
+set_location_assignment PIN_C23 -to ENET1_GTX_CLK
+set_location_assignment PIN_D22 -to ENET1_RST_N
+set_location_assignment PIN_D23 -to ENET1_MDC
+set_location_assignment PIN_D25 -to ENET1_MDIO
+set_location_assignment PIN_D24 -to ENET1_INT_N
+set_location_assignment PIN_C25 -to ENET1_TX_DATA[0]
+set_location_assignment PIN_A26 -to ENET1_TX_DATA[1]
+set_location_assignment PIN_B26 -to ENET1_TX_DATA[2]
+set_location_assignment PIN_C26 -to ENET1_TX_DATA[3]
+set_location_assignment PIN_C22 -to ENET1_TX_CLK
+set_location_assignment PIN_B25 -to ENET1_TX_EN
+set_location_assignment PIN_A25 -to ENET1_TX_ER
+set_location_assignment PIN_B23 -to ENET1_RX_DATA[0]
+set_location_assignment PIN_C21 -to ENET1_RX_DATA[1]
+set_location_assignment PIN_A23 -to ENET1_RX_DATA[2]
+set_location_assignment PIN_D21 -to ENET1_RX_DATA[3]
+set_location_assignment PIN_B15 -to ENET1_RX_CLK
+set_location_assignment PIN_A22 -to ENET1_RX_DV
+set_location_assignment PIN_C24 -to ENET1_RX_ER
+set_location_assignment PIN_D20 -to ENET1_RX_CRS
+set_location_assignment PIN_B22 -to ENET1_RX_COL
+set_location_assignment PIN_E5 -to TD_HS
+set_location_assignment PIN_E4 -to TD_VS
+set_location_assignment PIN_B14 -to TD_CLK27
+set_location_assignment PIN_G7 -to TD_RESET_N
+set_location_assignment PIN_E8 -to TD_DATA[0]
+set_location_assignment PIN_A7 -to TD_DATA[1]
+set_location_assignment PIN_D8 -to TD_DATA[2]
+set_location_assignment PIN_C7 -to TD_DATA[3]
+set_location_assignment PIN_D7 -to TD_DATA[4]
+set_location_assignment PIN_D6 -to TD_DATA[5]
+set_location_assignment PIN_E7 -to TD_DATA[6]
+set_location_assignment PIN_F7 -to TD_DATA[7]
+set_location_assignment PIN_J6 -to OTG_DATA[0]
+set_location_assignment PIN_K4 -to OTG_DATA[1]
+set_location_assignment PIN_J5 -to OTG_DATA[2]
+set_location_assignment PIN_K3 -to OTG_DATA[3]
+set_location_assignment PIN_J4 -to OTG_DATA[4]
+set_location_assignment PIN_J3 -to OTG_DATA[5]
+set_location_assignment PIN_J7 -to OTG_DATA[6]
+set_location_assignment PIN_H6 -to OTG_DATA[7]
+set_location_assignment PIN_H3 -to OTG_DATA[8]
+set_location_assignment PIN_H4 -to OTG_DATA[9]
+set_location_assignment PIN_G1 -to OTG_DATA[10]
+set_location_assignment PIN_G2 -to OTG_DATA[11]
+set_location_assignment PIN_G3 -to OTG_DATA[12]
+set_location_assignment PIN_F1 -to OTG_DATA[13]
+set_location_assignment PIN_F3 -to OTG_DATA[14]
+set_location_assignment PIN_G4 -to OTG_DATA[15]
+set_location_assignment PIN_H7 -to OTG_ADDR[0]
+set_location_assignment PIN_C3 -to OTG_ADDR[1]
+set_location_assignment PIN_J1 -to OTG_DREQ[0]
+set_location_assignment PIN_A3 -to OTG_CS_N
+set_location_assignment PIN_A4 -to OTG_WR_N
+set_location_assignment PIN_B3 -to OTG_RD_N
+set_location_assignment PIN_D5 -to OTG_INT
+set_location_assignment PIN_C5 -to OTG_RST_N
+set_location_assignment PIN_Y15 -to IRDA_RXD
+set_location_assignment PIN_U7 -to DRAM_BA[0]
+set_location_assignment PIN_R4 -to DRAM_BA[1]
+set_location_assignment PIN_U2 -to DRAM_DQM[0]
+set_location_assignment PIN_W4 -to DRAM_DQM[1]
+set_location_assignment PIN_K8 -to DRAM_DQM[2]
+set_location_assignment PIN_N8 -to DRAM_DQM[3]
+set_location_assignment PIN_U6 -to DRAM_RAS_N
+set_location_assignment PIN_V7 -to DRAM_CAS_N
+set_location_assignment PIN_AA6 -to DRAM_CKE
+set_location_assignment PIN_AE5 -to DRAM_CLK
+set_location_assignment PIN_V6 -to DRAM_WE_N
+set_location_assignment PIN_T4 -to DRAM_CS_N
+set_location_assignment PIN_W3 -to DRAM_DQ[0]
+set_location_assignment PIN_W2 -to DRAM_DQ[1]
+set_location_assignment PIN_V4 -to DRAM_DQ[2]
+set_location_assignment PIN_W1 -to DRAM_DQ[3]
+set_location_assignment PIN_V3 -to DRAM_DQ[4]
+set_location_assignment PIN_V2 -to DRAM_DQ[5]
+set_location_assignment PIN_V1 -to DRAM_DQ[6]
+set_location_assignment PIN_U3 -to DRAM_DQ[7]
+set_location_assignment PIN_Y3 -to DRAM_DQ[8]
+set_location_assignment PIN_Y4 -to DRAM_DQ[9]
+set_location_assignment PIN_AB1 -to DRAM_DQ[10]
+set_location_assignment PIN_AA3 -to DRAM_DQ[11]
+set_location_assignment PIN_AB2 -to DRAM_DQ[12]
+set_location_assignment PIN_AC1 -to DRAM_DQ[13]
+set_location_assignment PIN_AB3 -to DRAM_DQ[14]
+set_location_assignment PIN_AC2 -to DRAM_DQ[15]
+set_location_assignment PIN_M8 -to DRAM_DQ[16]
+set_location_assignment PIN_L8 -to DRAM_DQ[17]
+set_location_assignment PIN_P2 -to DRAM_DQ[18]
+set_location_assignment PIN_N3 -to DRAM_DQ[19]
+set_location_assignment PIN_N4 -to DRAM_DQ[20]
+set_location_assignment PIN_M4 -to DRAM_DQ[21]
+set_location_assignment PIN_M7 -to DRAM_DQ[22]
+set_location_assignment PIN_L7 -to DRAM_DQ[23]
+set_location_assignment PIN_U5 -to DRAM_DQ[24]
+set_location_assignment PIN_R7 -to DRAM_DQ[25]
+set_location_assignment PIN_R1 -to DRAM_DQ[26]
+set_location_assignment PIN_R2 -to DRAM_DQ[27]
+set_location_assignment PIN_R3 -to DRAM_DQ[28]
+set_location_assignment PIN_T3 -to DRAM_DQ[29]
+set_location_assignment PIN_U4 -to DRAM_DQ[30]
+set_location_assignment PIN_U1 -to DRAM_DQ[31]
+set_location_assignment PIN_R6 -to DRAM_ADDR[0]
+set_location_assignment PIN_V8 -to DRAM_ADDR[1]
+set_location_assignment PIN_U8 -to DRAM_ADDR[2]
+set_location_assignment PIN_P1 -to DRAM_ADDR[3]
+set_location_assignment PIN_V5 -to DRAM_ADDR[4]
+set_location_assignment PIN_W8 -to DRAM_ADDR[5]
+set_location_assignment PIN_W7 -to DRAM_ADDR[6]
+set_location_assignment PIN_AA7 -to DRAM_ADDR[7]
+set_location_assignment PIN_Y5 -to DRAM_ADDR[8]
+set_location_assignment PIN_Y6 -to DRAM_ADDR[9]
+set_location_assignment PIN_R5 -to DRAM_ADDR[10]
+set_location_assignment PIN_AA5 -to DRAM_ADDR[11]
+set_location_assignment PIN_Y7 -to DRAM_ADDR[12]
+set_location_assignment PIN_AB7 -to SRAM_ADDR[0]
+set_location_assignment PIN_AD7 -to SRAM_ADDR[1]
+set_location_assignment PIN_AE7 -to SRAM_ADDR[2]
+set_location_assignment PIN_AC7 -to SRAM_ADDR[3]
+set_location_assignment PIN_AB6 -to SRAM_ADDR[4]
+set_location_assignment PIN_AE6 -to SRAM_ADDR[5]
+set_location_assignment PIN_AB5 -to SRAM_ADDR[6]
+set_location_assignment PIN_AC5 -to SRAM_ADDR[7]
+set_location_assignment PIN_AF5 -to SRAM_ADDR[8]
+set_location_assignment PIN_T7 -to SRAM_ADDR[9]
+set_location_assignment PIN_AF2 -to SRAM_ADDR[10]
+set_location_assignment PIN_AD3 -to SRAM_ADDR[11]
+set_location_assignment PIN_AB4 -to SRAM_ADDR[12]
+set_location_assignment PIN_AC3 -to SRAM_ADDR[13]
+set_location_assignment PIN_AA4 -to SRAM_ADDR[14]
+set_location_assignment PIN_AB11 -to SRAM_ADDR[15]
+set_location_assignment PIN_AC11 -to SRAM_ADDR[16]
+set_location_assignment PIN_AB9 -to SRAM_ADDR[17]
+set_location_assignment PIN_AB8 -to SRAM_ADDR[18]
+set_location_assignment PIN_T8 -to SRAM_ADDR[19]
+set_location_assignment PIN_AH3 -to SRAM_DQ[0]
+set_location_assignment PIN_AF4 -to SRAM_DQ[1]
+set_location_assignment PIN_AG4 -to SRAM_DQ[2]
+set_location_assignment PIN_AH4 -to SRAM_DQ[3]
+set_location_assignment PIN_AF6 -to SRAM_DQ[4]
+set_location_assignment PIN_AG6 -to SRAM_DQ[5]
+set_location_assignment PIN_AH6 -to SRAM_DQ[6]
+set_location_assignment PIN_AF7 -to SRAM_DQ[7]
+set_location_assignment PIN_AD1 -to SRAM_DQ[8]
+set_location_assignment PIN_AD2 -to SRAM_DQ[9]
+set_location_assignment PIN_AE2 -to SRAM_DQ[10]
+set_location_assignment PIN_AE1 -to SRAM_DQ[11]
+set_location_assignment PIN_AE3 -to SRAM_DQ[12]
+set_location_assignment PIN_AE4 -to SRAM_DQ[13]
+set_location_assignment PIN_AF3 -to SRAM_DQ[14]
+set_location_assignment PIN_AG3 -to SRAM_DQ[15]
+set_location_assignment PIN_AC4 -to SRAM_UB_N
+set_location_assignment PIN_AD4 -to SRAM_LB_N
+set_location_assignment PIN_AF8 -to SRAM_CE_N
+set_location_assignment PIN_AD5 -to SRAM_OE_N
+set_location_assignment PIN_AE8 -to SRAM_WE_N
+set_location_assignment PIN_AG12 -to FL_ADDR[0]
+set_location_assignment PIN_AH7 -to FL_ADDR[1]
+set_location_assignment PIN_Y13 -to FL_ADDR[2]
+set_location_assignment PIN_Y14 -to FL_ADDR[3]
+set_location_assignment PIN_Y12 -to FL_ADDR[4]
+set_location_assignment PIN_AA13 -to FL_ADDR[5]
+set_location_assignment PIN_AA12 -to FL_ADDR[6]
+set_location_assignment PIN_AB13 -to FL_ADDR[7]
+set_location_assignment PIN_AB12 -to FL_ADDR[8]
+set_location_assignment PIN_AB10 -to FL_ADDR[9]
+set_location_assignment PIN_AE9 -to FL_ADDR[10]
+set_location_assignment PIN_AF9 -to FL_ADDR[11]
+set_location_assignment PIN_AA10 -to FL_ADDR[12]
+set_location_assignment PIN_AD8 -to FL_ADDR[13]
+set_location_assignment PIN_AC8 -to FL_ADDR[14]
+set_location_assignment PIN_Y10 -to FL_ADDR[15]
+set_location_assignment PIN_AA8 -to FL_ADDR[16]
+set_location_assignment PIN_AH12 -to FL_ADDR[17]
+set_location_assignment PIN_AC12 -to FL_ADDR[18]
+set_location_assignment PIN_AD12 -to FL_ADDR[19]
+set_location_assignment PIN_AE10 -to FL_ADDR[20]
+set_location_assignment PIN_AD10 -to FL_ADDR[21]
+set_location_assignment PIN_AD11 -to FL_ADDR[22]
+set_location_assignment PIN_AH8 -to FL_DQ[0]
+set_location_assignment PIN_AF10 -to FL_DQ[1]
+set_location_assignment PIN_AG10 -to FL_DQ[2]
+set_location_assignment PIN_AH10 -to FL_DQ[3]
+set_location_assignment PIN_AF11 -to FL_DQ[4]
+set_location_assignment PIN_AG11 -to FL_DQ[5]
+set_location_assignment PIN_AH11 -to FL_DQ[6]
+set_location_assignment PIN_AF12 -to FL_DQ[7]
+set_location_assignment PIN_AG7 -to FL_CE_N
+set_location_assignment PIN_AG8 -to FL_OE_N
+set_location_assignment PIN_AE11 -to FL_RST_N
+set_location_assignment PIN_Y1 -to FL_RY
+set_location_assignment PIN_AC10 -to FL_WE_N
+set_location_assignment PIN_AE12 -to FL_WP_N
+set_location_assignment PIN_AB22 -to GPIO[0]
+set_location_assignment PIN_AC15 -to GPIO[1]
+set_location_assignment PIN_AB21 -to GPIO[2]
+set_location_assignment PIN_Y17 -to GPIO[3]
+set_location_assignment PIN_AC21 -to GPIO[4]
+set_location_assignment PIN_Y16 -to GPIO[5]
+set_location_assignment PIN_AD21 -to GPIO[6]
+set_location_assignment PIN_AE16 -to GPIO[7]
+set_location_assignment PIN_AD15 -to GPIO[8]
+set_location_assignment PIN_AE15 -to GPIO[9]
+set_location_assignment PIN_AC19 -to GPIO[10]
+set_location_assignment PIN_AF16 -to GPIO[11]
+set_location_assignment PIN_AD19 -to GPIO[12]
+set_location_assignment PIN_AF15 -to GPIO[13]
+set_location_assignment PIN_AF24 -to GPIO[14]
+set_location_assignment PIN_AE21 -to GPIO[15]
+set_location_assignment PIN_AF25 -to GPIO[16]
+set_location_assignment PIN_AC22 -to GPIO[17]
+set_location_assignment PIN_AE22 -to GPIO[18]
+set_location_assignment PIN_AF21 -to GPIO[19]
+set_location_assignment PIN_AF22 -to GPIO[20]
+set_location_assignment PIN_AD22 -to GPIO[21]
+set_location_assignment PIN_AG25 -to GPIO[22]
+set_location_assignment PIN_AD25 -to GPIO[23]
+set_location_assignment PIN_AH25 -to GPIO[24]
+set_location_assignment PIN_AE25 -to GPIO[25]
+set_location_assignment PIN_AG22 -to GPIO[26]
+set_location_assignment PIN_AE24 -to GPIO[27]
+set_location_assignment PIN_AH22 -to GPIO[28]
+set_location_assignment PIN_AF26 -to GPIO[29]
+set_location_assignment PIN_AE20 -to GPIO[30]
+set_location_assignment PIN_AG23 -to GPIO[31]
+set_location_assignment PIN_AF20 -to GPIO[32]
+set_location_assignment PIN_AH26 -to GPIO[33]
+set_location_assignment PIN_AH23 -to GPIO[34]
+set_location_assignment PIN_AG26 -to GPIO[35]
+set_location_assignment PIN_AH15 -to HSMC_CLKIN0
+set_location_assignment PIN_AD28 -to HSMC_CLKOUT0
+set_location_assignment PIN_AE26 -to HSMC_D[0]
+set_location_assignment PIN_AE28 -to HSMC_D[1]
+set_location_assignment PIN_AE27 -to HSMC_D[2]
+set_location_assignment PIN_AF27 -to HSMC_D[3]
+set_location_assignment PIN_J27 -to HSMC_CLKIN_P1
+set_location_assignment PIN_J28 -to HSMC_CLKIN_N1
+set_location_assignment PIN_G23 -to HSMC_CLKOUT_P1
+set_location_assignment PIN_G24 -to HSMC_CLKOUT_N1
+set_location_assignment PIN_Y27 -to HSMC_CLKIN_P2
+set_location_assignment PIN_Y28 -to HSMC_CLKIN_N2
+set_location_assignment PIN_V23 -to HSMC_CLKOUT_P2
+set_location_assignment PIN_V24 -to HSMC_CLKOUT_N2
+set_location_assignment PIN_D27 -to HSMC_TX_D_P[0]
+set_location_assignment PIN_D28 -to HSMC_TX_D_N[0]
+set_location_assignment PIN_E27 -to HSMC_TX_D_P[1]
+set_location_assignment PIN_E28 -to HSMC_TX_D_N[1]
+set_location_assignment PIN_F27 -to HSMC_TX_D_P[2]
+set_location_assignment PIN_F28 -to HSMC_TX_D_N[2]
+set_location_assignment PIN_G27 -to HSMC_TX_D_P[3]
+set_location_assignment PIN_G28 -to HSMC_TX_D_N[3]
+set_location_assignment PIN_K27 -to HSMC_TX_D_P[4]
+set_location_assignment PIN_K28 -to HSMC_TX_D_N[4]
+set_location_assignment PIN_M27 -to HSMC_TX_D_P[5]
+set_location_assignment PIN_M28 -to HSMC_TX_D_N[5]
+set_location_assignment PIN_K21 -to HSMC_TX_D_P[6]
+set_location_assignment PIN_K22 -to HSMC_TX_D_N[6]
+set_location_assignment PIN_H23 -to HSMC_TX_D_P[7]
+set_location_assignment PIN_H24 -to HSMC_TX_D_N[7]
+set_location_assignment PIN_J23 -to HSMC_TX_D_P[8]
+set_location_assignment PIN_J24 -to HSMC_TX_D_N[8]
+set_location_assignment PIN_P27 -to HSMC_TX_D_P[9]
+set_location_assignment PIN_P28 -to HSMC_TX_D_N[9]
+set_location_assignment PIN_J25 -to HSMC_TX_D_P[10]
+set_location_assignment PIN_J26 -to HSMC_TX_D_N[10]
+set_location_assignment PIN_L27 -to HSMC_TX_D_P[11]
+set_location_assignment PIN_L28 -to HSMC_TX_D_N[11]
+set_location_assignment PIN_V25 -to HSMC_TX_D_P[12]
+set_location_assignment PIN_V26 -to HSMC_TX_D_N[12]
+set_location_assignment PIN_R27 -to HSMC_TX_D_P[13]
+set_location_assignment PIN_R28 -to HSMC_TX_D_N[13]
+set_location_assignment PIN_U27 -to HSMC_TX_D_P[14]
+set_location_assignment PIN_U28 -to HSMC_TX_D_N[14]
+set_location_assignment PIN_V27 -to HSMC_TX_D_P[15]
+set_location_assignment PIN_V28 -to HSMC_TX_D_N[15]
+set_location_assignment PIN_U22 -to HSMC_TX_D_P[16]
+set_location_assignment PIN_V22 -to HSMC_TX_D_N[16]
+set_location_assignment PIN_F24 -to HSMC_RX_D_P[0]
+set_location_assignment PIN_F25 -to HSMC_RX_D_N[0]
+set_location_assignment PIN_D26 -to HSMC_RX_D_P[1]
+set_location_assignment PIN_C27 -to HSMC_RX_D_N[1]
+set_location_assignment PIN_F26 -to HSMC_RX_D_P[2]
+set_location_assignment PIN_E26 -to HSMC_RX_D_N[2]
+set_location_assignment PIN_G25 -to HSMC_RX_D_P[3]
+set_location_assignment PIN_G26 -to HSMC_RX_D_N[3]
+set_location_assignment PIN_H25 -to HSMC_RX_D_P[4]
+set_location_assignment PIN_H26 -to HSMC_RX_D_N[4]
+set_location_assignment PIN_K25 -to HSMC_RX_D_P[5]
+set_location_assignment PIN_K26 -to HSMC_RX_D_N[5]
+set_location_assignment PIN_L23 -to HSMC_RX_D_P[6]
+set_location_assignment PIN_L24 -to HSMC_RX_D_N[6]
+set_location_assignment PIN_M25 -to HSMC_RX_D_P[7]
+set_location_assignment PIN_M26 -to HSMC_RX_D_N[7]
+set_location_assignment PIN_R25 -to HSMC_RX_D_P[8]
+set_location_assignment PIN_R26 -to HSMC_RX_D_N[8]
+set_location_assignment PIN_T25 -to HSMC_RX_D_P[9]
+set_location_assignment PIN_T26 -to HSMC_RX_D_N[9]
+set_location_assignment PIN_U25 -to HSMC_RX_D_P[10]
+set_location_assignment PIN_U26 -to HSMC_RX_D_N[10]
+set_location_assignment PIN_L21 -to HSMC_RX_D_P[11]
+set_location_assignment PIN_L22 -to HSMC_RX_D_N[11]
+set_location_assignment PIN_N25 -to HSMC_RX_D_P[12]
+set_location_assignment PIN_N26 -to HSMC_RX_D_N[12]
+set_location_assignment PIN_P25 -to HSMC_RX_D_P[13]
+set_location_assignment PIN_P26 -to HSMC_RX_D_N[13]
+set_location_assignment PIN_P21 -to HSMC_RX_D_P[14]
+set_location_assignment PIN_R21 -to HSMC_RX_D_N[14]
+set_location_assignment PIN_R22 -to HSMC_RX_D_P[15]
+set_location_assignment PIN_R23 -to HSMC_RX_D_N[15]
+set_location_assignment PIN_T21 -to HSMC_RX_D_P[16]
+set_location_assignment PIN_T22 -to HSMC_RX_D_N[16]
+set_location_assignment PIN_J10 -to EX_IO[0]
+set_location_assignment PIN_J14 -to EX_IO[1]
+set_location_assignment PIN_H13 -to EX_IO[2]
+set_location_assignment PIN_H14 -to EX_IO[3]
+set_location_assignment PIN_F14 -to EX_IO[4]
+set_location_assignment PIN_E10 -to EX_IO[5]
+set_location_assignment PIN_D9 -to EX_IO[6]
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/RegisterDemo.qsf.bak b/1ano/2semestre/lsd/pratica04/RegisterDemo/RegisterDemo.qsf.bak
new file mode 100644
index 0000000..4192896
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica04/RegisterDemo/RegisterDemo.qsf.bak
@@ -0,0 +1,65 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2020 Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions
+# and other software and tools, and any partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Intel Program License
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors. Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+# Date created = 12:32:20 March 15, 2023
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+# RegisterDemo_assignment_defaults.qdf
+# If this file doesn't exist, see file:
+# assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus Prime software
+# and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone IV E"
+set_global_assignment -name DEVICE EP4CE115F29C7
+set_global_assignment -name TOP_LEVEL_ENTITY Register8
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:32:20 MARCH 15, 2023"
+set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
+set_global_assignment -name VHDL_FILE Register8.vhd
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name VECTOR_WAVEFORM_FILE Register8.vwf
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/RegisterDemo.qws b/1ano/2semestre/lsd/pratica04/RegisterDemo/RegisterDemo.qws
new file mode 100644
index 0000000..63563b7
Binary files /dev/null and b/1ano/2semestre/lsd/pratica04/RegisterDemo/RegisterDemo.qws differ
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.(0).cnf.cdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.(0).cnf.cdb
new file mode 100644
index 0000000..eb80a2b
Binary files /dev/null and b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.(0).cnf.cdb differ
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.(0).cnf.hdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.(0).cnf.hdb
new file mode 100644
index 0000000..ac1def0
Binary files /dev/null and b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.(0).cnf.hdb differ
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.(1).cnf.cdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.(1).cnf.cdb
new file mode 100644
index 0000000..4d928bd
Binary files /dev/null and b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.(1).cnf.cdb differ
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.(1).cnf.hdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.(1).cnf.hdb
new file mode 100644
index 0000000..4eeca6b
Binary files /dev/null and b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.(1).cnf.hdb differ
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.asm.qmsg b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.asm.qmsg
new file mode 100644
index 0000000..bdc79f1
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.asm.qmsg
@@ -0,0 +1,7 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1679476798910 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1679476798911 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 22 09:19:58 2023 " "Processing started: Wed Mar 22 09:19:58 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1679476798911 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1679476798911 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RegisterDemo -c RegisterDemo " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RegisterDemo -c RegisterDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1679476798911 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1679476799262 ""}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1679476803465 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1679476803646 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "364 " "Peak virtual memory: 364 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679476804192 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 22 09:20:04 2023 " "Processing ended: Wed Mar 22 09:20:04 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679476804192 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679476804192 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679476804192 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1679476804192 ""}
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.asm.rdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.asm.rdb
new file mode 100644
index 0000000..7935eb6
Binary files /dev/null and b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.asm.rdb differ
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.asm_labs.ddb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.asm_labs.ddb
new file mode 100644
index 0000000..fe56162
Binary files /dev/null and b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.asm_labs.ddb differ
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.cbx.xml b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.cbx.xml
new file mode 100644
index 0000000..c0a111c
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.cbx.xml
@@ -0,0 +1,5 @@
+
+
+
+
+
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.cmp.bpm b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.cmp.bpm
new file mode 100644
index 0000000..b79a790
Binary files /dev/null and b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.cmp.bpm differ
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.cmp.cdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.cmp.cdb
new file mode 100644
index 0000000..c326152
Binary files /dev/null and b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.cmp.cdb differ
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.cmp.hdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.cmp.hdb
new file mode 100644
index 0000000..5be2cf6
Binary files /dev/null and b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.cmp.hdb differ
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.cmp.idb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.cmp.idb
new file mode 100644
index 0000000..93056c6
Binary files /dev/null and b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.cmp.idb differ
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.cmp.logdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.cmp.logdb
new file mode 100644
index 0000000..40b57b0
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.cmp.logdb
@@ -0,0 +1,60 @@
+v1
+IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
+IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
+IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
+IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,,
+IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
+IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
+IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000001;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000047;IO_000046;IO_000045;IO_000027;IO_000026;IO_000024;IO_000023;IO_000022;IO_000021;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000033;IO_000034;IO_000042,
+IO_RULES_MATRIX,Total Pass,0;18;18;0;0;18;18;0;0;0;0;0;0;8;0;0;0;10;8;0;10;0;0;8;0;18;18;18;0;0,
+IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Total Inapplicable,18;0;0;18;18;0;0;18;18;18;18;18;18;10;18;18;18;8;10;18;8;18;18;10;18;0;0;0;18;18,
+IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,LEDR[7],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDR[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDR[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDR[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDR[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDR[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDR[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,LEDR[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[7],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,KEY[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[8],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,SW[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
+IO_RULES_SUMMARY,Total I/O Rules,30,
+IO_RULES_SUMMARY,Number of I/O Rules Passed,12,
+IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
+IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
+IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,18,
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.cmp.rdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.cmp.rdb
new file mode 100644
index 0000000..b484974
Binary files /dev/null and b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.cmp.rdb differ
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.cmp_merge.kpt b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.cmp_merge.kpt
new file mode 100644
index 0000000..e91f4e8
Binary files /dev/null and b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.cmp_merge.kpt differ
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
new file mode 100644
index 0000000..d9c61ce
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diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.db_info b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.db_info
new file mode 100644
index 0000000..83b814d
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+Version_Index = 520278016
+Creation_Time = Wed Mar 22 09:08:32 2023
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.eda.qmsg b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.eda.qmsg
new file mode 100644
index 0000000..fbd9692
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.eda.qmsg
@@ -0,0 +1,6 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1679476809390 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1679476809391 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 22 09:20:09 2023 " "Processing started: Wed Mar 22 09:20:09 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1679476809391 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1679476809391 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off RegisterDemo -c RegisterDemo " "Command: quartus_eda --read_settings_files=off --write_settings_files=off RegisterDemo -c RegisterDemo" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1679476809391 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1679476809824 ""}
+{ "Info" "IWSC_DONE_HDL_GENERATION" "RegisterDemo.vho /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/modelsim/ simulation " "Generated file RegisterDemo.vho in folder \"/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1679476809899 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "612 " "Peak virtual memory: 612 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679476809929 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 22 09:20:09 2023 " "Processing ended: Wed Mar 22 09:20:09 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679476809929 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679476809929 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679476809929 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1679476809929 ""}
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.fit.qmsg b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.fit.qmsg
new file mode 100644
index 0000000..01b8ce2
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.fit.qmsg
@@ -0,0 +1,46 @@
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1679476780815 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1679476780815 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "RegisterDemo EP4CE115F29C7 " "Selected device EP4CE115F29C7 for design \"RegisterDemo\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1679476780820 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1679476780960 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1679476780960 ""}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1679476781655 ""}
+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1679476781665 ""}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29C7 " "Device EP4CE40F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679476781923 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29I7 " "Device EP4CE40F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679476781923 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29C7 " "Device EP4CE30F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679476781923 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29I7 " "Device EP4CE30F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679476781923 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29C7 " "Device EP4CE55F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679476781923 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29I7 " "Device EP4CE55F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679476781923 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29C7 " "Device EP4CE75F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679476781923 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29I7 " "Device EP4CE75F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679476781923 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE115F29I7 " "Device EP4CE115F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679476781923 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1679476781923 ""}
+{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ F4 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/" { { 0 { 0 ""} 0 594 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1679476781929 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/" { { 0 { 0 ""} 0 596 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1679476781929 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ P3 " "Pin ~ALTERA_DCLK~ is reserved at location P3" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/" { { 0 { 0 ""} 0 598 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1679476781929 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ N7 " "Pin ~ALTERA_DATA0~ is reserved at location N7" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/" { { 0 { 0 ""} 0 600 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1679476781929 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ P28 " "Pin ~ALTERA_nCEO~ is reserved at location P28" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/" { { 0 { 0 ""} 0 602 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1679476781929 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1679476781929 ""}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1679476781939 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RegisterDemo.sdc " "Synopsys Design Constraints File file not found: 'RegisterDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1679476783502 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1679476783503 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1679476783512 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1679476783512 ""}
+{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1679476783513 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1679476783864 ""}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1679476783864 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1679476783865 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1679476783866 ""}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1679476783866 ""}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1679476783867 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1679476783867 ""}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1679476783867 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1679476783876 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1679476783876 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1679476783876 ""}
+{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCDAT " "Node \"AUD_ADCDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCLRCK " "Node \"AUD_ADCLRCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_BCLK " "Node \"AUD_BCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACDAT " "Node \"AUD_DACDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_DACDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACLRCK " "Node \"AUD_DACLRCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_XCK " "Node \"AUD_XCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_XCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK2_50 " "Node \"CLOCK2_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK2_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK3_50 " "Node \"CLOCK3_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK3_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK_50 " "Node \"CLOCK_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[0\] " "Node \"DRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[1\] " "Node \"DRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[0\] " "Node \"DRAM_DQM\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[1\] " "Node \"DRAM_DQM\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[2\] " "Node \"DRAM_DQM\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[3\] " "Node \"DRAM_DQM\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[16\] " "Node \"DRAM_DQ\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[17\] " "Node \"DRAM_DQ\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[18\] " "Node \"DRAM_DQ\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[19\] " "Node \"DRAM_DQ\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[20\] " "Node \"DRAM_DQ\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[21\] " "Node \"DRAM_DQ\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[22\] " "Node \"DRAM_DQ\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[23\] " "Node \"DRAM_DQ\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[24\] " "Node \"DRAM_DQ\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[25\] " "Node \"DRAM_DQ\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[26\] " "Node \"DRAM_DQ\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[27\] " "Node \"DRAM_DQ\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[28\] " "Node \"DRAM_DQ\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[29\] " "Node \"DRAM_DQ\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[30\] " "Node \"DRAM_DQ\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[31\] " "Node \"DRAM_DQ\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SCLK " "Node \"EEP_I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SDAT " "Node \"EEP_I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_GTX_CLK " "Node \"ENET0_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_INT_N " "Node \"ENET0_INT_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_INT_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_LINK100 " "Node \"ENET0_LINK100\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_LINK100" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDC " "Node \"ENET0_MDC\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDIO " "Node \"ENET0_MDIO\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_MDIO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RST_N " "Node \"ENET0_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_CLK " "Node \"ENET0_RX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_COL " "Node \"ENET0_RX_COL\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_COL" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_CRS " "Node \"ENET0_RX_CRS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CRS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[0\] " "Node \"ENET0_RX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[1\] " "Node \"ENET0_RX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[2\] " "Node \"ENET0_RX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[3\] " "Node \"ENET0_RX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DV " "Node \"ENET0_RX_DV\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DV" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_ER " "Node \"ENET0_RX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_CLK " "Node \"ENET0_TX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[0\] " "Node \"ENET0_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[1\] " "Node \"ENET0_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[2\] " "Node \"ENET0_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[3\] " "Node \"ENET0_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_EN " "Node \"ENET0_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_ER " "Node \"ENET0_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_GTX_CLK " "Node \"ENET1_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_INT_N " "Node \"ENET1_INT_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_INT_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_LINK100 " "Node \"ENET1_LINK100\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_LINK100" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDC " "Node \"ENET1_MDC\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDIO " "Node \"ENET1_MDIO\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_MDIO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RST_N " "Node \"ENET1_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_CLK " "Node \"ENET1_RX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_COL " "Node \"ENET1_RX_COL\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_COL" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_CRS " "Node \"ENET1_RX_CRS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CRS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[0\] " "Node \"ENET1_RX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[1\] " "Node \"ENET1_RX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[2\] " "Node \"ENET1_RX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[3\] " "Node \"ENET1_RX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DV " "Node \"ENET1_RX_DV\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DV" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_ER " "Node \"ENET1_RX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_CLK " "Node \"ENET1_TX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[0\] " "Node \"ENET1_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[1\] " "Node \"ENET1_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[2\] " "Node \"ENET1_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[3\] " "Node \"ENET1_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_EN " "Node \"ENET1_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_ER " "Node \"ENET1_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENETCLK_25 " "Node \"ENETCLK_25\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENETCLK_25" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[0\] " "Node \"EX_IO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[1\] " "Node \"EX_IO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[2\] " "Node \"EX_IO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[3\] " "Node \"EX_IO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[4\] " "Node \"EX_IO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[5\] " "Node \"EX_IO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[6\] " "Node \"EX_IO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[0\] " "Node \"FL_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[10\] " "Node \"FL_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[11\] " "Node \"FL_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[12\] " "Node \"FL_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[13\] " "Node \"FL_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[14\] " "Node \"FL_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[15\] " "Node \"FL_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[16\] " "Node \"FL_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[17\] " "Node \"FL_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[18\] " "Node \"FL_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[19\] " "Node \"FL_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[1\] " "Node \"FL_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[20\] " "Node \"FL_ADDR\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[21\] " "Node \"FL_ADDR\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[22\] " "Node \"FL_ADDR\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[2\] " "Node \"FL_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[3\] " "Node \"FL_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[4\] " "Node \"FL_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[5\] " "Node \"FL_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[6\] " "Node \"FL_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[7\] " "Node \"FL_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[8\] " "Node \"FL_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[9\] " "Node \"FL_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_CE_N " "Node \"FL_CE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[0\] " "Node \"FL_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[1\] " "Node \"FL_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[2\] " "Node \"FL_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[3\] " "Node \"FL_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[4\] " "Node \"FL_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[5\] " "Node \"FL_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[6\] " "Node \"FL_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[7\] " "Node \"FL_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_OE_N " "Node \"FL_OE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RST_N " "Node \"FL_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RY " "Node \"FL_RY\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_RY" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WE_N " "Node \"FL_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WP_N " "Node \"FL_WP_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[0\] " "Node \"GPIO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[10\] " "Node \"GPIO\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[11\] " "Node \"GPIO\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[12\] " "Node \"GPIO\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[13\] " "Node \"GPIO\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[14\] " "Node \"GPIO\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[15\] " "Node \"GPIO\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[16\] " "Node \"GPIO\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[17\] " "Node \"GPIO\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[18\] " "Node \"GPIO\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[19\] " "Node \"GPIO\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[1\] " "Node \"GPIO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[20\] " "Node \"GPIO\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[21\] " "Node \"GPIO\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[22\] " "Node \"GPIO\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[23\] " "Node \"GPIO\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[24\] " "Node \"GPIO\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[25\] " "Node \"GPIO\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[26\] " "Node \"GPIO\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[27\] " "Node \"GPIO\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[28\] " "Node \"GPIO\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[29\] " "Node \"GPIO\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[2\] " "Node \"GPIO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[30\] " "Node \"GPIO\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[31\] " "Node \"GPIO\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[32\] " "Node \"GPIO\[32\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[33\] " "Node \"GPIO\[33\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[34\] " "Node \"GPIO\[34\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[34\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[35\] " "Node \"GPIO\[35\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[35\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[3\] " "Node \"GPIO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[4\] " "Node \"GPIO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[5\] " "Node \"GPIO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[6\] " "Node \"GPIO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[7\] " "Node \"GPIO\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[8\] " "Node \"GPIO\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[9\] " "Node \"GPIO\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[0\] " "Node \"HEX0\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[1\] " "Node \"HEX0\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[2\] " "Node \"HEX0\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[3\] " "Node \"HEX0\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[4\] " "Node \"HEX0\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[5\] " "Node \"HEX0\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[6\] " "Node \"HEX0\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[0\] " "Node \"HEX1\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[1\] " "Node \"HEX1\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[2\] " "Node \"HEX1\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[3\] " "Node \"HEX1\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[4\] " "Node \"HEX1\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[5\] " "Node \"HEX1\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[6\] " "Node \"HEX1\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[0\] " "Node \"HEX2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[1\] " "Node \"HEX2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[2\] " "Node \"HEX2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[3\] " "Node \"HEX2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[4\] " "Node \"HEX2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[5\] " "Node \"HEX2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[6\] " "Node \"HEX2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[0\] " "Node \"HEX3\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[1\] " "Node \"HEX3\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[2\] " "Node \"HEX3\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[3\] " "Node \"HEX3\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[4\] " "Node \"HEX3\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[5\] " "Node \"HEX3\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[6\] " "Node \"HEX3\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[0\] " "Node \"HEX4\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[1\] " "Node \"HEX4\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[2\] " "Node \"HEX4\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[3\] " "Node \"HEX4\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[4\] " "Node \"HEX4\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[5\] " "Node \"HEX4\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[6\] " "Node \"HEX4\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[0\] " "Node \"HEX6\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[1\] " "Node \"HEX6\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[2\] " "Node \"HEX6\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[3\] " "Node \"HEX6\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[4\] " "Node \"HEX6\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[5\] " "Node \"HEX6\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[6\] " "Node \"HEX6\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[0\] " "Node \"HEX7\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[1\] " "Node \"HEX7\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[2\] " "Node \"HEX7\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[3\] " "Node \"HEX7\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[4\] " "Node \"HEX7\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[5\] " "Node \"HEX7\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[6\] " "Node \"HEX7\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN0 " "Node \"HSMC_CLKIN0\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N1 " "Node \"HSMC_CLKIN_N1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N2 " "Node \"HSMC_CLKIN_N2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P1 " "Node \"HSMC_CLKIN_P1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P2 " "Node \"HSMC_CLKIN_P2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT0 " "Node \"HSMC_CLKOUT0\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N1 " "Node \"HSMC_CLKOUT_N1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N2 " "Node \"HSMC_CLKOUT_N2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P1 " "Node \"HSMC_CLKOUT_P1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P2 " "Node \"HSMC_CLKOUT_P2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[0\] " "Node \"HSMC_D\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[1\] " "Node \"HSMC_D\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[2\] " "Node \"HSMC_D\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[3\] " "Node \"HSMC_D\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[0\] " "Node \"HSMC_RX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[10\] " "Node \"HSMC_RX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[11\] " "Node \"HSMC_RX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[12\] " "Node \"HSMC_RX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[13\] " "Node \"HSMC_RX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[14\] " "Node \"HSMC_RX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[15\] " "Node \"HSMC_RX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[16\] " "Node \"HSMC_RX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[1\] " "Node \"HSMC_RX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[2\] " "Node \"HSMC_RX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[3\] " "Node \"HSMC_RX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[4\] " "Node \"HSMC_RX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[5\] " "Node \"HSMC_RX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[6\] " "Node \"HSMC_RX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[7\] " "Node \"HSMC_RX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[8\] " "Node \"HSMC_RX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[9\] " "Node \"HSMC_RX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[0\] " "Node \"HSMC_RX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[10\] " "Node \"HSMC_RX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[11\] " "Node \"HSMC_RX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[12\] " "Node \"HSMC_RX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[13\] " "Node \"HSMC_RX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[14\] " "Node \"HSMC_RX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[15\] " "Node \"HSMC_RX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[16\] " "Node \"HSMC_RX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[1\] " "Node \"HSMC_RX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[2\] " "Node \"HSMC_RX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[3\] " "Node \"HSMC_RX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[4\] " "Node \"HSMC_RX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[5\] " "Node \"HSMC_RX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[6\] " "Node \"HSMC_RX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[7\] " "Node \"HSMC_RX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[8\] " "Node \"HSMC_RX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[9\] " "Node \"HSMC_RX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[0\] " "Node \"HSMC_TX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[10\] " "Node \"HSMC_TX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[11\] " "Node \"HSMC_TX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[12\] " "Node \"HSMC_TX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[13\] " "Node \"HSMC_TX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[14\] " "Node \"HSMC_TX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[15\] " "Node \"HSMC_TX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[16\] " "Node \"HSMC_TX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[1\] " "Node \"HSMC_TX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[2\] " "Node \"HSMC_TX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[3\] " "Node \"HSMC_TX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[4\] " "Node \"HSMC_TX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[5\] " "Node \"HSMC_TX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[6\] " "Node \"HSMC_TX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[7\] " "Node \"HSMC_TX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[8\] " "Node \"HSMC_TX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[9\] " "Node \"HSMC_TX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[0\] " "Node \"HSMC_TX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[10\] " "Node \"HSMC_TX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[11\] " "Node \"HSMC_TX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[12\] " "Node \"HSMC_TX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[13\] " "Node \"HSMC_TX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[14\] " "Node \"HSMC_TX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[15\] " "Node \"HSMC_TX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[16\] " "Node \"HSMC_TX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[1\] " "Node \"HSMC_TX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[2\] " "Node \"HSMC_TX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[3\] " "Node \"HSMC_TX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[4\] " "Node \"HSMC_TX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[5\] " "Node \"HSMC_TX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[6\] " "Node \"HSMC_TX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[7\] " "Node \"HSMC_TX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[8\] " "Node \"HSMC_TX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[9\] " "Node \"HSMC_TX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SCLK " "Node \"I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SDAT " "Node \"I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "IRDA_RXD " "Node \"IRDA_RXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "IRDA_RXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[1\] " "Node \"KEY\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[2\] " "Node \"KEY\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[3\] " "Node \"KEY\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_BLON " "Node \"LCD_BLON\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_BLON" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[0\] " "Node \"LCD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[1\] " "Node \"LCD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[2\] " "Node \"LCD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[3\] " "Node \"LCD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[4\] " "Node \"LCD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[5\] " "Node \"LCD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[6\] " "Node \"LCD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[7\] " "Node \"LCD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_EN " "Node \"LCD_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_ON " "Node \"LCD_ON\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_ON" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RS " "Node \"LCD_RS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_RS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RW " "Node \"LCD_RW\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_RW" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[0\] " "Node \"LEDG\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[1\] " "Node \"LEDG\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[2\] " "Node \"LEDG\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[3\] " "Node \"LEDG\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[4\] " "Node \"LEDG\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[5\] " "Node \"LEDG\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[6\] " "Node \"LEDG\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[7\] " "Node \"LEDG\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[8\] " "Node \"LEDG\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[10\] " "Node \"LEDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[11\] " "Node \"LEDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[12\] " "Node \"LEDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[13\] " "Node \"LEDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[14\] " "Node \"LEDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[15\] " "Node \"LEDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[16\] " "Node \"LEDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[17\] " "Node \"LEDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[0\] " "Node \"OTG_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[1\] " "Node \"OTG_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_CS_N " "Node \"OTG_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[0\] " "Node \"OTG_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[10\] " "Node \"OTG_DATA\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[11\] " "Node \"OTG_DATA\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[12\] " "Node \"OTG_DATA\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[13\] " "Node \"OTG_DATA\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[14\] " "Node \"OTG_DATA\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[15\] " "Node \"OTG_DATA\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[1\] " "Node \"OTG_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[2\] " "Node \"OTG_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[3\] " "Node \"OTG_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[4\] " "Node \"OTG_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[5\] " "Node \"OTG_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[6\] " "Node \"OTG_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[7\] " "Node \"OTG_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[8\] " "Node \"OTG_DATA\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[9\] " "Node \"OTG_DATA\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DREQ\[0\] " "Node \"OTG_DREQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DREQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_INT " "Node \"OTG_INT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_INT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RD_N " "Node \"OTG_RD_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_RD_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RST_N " "Node \"OTG_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_WR_N " "Node \"OTG_WR_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_WR_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK " "Node \"PS2_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK2 " "Node \"PS2_CLK2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_CLK2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT " "Node \"PS2_DAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT2 " "Node \"PS2_DAT2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_DAT2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CLK " "Node \"SD_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CMD " "Node \"SD_CMD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_CMD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[0\] " "Node \"SD_DAT\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[1\] " "Node \"SD_DAT\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[2\] " "Node \"SD_DAT\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[3\] " "Node \"SD_DAT\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_WP_N " "Node \"SD_WP_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKIN " "Node \"SMA_CLKIN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SMA_CLKIN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKOUT " "Node \"SMA_CLKOUT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SMA_CLKOUT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[0\] " "Node \"SRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[10\] " "Node \"SRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[11\] " "Node \"SRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[12\] " "Node \"SRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[13\] " "Node \"SRAM_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[14\] " "Node \"SRAM_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[15\] " "Node \"SRAM_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[16\] " "Node \"SRAM_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[17\] " "Node \"SRAM_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[18\] " "Node \"SRAM_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[19\] " "Node \"SRAM_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[1\] " "Node \"SRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[2\] " "Node \"SRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[3\] " "Node \"SRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[4\] " "Node \"SRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[5\] " "Node \"SRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[6\] " "Node \"SRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[7\] " "Node \"SRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[8\] " "Node \"SRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[9\] " "Node \"SRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_CE_N " "Node \"SRAM_CE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[0\] " "Node \"SRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[10\] " "Node \"SRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[11\] " "Node \"SRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[12\] " "Node \"SRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[13\] " "Node \"SRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[14\] " "Node \"SRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[15\] " "Node \"SRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[1\] " "Node \"SRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[2\] " "Node \"SRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[3\] " "Node \"SRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[4\] " "Node \"SRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[5\] " "Node \"SRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[6\] " "Node \"SRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[7\] " "Node \"SRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[8\] " "Node \"SRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[9\] " "Node \"SRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_LB_N " "Node \"SRAM_LB_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_LB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_OE_N " "Node \"SRAM_OE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_UB_N " "Node \"SRAM_UB_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_UB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_WE_N " "Node \"SRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[10\] " "Node \"SW\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[11\] " "Node \"SW\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[12\] " "Node \"SW\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[13\] " "Node \"SW\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[14\] " "Node \"SW\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[15\] " "Node \"SW\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[16\] " "Node \"SW\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[17\] " "Node \"SW\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SW\[9\] " "Node \"SW\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_CLK27 " "Node \"TD_CLK27\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_CLK27" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[0\] " "Node \"TD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[1\] " "Node \"TD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[2\] " "Node \"TD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[3\] " "Node \"TD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[4\] " "Node \"TD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[5\] " "Node \"TD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[6\] " "Node \"TD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[7\] " "Node \"TD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_HS " "Node \"TD_HS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_RESET_N " "Node \"TD_RESET_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_RESET_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_VS " "Node \"TD_VS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_CTS " "Node \"UART_CTS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_CTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RTS " "Node \"UART_RTS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_RTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RXD " "Node \"UART_RXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_RXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_TXD " "Node \"UART_TXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_TXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_BLANK_N " "Node \"VGA_BLANK_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_BLANK_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[0\] " "Node \"VGA_B\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[1\] " "Node \"VGA_B\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[2\] " "Node \"VGA_B\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[3\] " "Node \"VGA_B\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[4\] " "Node \"VGA_B\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[5\] " "Node \"VGA_B\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[6\] " "Node \"VGA_B\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[7\] " "Node \"VGA_B\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_CLK " "Node \"VGA_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[0\] " "Node \"VGA_G\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[1\] " "Node \"VGA_G\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[2\] " "Node \"VGA_G\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[3\] " "Node \"VGA_G\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[4\] " "Node \"VGA_G\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[5\] " "Node \"VGA_G\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[6\] " "Node \"VGA_G\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[7\] " "Node \"VGA_G\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_HS " "Node \"VGA_HS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[0\] " "Node \"VGA_R\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[1\] " "Node \"VGA_R\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[2\] " "Node \"VGA_R\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[3\] " "Node \"VGA_R\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[4\] " "Node \"VGA_R\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[5\] " "Node \"VGA_R\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[6\] " "Node \"VGA_R\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[7\] " "Node \"VGA_R\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_SYNC_N " "Node \"VGA_SYNC_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_SYNC_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_VS " "Node \"VGA_VS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679476783924 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1679476783924 ""}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:02 " "Fitter preparation operations ending: elapsed time is 00:00:02" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1679476783945 ""}
+{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1679476783953 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1679476787519 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1679476787725 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1679476787806 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1679476788347 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1679476788347 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1679476788799 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X104_Y37 X115_Y48 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X104_Y37 to location X115_Y48" { } { { "loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X104_Y37 to location X115_Y48"} { { 12 { 0 ""} 104 37 12 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1679476794390 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1679476794390 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1679476794649 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1679476794649 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1679476794649 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1679476794651 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.03 " "Total time spent on timing analysis during the Fitter is 0.03 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1679476794847 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1679476794857 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1679476795309 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1679476795309 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1679476795724 ""}
+{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:02 " "Fitter post-fit operations ending: elapsed time is 00:00:02" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1679476796365 ""}
+{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1679476796816 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.fit.smsg " "Generated suppressed messages file /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1679476796921 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 507 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 507 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1151 " "Peak virtual memory: 1151 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679476797269 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 22 09:19:57 2023 " "Processing ended: Wed Mar 22 09:19:57 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679476797269 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:17 " "Elapsed time: 00:00:17" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679476797269 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:24 " "Total CPU time (on all processors): 00:00:24" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679476797269 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1679476797269 ""}
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.hier_info b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.hier_info
new file mode 100644
index 0000000..ce19507
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.hier_info
@@ -0,0 +1,56 @@
+|RegisterDemo
+LEDR[0] <= Register8:inst.dataOut[0]
+LEDR[1] <= Register8:inst.dataOut[1]
+LEDR[2] <= Register8:inst.dataOut[2]
+LEDR[3] <= Register8:inst.dataOut[3]
+LEDR[4] <= Register8:inst.dataOut[4]
+LEDR[5] <= Register8:inst.dataOut[5]
+LEDR[6] <= Register8:inst.dataOut[6]
+LEDR[7] <= Register8:inst.dataOut[7]
+KEY[0] => Register8:inst.clk
+SW[0] => Register8:inst.dataIn[0]
+SW[1] => Register8:inst.dataIn[1]
+SW[2] => Register8:inst.dataIn[2]
+SW[3] => Register8:inst.dataIn[3]
+SW[4] => Register8:inst.dataIn[4]
+SW[5] => Register8:inst.dataIn[5]
+SW[6] => Register8:inst.dataIn[6]
+SW[7] => Register8:inst.dataIn[7]
+SW[8] => Register8:inst.wrEn
+
+
+|RegisterDemo|Register8:inst
+dataIn[0] => dataOut[0]~reg0.DATAIN
+dataIn[1] => dataOut[1]~reg0.DATAIN
+dataIn[2] => dataOut[2]~reg0.DATAIN
+dataIn[3] => dataOut[3]~reg0.DATAIN
+dataIn[4] => dataOut[4]~reg0.DATAIN
+dataIn[5] => dataOut[5]~reg0.DATAIN
+dataIn[6] => dataOut[6]~reg0.DATAIN
+dataIn[7] => dataOut[7]~reg0.DATAIN
+clk => dataOut[0]~reg0.CLK
+clk => dataOut[1]~reg0.CLK
+clk => dataOut[2]~reg0.CLK
+clk => dataOut[3]~reg0.CLK
+clk => dataOut[4]~reg0.CLK
+clk => dataOut[5]~reg0.CLK
+clk => dataOut[6]~reg0.CLK
+clk => dataOut[7]~reg0.CLK
+wrEn => dataOut[0]~reg0.ENA
+wrEn => dataOut[1]~reg0.ENA
+wrEn => dataOut[2]~reg0.ENA
+wrEn => dataOut[3]~reg0.ENA
+wrEn => dataOut[4]~reg0.ENA
+wrEn => dataOut[5]~reg0.ENA
+wrEn => dataOut[6]~reg0.ENA
+wrEn => dataOut[7]~reg0.ENA
+dataOut[0] <= dataOut[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+dataOut[1] <= dataOut[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+dataOut[2] <= dataOut[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+dataOut[3] <= dataOut[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+dataOut[4] <= dataOut[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+dataOut[5] <= dataOut[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+dataOut[6] <= dataOut[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+dataOut[7] <= dataOut[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.hif b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.hif
new file mode 100644
index 0000000..84e109f
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diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.lpc.html b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.lpc.html
new file mode 100644
index 0000000..d666a97
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.lpc.html
@@ -0,0 +1,34 @@
+
+
+| Hierarchy |
+Input |
+Constant Input |
+Unused Input |
+Floating Input |
+Output |
+Constant Output |
+Unused Output |
+Floating Output |
+Bidir |
+Constant Bidir |
+Unused Bidir |
+Input only Bidir |
+Output only Bidir |
+
+
+| inst |
+10 |
+0 |
+0 |
+0 |
+8 |
+0 |
+0 |
+0 |
+0 |
+0 |
+0 |
+0 |
+0 |
+
+
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.lpc.rdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.lpc.rdb
new file mode 100644
index 0000000..9a2dd17
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diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.lpc.txt b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.lpc.txt
new file mode 100644
index 0000000..dfec3a3
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.lpc.txt
@@ -0,0 +1,7 @@
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; inst ; 10 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.map.ammdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.map.ammdb
new file mode 100644
index 0000000..790b913
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diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.map.bpm b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.map.bpm
new file mode 100644
index 0000000..852de38
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diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.map.cdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.map.cdb
new file mode 100644
index 0000000..3210da8
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diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.map.hdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.map.hdb
new file mode 100644
index 0000000..6e29a54
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diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.map.kpt b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.map.kpt
new file mode 100644
index 0000000..e7a7f67
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diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.map.logdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.map.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.map.logdb
@@ -0,0 +1 @@
+v1
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.map.qmsg b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.map.qmsg
new file mode 100644
index 0000000..8864fa9
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.map.qmsg
@@ -0,0 +1,13 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1679476766975 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1679476766976 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 22 09:19:26 2023 " "Processing started: Wed Mar 22 09:19:26 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1679476766976 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679476766976 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RegisterDemo -c RegisterDemo " "Command: quartus_map --read_settings_files=on --write_settings_files=off RegisterDemo -c RegisterDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679476766976 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1679476767318 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1679476767318 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Register8.vhd 2 1 " "Found 2 design units, including 1 entities, in source file Register8.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Register8-Behavioral " "Found design unit 1: Register8-Behavioral" { } { { "Register8.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/Register8.vhd" 14 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679476777398 ""} { "Info" "ISGN_ENTITY_NAME" "1 Register8 " "Found entity 1: Register8" { } { { "Register8.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/Register8.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679476777398 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679476777398 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "RegisterDemo.bdf 1 1 " "Found 1 design units, including 1 entities, in source file RegisterDemo.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 RegisterDemo " "Found entity 1: RegisterDemo" { } { { "RegisterDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/RegisterDemo.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679476777404 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679476777404 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "RegisterDemo " "Elaborating entity \"RegisterDemo\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1679476777479 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Register8 Register8:inst " "Elaborating entity \"Register8\" for hierarchy \"Register8:inst\"" { } { { "RegisterDemo.bdf" "inst" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/RegisterDemo.bdf" { { 184 408 600 296 "inst" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1679476777485 ""}
+{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1679476778374 ""}
+{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1679476779182 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1679476779182 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "26 " "Implemented 26 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "10 " "Implemented 10 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1679476779225 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1679476779225 ""} { "Info" "ICUT_CUT_TM_LCELLS" "8 " "Implemented 8 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1679476779225 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1679476779225 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "429 " "Peak virtual memory: 429 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679476779234 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 22 09:19:39 2023 " "Processing ended: Wed Mar 22 09:19:39 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679476779234 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Elapsed time: 00:00:13" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679476779234 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:32 " "Total CPU time (on all processors): 00:00:32" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679476779234 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1679476779234 ""}
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.map.rdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.map.rdb
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index 0000000..91f6e22
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diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.map_bb.cdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.map_bb.cdb
new file mode 100644
index 0000000..7fb04a3
Binary files /dev/null and b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.map_bb.cdb differ
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.map_bb.hdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.map_bb.hdb
new file mode 100644
index 0000000..ce97220
Binary files /dev/null and b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.map_bb.hdb differ
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.map_bb.logdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.map_bb.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.map_bb.logdb
@@ -0,0 +1 @@
+v1
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.pre_map.hdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.pre_map.hdb
new file mode 100644
index 0000000..79a73bf
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diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.root_partition.map.reg_db.cdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.root_partition.map.reg_db.cdb
new file mode 100644
index 0000000..3bda29b
Binary files /dev/null and b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.root_partition.map.reg_db.cdb differ
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.routing.rdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.routing.rdb
new file mode 100644
index 0000000..b851c5d
Binary files /dev/null and b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.routing.rdb differ
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.rtlv.hdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.rtlv.hdb
new file mode 100644
index 0000000..7c8f560
Binary files /dev/null and b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.rtlv.hdb differ
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.rtlv_sg.cdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.rtlv_sg.cdb
new file mode 100644
index 0000000..bd1a389
Binary files /dev/null and b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.rtlv_sg.cdb differ
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.rtlv_sg_swap.cdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.rtlv_sg_swap.cdb
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index 0000000..8863e01
Binary files /dev/null and b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.rtlv_sg_swap.cdb differ
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.sld_design_entry.sci b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.sld_design_entry.sci
new file mode 100644
index 0000000..7d39add
Binary files /dev/null and b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.sld_design_entry.sci differ
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.sld_design_entry_dsc.sci b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.sld_design_entry_dsc.sci
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index 0000000..7d39add
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diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.smart_action.txt b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.smart_action.txt
new file mode 100644
index 0000000..c8e8a13
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.smart_action.txt
@@ -0,0 +1 @@
+DONE
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.sta.qmsg b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.sta.qmsg
new file mode 100644
index 0000000..ec0a272
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.sta.qmsg
@@ -0,0 +1,44 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1679476805482 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1679476805483 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 22 09:20:05 2023 " "Processing started: Wed Mar 22 09:20:05 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1679476805483 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1679476805483 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RegisterDemo -c RegisterDemo " "Command: quartus_sta RegisterDemo -c RegisterDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1679476805483 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1679476805547 ""}
+{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1679476805713 ""}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1679476805713 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679476805835 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679476805835 ""}
+{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RegisterDemo.sdc " "Synopsys Design Constraints File file not found: 'RegisterDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1679476806667 ""}
+{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1679476806667 ""}
+{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name KEY\[0\] KEY\[0\] " "create_clock -period 1.000 -name KEY\[0\] KEY\[0\]" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1679476806668 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1679476806668 ""}
+{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1679476806669 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1679476806669 ""}
+{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1679476806670 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1679476806679 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679476806680 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679476806686 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679476806687 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679476806688 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679476806689 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1679476806689 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1679476806689 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679476806690 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679476806690 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -13.280 KEY\[0\] " " -3.000 -13.280 KEY\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679476806690 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679476806690 ""}
+{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1679476806708 ""}
+{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1679476806747 ""}
+{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1679476807280 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1679476807315 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679476807316 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679476807317 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679476807319 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679476807320 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679476807321 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1679476807321 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1679476807321 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679476807322 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679476807322 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -13.280 KEY\[0\] " " -3.000 -13.280 KEY\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679476807322 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679476807322 ""}
+{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1679476807338 ""}
+{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1679476807441 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679476807442 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679476807444 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679476807445 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679476807446 ""}
+{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1679476807446 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1679476807446 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679476807447 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679476807447 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -11.696 KEY\[0\] " " -3.000 -11.696 KEY\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679476807447 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679476807447 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1679476808049 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1679476808050 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "534 " "Peak virtual memory: 534 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679476808076 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 22 09:20:08 2023 " "Processing ended: Wed Mar 22 09:20:08 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679476808076 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679476808076 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679476808076 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1679476808076 ""}
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.sta.rdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.sta.rdb
new file mode 100644
index 0000000..a866f1f
Binary files /dev/null and b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.sta.rdb differ
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.sta_cmp.7_slow_1200mv_85c.tdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.sta_cmp.7_slow_1200mv_85c.tdb
new file mode 100644
index 0000000..0d13df0
Binary files /dev/null and b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.sta_cmp.7_slow_1200mv_85c.tdb differ
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.tis_db_list.ddb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.tis_db_list.ddb
new file mode 100644
index 0000000..73e5ec9
Binary files /dev/null and b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.tis_db_list.ddb differ
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.tiscmp.fast_1200mv_0c.ddb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.tiscmp.fast_1200mv_0c.ddb
new file mode 100644
index 0000000..f6380d2
Binary files /dev/null and b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.tiscmp.fast_1200mv_0c.ddb differ
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.tiscmp.slow_1200mv_0c.ddb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.tiscmp.slow_1200mv_0c.ddb
new file mode 100644
index 0000000..8de7c5e
Binary files /dev/null and b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.tiscmp.slow_1200mv_0c.ddb differ
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.tiscmp.slow_1200mv_85c.ddb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.tiscmp.slow_1200mv_85c.ddb
new file mode 100644
index 0000000..1f52d4f
Binary files /dev/null and b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.tiscmp.slow_1200mv_85c.ddb differ
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.tmw_info b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.tmw_info
new file mode 100644
index 0000000..def6241
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.tmw_info
@@ -0,0 +1,7 @@
+start_full_compilation:s:00:00:45
+start_analysis_synthesis:s:00:00:14-start_full_compilation
+start_analysis_elaboration:s-start_full_compilation
+start_fitter:s:00:00:18-start_full_compilation
+start_assembler:s:00:00:07-start_full_compilation
+start_timing_analyzer:s:00:00:04-start_full_compilation
+start_eda_netlist_writer:s:00:00:02-start_full_compilation
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.vpr.ammdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.vpr.ammdb
new file mode 100644
index 0000000..9e79825
Binary files /dev/null and b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.vpr.ammdb differ
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo_partition_pins.json b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo_partition_pins.json
new file mode 100644
index 0000000..0e70d74
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo_partition_pins.json
@@ -0,0 +1,81 @@
+{
+ "partitions" : [
+ {
+ "name" : "Top",
+ "pins" : [
+ {
+ "name" : "LEDR[7]",
+ "strict" : false
+ },
+ {
+ "name" : "LEDR[6]",
+ "strict" : false
+ },
+ {
+ "name" : "LEDR[5]",
+ "strict" : false
+ },
+ {
+ "name" : "LEDR[4]",
+ "strict" : false
+ },
+ {
+ "name" : "LEDR[3]",
+ "strict" : false
+ },
+ {
+ "name" : "LEDR[2]",
+ "strict" : false
+ },
+ {
+ "name" : "LEDR[1]",
+ "strict" : false
+ },
+ {
+ "name" : "LEDR[0]",
+ "strict" : false
+ },
+ {
+ "name" : "SW[7]",
+ "strict" : false
+ },
+ {
+ "name" : "KEY[0]",
+ "strict" : false
+ },
+ {
+ "name" : "SW[8]",
+ "strict" : false
+ },
+ {
+ "name" : "SW[6]",
+ "strict" : false
+ },
+ {
+ "name" : "SW[5]",
+ "strict" : false
+ },
+ {
+ "name" : "SW[4]",
+ "strict" : false
+ },
+ {
+ "name" : "SW[3]",
+ "strict" : false
+ },
+ {
+ "name" : "SW[2]",
+ "strict" : false
+ },
+ {
+ "name" : "SW[1]",
+ "strict" : false
+ },
+ {
+ "name" : "SW[0]",
+ "strict" : false
+ }
+ ]
+ }
+ ]
+}
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/db/prev_cmp_RegisterDemo.qmsg b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/prev_cmp_RegisterDemo.qmsg
new file mode 100644
index 0000000..10e047c
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica04/RegisterDemo/db/prev_cmp_RegisterDemo.qmsg
@@ -0,0 +1,4 @@
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1679476600097 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Create Symbol File Quartus Prime " "Running Quartus Prime Create Symbol File" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1679476600098 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 22 09:16:39 2023 " "Processing started: Wed Mar 22 09:16:39 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1679476600098 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Design Software" 0 -1 1679476600098 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RegisterDemo -c RegisterDemo --generate_symbol=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/Register8.vhd " "Command: quartus_map --read_settings_files=on --write_settings_files=off RegisterDemo -c RegisterDemo --generate_symbol=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/Register8.vhd" { } { } 0 0 "Command: %1!s!" 0 0 "Design Software" 0 -1 1679476600098 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Create Symbol File 0 s 0 s Quartus Prime " "Quartus Prime Create Symbol File was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "695 " "Peak virtual memory: 695 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679476601028 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 22 09:16:41 2023 " "Processing ended: Wed Mar 22 09:16:41 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679476601028 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679476601028 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679476601028 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Design Software" 0 -1 1679476601028 ""}
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/README b/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/README
new file mode 100644
index 0000000..9f62dcd
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/README
@@ -0,0 +1,11 @@
+This folder contains data for incremental compilation.
+
+The compiled_partitions sub-folder contains previous compilation results for each partition.
+As long as this folder is preserved, incremental compilation results from earlier compiles
+can be re-used. To perform a clean compilation from source files for all partitions, both
+the db and incremental_db folder should be removed.
+
+The imported_partitions sub-folder contains the last imported QXP for each imported partition.
+As long as this folder is preserved, imported partitions will be automatically re-imported
+when the db or incremental_db/compiled_partitions folders are removed.
+
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.db_info b/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.db_info
new file mode 100644
index 0000000..f364095
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.db_info
@@ -0,0 +1,3 @@
+Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+Version_Index = 520278016
+Creation_Time = Wed Mar 22 09:13:23 2023
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.cmp.ammdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.cmp.ammdb
new file mode 100644
index 0000000..b912250
Binary files /dev/null and b/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.cmp.ammdb differ
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.cmp.cdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.cmp.cdb
new file mode 100644
index 0000000..450f748
Binary files /dev/null and b/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.cmp.cdb differ
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.cmp.dfp b/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.cmp.dfp
new file mode 100644
index 0000000..b1c67d6
Binary files /dev/null and b/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.cmp.dfp differ
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.cmp.hdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.cmp.hdb
new file mode 100644
index 0000000..e43a9b2
Binary files /dev/null and b/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.cmp.hdb differ
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.cmp.logdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.cmp.logdb
new file mode 100644
index 0000000..626799f
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.cmp.logdb
@@ -0,0 +1 @@
+v1
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.cmp.rcfdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.cmp.rcfdb
new file mode 100644
index 0000000..cb0c02b
Binary files /dev/null and b/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.cmp.rcfdb differ
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.map.cdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.map.cdb
new file mode 100644
index 0000000..cc89887
Binary files /dev/null and b/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.map.cdb differ
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.map.dpi b/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.map.dpi
new file mode 100644
index 0000000..ef4ffbe
Binary files /dev/null and b/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.map.dpi differ
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.map.hbdb.cdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.map.hbdb.cdb
new file mode 100644
index 0000000..cf03cfb
Binary files /dev/null and b/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.map.hbdb.cdb differ
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.map.hbdb.hb_info b/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.map.hbdb.hb_info
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diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.map.hbdb.hdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.map.hbdb.hdb
new file mode 100644
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diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.map.hbdb.sig b/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.map.hbdb.sig
new file mode 100644
index 0000000..6c0af65
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.map.hbdb.sig
@@ -0,0 +1 @@
+c5eb7f6cdd530884c3b884e0a3668ea4
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.map.hdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.map.hdb
new file mode 100644
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diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.map.kpt b/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.map.kpt
new file mode 100644
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Binary files /dev/null and b/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.root_partition.map.kpt differ
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.rrp.hdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/incremental_db/compiled_partitions/RegisterDemo.rrp.hdb
new file mode 100644
index 0000000..107377a
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diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.asm.rpt b/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.asm.rpt
new file mode 100644
index 0000000..f18555d
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.asm.rpt
@@ -0,0 +1,92 @@
+Assembler report for RegisterDemo
+Wed Mar 22 09:20:04 2023
+Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Assembler Summary
+ 3. Assembler Settings
+ 4. Assembler Generated Files
+ 5. Assembler Device Options: RegisterDemo.sof
+ 6. Assembler Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2020 Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions
+and other software and tools, and any partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Intel Program License
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors. Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+
+
+
++---------------------------------------------------------------+
+; Assembler Summary ;
++-----------------------+---------------------------------------+
+; Assembler Status ; Successful - Wed Mar 22 09:20:04 2023 ;
+; Revision Name ; RegisterDemo ;
+; Top-level Entity Name ; RegisterDemo ;
+; Family ; Cyclone IV E ;
+; Device ; EP4CE115F29C7 ;
++-----------------------+---------------------------------------+
+
+
++----------------------------------+
+; Assembler Settings ;
++--------+---------+---------------+
+; Option ; Setting ; Default Value ;
++--------+---------+---------------+
+
+
++----------------------------------------------------------------------------------------------------------+
+; Assembler Generated Files ;
++----------------------------------------------------------------------------------------------------------+
+; File Name ;
++----------------------------------------------------------------------------------------------------------+
+; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.sof ;
++----------------------------------------------------------------------------------------------------------+
+
+
++--------------------------------------------+
+; Assembler Device Options: RegisterDemo.sof ;
++----------------+---------------------------+
+; Option ; Setting ;
++----------------+---------------------------+
+; JTAG usercode ; 0x00564A1F ;
+; Checksum ; 0x00564A1F ;
++----------------+---------------------------+
+
+
++--------------------+
+; Assembler Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Assembler
+ Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+ Info: Processing started: Wed Mar 22 09:19:58 2023
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RegisterDemo -c RegisterDemo
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (115031): Writing out detailed assembly data for power analysis
+Info (115030): Assembler is generating device programming files
+Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
+ Info: Peak virtual memory: 364 megabytes
+ Info: Processing ended: Wed Mar 22 09:20:04 2023
+ Info: Elapsed time: 00:00:06
+ Info: Total CPU time (on all processors): 00:00:05
+
+
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.done b/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.done
new file mode 100644
index 0000000..515e6e3
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.done
@@ -0,0 +1 @@
+Wed Mar 22 09:20:10 2023
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.eda.rpt b/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.eda.rpt
new file mode 100644
index 0000000..bd2eead
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.eda.rpt
@@ -0,0 +1,94 @@
+EDA Netlist Writer report for RegisterDemo
+Wed Mar 22 09:20:09 2023
+Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. EDA Netlist Writer Summary
+ 3. Simulation Settings
+ 4. Simulation Generated Files
+ 5. EDA Netlist Writer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2020 Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions
+and other software and tools, and any partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Intel Program License
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors. Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+
+
+
++-------------------------------------------------------------------+
+; EDA Netlist Writer Summary ;
++---------------------------+---------------------------------------+
+; EDA Netlist Writer Status ; Successful - Wed Mar 22 09:20:09 2023 ;
+; Revision Name ; RegisterDemo ;
+; Top-level Entity Name ; RegisterDemo ;
+; Family ; Cyclone IV E ;
+; Simulation Files Creation ; Successful ;
++---------------------------+---------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------+
+; Simulation Settings ;
++---------------------------------------------------------------------------------------------------+------------------------+
+; Option ; Setting ;
++---------------------------------------------------------------------------------------------------+------------------------+
+; Tool Name ; ModelSim-Altera (VHDL) ;
+; Generate functional simulation netlist ; On ;
+; Truncate long hierarchy paths ; Off ;
+; Map illegal HDL characters ; Off ;
+; Flatten buses into individual nodes ; Off ;
+; Maintain hierarchy ; Off ;
+; Bring out device-wide set/reset signals as ports ; Off ;
+; Enable glitch filtering ; Off ;
+; Do not write top level VHDL entity ; Off ;
+; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ;
+; Architecture name in VHDL output netlist ; structure ;
+; Generate third-party EDA tool command script for RTL functional simulation ; Off ;
+; Generate third-party EDA tool command script for gate-level simulation ; Off ;
++---------------------------------------------------------------------------------------------------+------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------+
+; Simulation Generated Files ;
++-----------------------------------------------------------------------------------------------------------------+
+; Generated Files ;
++-----------------------------------------------------------------------------------------------------------------+
+; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/modelsim/RegisterDemo.vho ;
++-----------------------------------------------------------------------------------------------------------------+
+
+
++-----------------------------+
+; EDA Netlist Writer Messages ;
++-----------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime EDA Netlist Writer
+ Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+ Info: Processing started: Wed Mar 22 09:20:09 2023
+Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off RegisterDemo -c RegisterDemo
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (204019): Generated file RegisterDemo.vho in folder "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/modelsim/" for EDA simulation tool
+Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
+ Info: Peak virtual memory: 612 megabytes
+ Info: Processing ended: Wed Mar 22 09:20:09 2023
+ Info: Elapsed time: 00:00:00
+ Info: Total CPU time (on all processors): 00:00:01
+
+
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.fit.rpt b/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.fit.rpt
new file mode 100644
index 0000000..a13caba
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.fit.rpt
@@ -0,0 +1,2606 @@
+Fitter report for RegisterDemo
+Wed Mar 22 09:19:56 2023
+Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Fitter Summary
+ 3. Fitter Settings
+ 4. Parallel Compilation
+ 5. Ignored Assignments
+ 6. Incremental Compilation Preservation Summary
+ 7. Incremental Compilation Partition Settings
+ 8. Incremental Compilation Placement Preservation
+ 9. Pin-Out File
+ 10. Fitter Resource Usage Summary
+ 11. Fitter Partition Statistics
+ 12. Input Pins
+ 13. Output Pins
+ 14. Dual Purpose and Dedicated Pins
+ 15. I/O Bank Usage
+ 16. All Package Pins
+ 17. I/O Assignment Warnings
+ 18. Fitter Resource Utilization by Entity
+ 19. Delay Chain Summary
+ 20. Pad To Core Delay Chain Fanout
+ 21. Control Signals
+ 22. Routing Usage Summary
+ 23. LAB Logic Elements
+ 24. LAB-wide Signals
+ 25. LAB Signals Sourced
+ 26. LAB Signals Sourced Out
+ 27. LAB Distinct Inputs
+ 28. I/O Rules Summary
+ 29. I/O Rules Details
+ 30. I/O Rules Matrix
+ 31. Fitter Device Options
+ 32. Operating Settings and Conditions
+ 33. Fitter Messages
+ 34. Fitter Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2020 Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions
+and other software and tools, and any partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Intel Program License
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors. Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+
+
+
++----------------------------------------------------------------------------------+
+; Fitter Summary ;
++------------------------------------+---------------------------------------------+
+; Fitter Status ; Successful - Wed Mar 22 09:19:56 2023 ;
+; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
+; Revision Name ; RegisterDemo ;
+; Top-level Entity Name ; RegisterDemo ;
+; Family ; Cyclone IV E ;
+; Device ; EP4CE115F29C7 ;
+; Timing Models ; Final ;
+; Total logic elements ; 8 / 114,480 ( < 1 % ) ;
+; Total combinational functions ; 0 / 114,480 ( 0 % ) ;
+; Dedicated logic registers ; 8 / 114,480 ( < 1 % ) ;
+; Total registers ; 8 ;
+; Total pins ; 18 / 529 ( 3 % ) ;
+; Total virtual pins ; 0 ;
+; Total memory bits ; 0 / 3,981,312 ( 0 % ) ;
+; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ;
+; Total PLLs ; 0 / 4 ( 0 % ) ;
++------------------------------------+---------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings ;
++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Option ; Setting ; Default Value ;
++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+; Device ; EP4CE115F29C7 ; ;
+; Nominal Core Supply Voltage ; 1.2V ; ;
+; Minimum Core Junction Temperature ; 0 ; ;
+; Maximum Core Junction Temperature ; 85 ; ;
+; Fit Attempts to Skip ; 0 ; 0.0 ;
+; Use smart compilation ; Off ; Off ;
+; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
+; Enable compact report table ; Off ; Off ;
+; Auto Merge PLLs ; On ; On ;
+; Router Timing Optimization Level ; Normal ; Normal ;
+; Perform Clocking Topology Analysis During Routing ; Off ; Off ;
+; Placement Effort Multiplier ; 1.0 ; 1.0 ;
+; Router Effort Multiplier ; 1.0 ; 1.0 ;
+; Optimize Hold Timing ; All Paths ; All Paths ;
+; Optimize Multi-Corner Timing ; On ; On ;
+; Power Optimization During Fitting ; Normal compilation ; Normal compilation ;
+; SSN Optimization ; Off ; Off ;
+; Optimize Timing ; Normal compilation ; Normal compilation ;
+; Optimize Timing for ECOs ; Off ; Off ;
+; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ;
+; Optimize IOC Register Placement for Timing ; Normal ; Normal ;
+; Limit to One Fitting Attempt ; Off ; Off ;
+; Final Placement Optimizations ; Automatically ; Automatically ;
+; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
+; Fitter Initial Placement Seed ; 1 ; 1 ;
+; Periphery to Core Placement and Routing Optimization ; Off ; Off ;
+; PCI I/O ; Off ; Off ;
+; Weak Pull-Up Resistor ; Off ; Off ;
+; Enable Bus-Hold Circuitry ; Off ; Off ;
+; Auto Packed Registers ; Auto ; Auto ;
+; Auto Delay Chains ; On ; On ;
+; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ;
+; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ;
+; Treat Bidirectional Pin as Output Pin ; Off ; Off ;
+; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ;
+; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
+; Perform Register Duplication for Performance ; Off ; Off ;
+; Perform Logic to Memory Mapping for Fitting ; Off ; Off ;
+; Perform Register Retiming for Performance ; Off ; Off ;
+; Perform Asynchronous Signal Pipelining ; Off ; Off ;
+; Fitter Effort ; Auto Fit ; Auto Fit ;
+; Physical Synthesis Effort Level ; Normal ; Normal ;
+; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;
+; Auto Register Duplication ; Auto ; Auto ;
+; Auto Global Clock ; On ; On ;
+; Auto Global Register Control Signals ; On ; On ;
+; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
+; Synchronizer Identification ; Auto ; Auto ;
+; Enable Beneficial Skew Optimization ; On ; On ;
+; Optimize Design for Metastability ; On ; On ;
+; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
+; Enable input tri-state on active configuration pins in user mode ; Off ; Off ;
++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation ;
++----------------------------+-------------+
+; Processors ; Number ;
++----------------------------+-------------+
+; Number detected on machine ; 8 ;
+; Maximum allowed ; 4 ;
+; ; ;
+; Average used ; 1.00 ;
+; Maximum used ; 4 ;
+; ; ;
+; Usage by Processor ; % Time Used ;
+; Processor 1 ; 100.0% ;
+; Processors 2-4 ; 0.1% ;
++----------------------------+-------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Ignored Assignments ;
++----------+----------------+--------------+------------------+---------------+----------------+
+; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ;
++----------+----------------+--------------+------------------+---------------+----------------+
+; Location ; ; ; AUD_ADCDAT ; PIN_D2 ; QSF Assignment ;
+; Location ; ; ; AUD_ADCLRCK ; PIN_C2 ; QSF Assignment ;
+; Location ; ; ; AUD_BCLK ; PIN_F2 ; QSF Assignment ;
+; Location ; ; ; AUD_DACDAT ; PIN_D1 ; QSF Assignment ;
+; Location ; ; ; AUD_DACLRCK ; PIN_E3 ; QSF Assignment ;
+; Location ; ; ; AUD_XCK ; PIN_E1 ; QSF Assignment ;
+; Location ; ; ; CLOCK2_50 ; PIN_AG14 ; QSF Assignment ;
+; Location ; ; ; CLOCK3_50 ; PIN_AG15 ; QSF Assignment ;
+; Location ; ; ; CLOCK_50 ; PIN_Y2 ; QSF Assignment ;
+; Location ; ; ; DRAM_ADDR[0] ; PIN_R6 ; QSF Assignment ;
+; Location ; ; ; DRAM_ADDR[10] ; PIN_R5 ; QSF Assignment ;
+; Location ; ; ; DRAM_ADDR[11] ; PIN_AA5 ; QSF Assignment ;
+; Location ; ; ; DRAM_ADDR[12] ; PIN_Y7 ; QSF Assignment ;
+; Location ; ; ; DRAM_ADDR[1] ; PIN_V8 ; QSF Assignment ;
+; Location ; ; ; DRAM_ADDR[2] ; PIN_U8 ; QSF Assignment ;
+; Location ; ; ; DRAM_ADDR[3] ; PIN_P1 ; QSF Assignment ;
+; Location ; ; ; DRAM_ADDR[4] ; PIN_V5 ; QSF Assignment ;
+; Location ; ; ; DRAM_ADDR[5] ; PIN_W8 ; QSF Assignment ;
+; Location ; ; ; DRAM_ADDR[6] ; PIN_W7 ; QSF Assignment ;
+; Location ; ; ; DRAM_ADDR[7] ; PIN_AA7 ; QSF Assignment ;
+; Location ; ; ; DRAM_ADDR[8] ; PIN_Y5 ; QSF Assignment ;
+; Location ; ; ; DRAM_ADDR[9] ; PIN_Y6 ; QSF Assignment ;
+; Location ; ; ; DRAM_BA[0] ; PIN_U7 ; QSF Assignment ;
+; Location ; ; ; DRAM_BA[1] ; PIN_R4 ; QSF Assignment ;
+; Location ; ; ; DRAM_CAS_N ; PIN_V7 ; QSF Assignment ;
+; Location ; ; ; DRAM_CKE ; PIN_AA6 ; QSF Assignment ;
+; Location ; ; ; DRAM_CLK ; PIN_AE5 ; QSF Assignment ;
+; Location ; ; ; DRAM_CS_N ; PIN_T4 ; QSF Assignment ;
+; Location ; ; ; DRAM_DQM[0] ; PIN_U2 ; QSF Assignment ;
+; Location ; ; ; DRAM_DQM[1] ; PIN_W4 ; QSF Assignment ;
+; Location ; ; ; DRAM_DQM[2] ; PIN_K8 ; QSF Assignment ;
+; Location ; ; ; DRAM_DQM[3] ; PIN_N8 ; QSF Assignment ;
+; Location ; ; ; DRAM_DQ[0] ; PIN_W3 ; QSF Assignment ;
+; Location ; ; ; DRAM_DQ[10] ; PIN_AB1 ; QSF Assignment ;
+; Location ; ; ; DRAM_DQ[11] ; PIN_AA3 ; QSF Assignment ;
+; Location ; ; ; DRAM_DQ[12] ; PIN_AB2 ; QSF Assignment ;
+; Location ; ; ; DRAM_DQ[13] ; PIN_AC1 ; QSF Assignment ;
+; Location ; ; ; DRAM_DQ[14] ; PIN_AB3 ; QSF Assignment ;
+; Location ; ; ; DRAM_DQ[15] ; PIN_AC2 ; QSF Assignment ;
+; Location ; ; ; DRAM_DQ[16] ; PIN_M8 ; QSF Assignment ;
+; Location ; ; ; DRAM_DQ[17] ; PIN_L8 ; QSF Assignment ;
+; Location ; ; ; DRAM_DQ[18] ; PIN_P2 ; QSF Assignment ;
+; Location ; ; ; DRAM_DQ[19] ; PIN_N3 ; QSF Assignment ;
+; Location ; ; ; DRAM_DQ[1] ; PIN_W2 ; QSF Assignment ;
+; Location ; ; ; DRAM_DQ[20] ; PIN_N4 ; QSF Assignment ;
+; Location ; ; ; DRAM_DQ[21] ; PIN_M4 ; QSF Assignment ;
+; Location ; ; ; DRAM_DQ[22] ; PIN_M7 ; QSF Assignment ;
+; Location ; ; ; DRAM_DQ[23] ; PIN_L7 ; QSF Assignment ;
+; Location ; ; ; DRAM_DQ[24] ; PIN_U5 ; QSF Assignment ;
+; Location ; ; ; DRAM_DQ[25] ; PIN_R7 ; QSF Assignment ;
+; Location ; ; ; DRAM_DQ[26] ; PIN_R1 ; QSF Assignment ;
+; Location ; ; ; DRAM_DQ[27] ; PIN_R2 ; QSF Assignment ;
+; Location ; ; ; DRAM_DQ[28] ; PIN_R3 ; QSF Assignment ;
+; Location ; ; ; DRAM_DQ[29] ; PIN_T3 ; QSF Assignment ;
+; Location ; ; ; DRAM_DQ[2] ; PIN_V4 ; QSF Assignment ;
+; Location ; ; ; DRAM_DQ[30] ; PIN_U4 ; QSF Assignment ;
+; Location ; ; ; DRAM_DQ[31] ; PIN_U1 ; QSF Assignment ;
+; Location ; ; ; DRAM_DQ[3] ; PIN_W1 ; QSF Assignment ;
+; Location ; ; ; DRAM_DQ[4] ; PIN_V3 ; QSF Assignment ;
+; Location ; ; ; DRAM_DQ[5] ; PIN_V2 ; QSF Assignment ;
+; Location ; ; ; DRAM_DQ[6] ; PIN_V1 ; QSF Assignment ;
+; Location ; ; ; DRAM_DQ[7] ; PIN_U3 ; QSF Assignment ;
+; Location ; ; ; DRAM_DQ[8] ; PIN_Y3 ; QSF Assignment ;
+; Location ; ; ; DRAM_DQ[9] ; PIN_Y4 ; QSF Assignment ;
+; Location ; ; ; DRAM_RAS_N ; PIN_U6 ; QSF Assignment ;
+; Location ; ; ; DRAM_WE_N ; PIN_V6 ; QSF Assignment ;
+; Location ; ; ; EEP_I2C_SCLK ; PIN_D14 ; QSF Assignment ;
+; Location ; ; ; EEP_I2C_SDAT ; PIN_E14 ; QSF Assignment ;
+; Location ; ; ; ENET0_GTX_CLK ; PIN_A17 ; QSF Assignment ;
+; Location ; ; ; ENET0_INT_N ; PIN_A21 ; QSF Assignment ;
+; Location ; ; ; ENET0_LINK100 ; PIN_C14 ; QSF Assignment ;
+; Location ; ; ; ENET0_MDC ; PIN_C20 ; QSF Assignment ;
+; Location ; ; ; ENET0_MDIO ; PIN_B21 ; QSF Assignment ;
+; Location ; ; ; ENET0_RST_N ; PIN_C19 ; QSF Assignment ;
+; Location ; ; ; ENET0_RX_CLK ; PIN_A15 ; QSF Assignment ;
+; Location ; ; ; ENET0_RX_COL ; PIN_E15 ; QSF Assignment ;
+; Location ; ; ; ENET0_RX_CRS ; PIN_D15 ; QSF Assignment ;
+; Location ; ; ; ENET0_RX_DATA[0] ; PIN_C16 ; QSF Assignment ;
+; Location ; ; ; ENET0_RX_DATA[1] ; PIN_D16 ; QSF Assignment ;
+; Location ; ; ; ENET0_RX_DATA[2] ; PIN_D17 ; QSF Assignment ;
+; Location ; ; ; ENET0_RX_DATA[3] ; PIN_C15 ; QSF Assignment ;
+; Location ; ; ; ENET0_RX_DV ; PIN_C17 ; QSF Assignment ;
+; Location ; ; ; ENET0_RX_ER ; PIN_D18 ; QSF Assignment ;
+; Location ; ; ; ENET0_TX_CLK ; PIN_B17 ; QSF Assignment ;
+; Location ; ; ; ENET0_TX_DATA[0] ; PIN_C18 ; QSF Assignment ;
+; Location ; ; ; ENET0_TX_DATA[1] ; PIN_D19 ; QSF Assignment ;
+; Location ; ; ; ENET0_TX_DATA[2] ; PIN_A19 ; QSF Assignment ;
+; Location ; ; ; ENET0_TX_DATA[3] ; PIN_B19 ; QSF Assignment ;
+; Location ; ; ; ENET0_TX_EN ; PIN_A18 ; QSF Assignment ;
+; Location ; ; ; ENET0_TX_ER ; PIN_B18 ; QSF Assignment ;
+; Location ; ; ; ENET1_GTX_CLK ; PIN_C23 ; QSF Assignment ;
+; Location ; ; ; ENET1_INT_N ; PIN_D24 ; QSF Assignment ;
+; Location ; ; ; ENET1_LINK100 ; PIN_D13 ; QSF Assignment ;
+; Location ; ; ; ENET1_MDC ; PIN_D23 ; QSF Assignment ;
+; Location ; ; ; ENET1_MDIO ; PIN_D25 ; QSF Assignment ;
+; Location ; ; ; ENET1_RST_N ; PIN_D22 ; QSF Assignment ;
+; Location ; ; ; ENET1_RX_CLK ; PIN_B15 ; QSF Assignment ;
+; Location ; ; ; ENET1_RX_COL ; PIN_B22 ; QSF Assignment ;
+; Location ; ; ; ENET1_RX_CRS ; PIN_D20 ; QSF Assignment ;
+; Location ; ; ; ENET1_RX_DATA[0] ; PIN_B23 ; QSF Assignment ;
+; Location ; ; ; ENET1_RX_DATA[1] ; PIN_C21 ; QSF Assignment ;
+; Location ; ; ; ENET1_RX_DATA[2] ; PIN_A23 ; QSF Assignment ;
+; Location ; ; ; ENET1_RX_DATA[3] ; PIN_D21 ; QSF Assignment ;
+; Location ; ; ; ENET1_RX_DV ; PIN_A22 ; QSF Assignment ;
+; Location ; ; ; ENET1_RX_ER ; PIN_C24 ; QSF Assignment ;
+; Location ; ; ; ENET1_TX_CLK ; PIN_C22 ; QSF Assignment ;
+; Location ; ; ; ENET1_TX_DATA[0] ; PIN_C25 ; QSF Assignment ;
+; Location ; ; ; ENET1_TX_DATA[1] ; PIN_A26 ; QSF Assignment ;
+; Location ; ; ; ENET1_TX_DATA[2] ; PIN_B26 ; QSF Assignment ;
+; Location ; ; ; ENET1_TX_DATA[3] ; PIN_C26 ; QSF Assignment ;
+; Location ; ; ; ENET1_TX_EN ; PIN_B25 ; QSF Assignment ;
+; Location ; ; ; ENET1_TX_ER ; PIN_A25 ; QSF Assignment ;
+; Location ; ; ; ENETCLK_25 ; PIN_A14 ; QSF Assignment ;
+; Location ; ; ; EX_IO[0] ; PIN_J10 ; QSF Assignment ;
+; Location ; ; ; EX_IO[1] ; PIN_J14 ; QSF Assignment ;
+; Location ; ; ; EX_IO[2] ; PIN_H13 ; QSF Assignment ;
+; Location ; ; ; EX_IO[3] ; PIN_H14 ; QSF Assignment ;
+; Location ; ; ; EX_IO[4] ; PIN_F14 ; QSF Assignment ;
+; Location ; ; ; EX_IO[5] ; PIN_E10 ; QSF Assignment ;
+; Location ; ; ; EX_IO[6] ; PIN_D9 ; QSF Assignment ;
+; Location ; ; ; FL_ADDR[0] ; PIN_AG12 ; QSF Assignment ;
+; Location ; ; ; FL_ADDR[10] ; PIN_AE9 ; QSF Assignment ;
+; Location ; ; ; FL_ADDR[11] ; PIN_AF9 ; QSF Assignment ;
+; Location ; ; ; FL_ADDR[12] ; PIN_AA10 ; QSF Assignment ;
+; Location ; ; ; FL_ADDR[13] ; PIN_AD8 ; QSF Assignment ;
+; Location ; ; ; FL_ADDR[14] ; PIN_AC8 ; QSF Assignment ;
+; Location ; ; ; FL_ADDR[15] ; PIN_Y10 ; QSF Assignment ;
+; Location ; ; ; FL_ADDR[16] ; PIN_AA8 ; QSF Assignment ;
+; Location ; ; ; FL_ADDR[17] ; PIN_AH12 ; QSF Assignment ;
+; Location ; ; ; FL_ADDR[18] ; PIN_AC12 ; QSF Assignment ;
+; Location ; ; ; FL_ADDR[19] ; PIN_AD12 ; QSF Assignment ;
+; Location ; ; ; FL_ADDR[1] ; PIN_AH7 ; QSF Assignment ;
+; Location ; ; ; FL_ADDR[20] ; PIN_AE10 ; QSF Assignment ;
+; Location ; ; ; FL_ADDR[21] ; PIN_AD10 ; QSF Assignment ;
+; Location ; ; ; FL_ADDR[22] ; PIN_AD11 ; QSF Assignment ;
+; Location ; ; ; FL_ADDR[2] ; PIN_Y13 ; QSF Assignment ;
+; Location ; ; ; FL_ADDR[3] ; PIN_Y14 ; QSF Assignment ;
+; Location ; ; ; FL_ADDR[4] ; PIN_Y12 ; QSF Assignment ;
+; Location ; ; ; FL_ADDR[5] ; PIN_AA13 ; QSF Assignment ;
+; Location ; ; ; FL_ADDR[6] ; PIN_AA12 ; QSF Assignment ;
+; Location ; ; ; FL_ADDR[7] ; PIN_AB13 ; QSF Assignment ;
+; Location ; ; ; FL_ADDR[8] ; PIN_AB12 ; QSF Assignment ;
+; Location ; ; ; FL_ADDR[9] ; PIN_AB10 ; QSF Assignment ;
+; Location ; ; ; FL_CE_N ; PIN_AG7 ; QSF Assignment ;
+; Location ; ; ; FL_DQ[0] ; PIN_AH8 ; QSF Assignment ;
+; Location ; ; ; FL_DQ[1] ; PIN_AF10 ; QSF Assignment ;
+; Location ; ; ; FL_DQ[2] ; PIN_AG10 ; QSF Assignment ;
+; Location ; ; ; FL_DQ[3] ; PIN_AH10 ; QSF Assignment ;
+; Location ; ; ; FL_DQ[4] ; PIN_AF11 ; QSF Assignment ;
+; Location ; ; ; FL_DQ[5] ; PIN_AG11 ; QSF Assignment ;
+; Location ; ; ; FL_DQ[6] ; PIN_AH11 ; QSF Assignment ;
+; Location ; ; ; FL_DQ[7] ; PIN_AF12 ; QSF Assignment ;
+; Location ; ; ; FL_OE_N ; PIN_AG8 ; QSF Assignment ;
+; Location ; ; ; FL_RST_N ; PIN_AE11 ; QSF Assignment ;
+; Location ; ; ; FL_RY ; PIN_Y1 ; QSF Assignment ;
+; Location ; ; ; FL_WE_N ; PIN_AC10 ; QSF Assignment ;
+; Location ; ; ; FL_WP_N ; PIN_AE12 ; QSF Assignment ;
+; Location ; ; ; GPIO[0] ; PIN_AB22 ; QSF Assignment ;
+; Location ; ; ; GPIO[10] ; PIN_AC19 ; QSF Assignment ;
+; Location ; ; ; GPIO[11] ; PIN_AF16 ; QSF Assignment ;
+; Location ; ; ; GPIO[12] ; PIN_AD19 ; QSF Assignment ;
+; Location ; ; ; GPIO[13] ; PIN_AF15 ; QSF Assignment ;
+; Location ; ; ; GPIO[14] ; PIN_AF24 ; QSF Assignment ;
+; Location ; ; ; GPIO[15] ; PIN_AE21 ; QSF Assignment ;
+; Location ; ; ; GPIO[16] ; PIN_AF25 ; QSF Assignment ;
+; Location ; ; ; GPIO[17] ; PIN_AC22 ; QSF Assignment ;
+; Location ; ; ; GPIO[18] ; PIN_AE22 ; QSF Assignment ;
+; Location ; ; ; GPIO[19] ; PIN_AF21 ; QSF Assignment ;
+; Location ; ; ; GPIO[1] ; PIN_AC15 ; QSF Assignment ;
+; Location ; ; ; GPIO[20] ; PIN_AF22 ; QSF Assignment ;
+; Location ; ; ; GPIO[21] ; PIN_AD22 ; QSF Assignment ;
+; Location ; ; ; GPIO[22] ; PIN_AG25 ; QSF Assignment ;
+; Location ; ; ; GPIO[23] ; PIN_AD25 ; QSF Assignment ;
+; Location ; ; ; GPIO[24] ; PIN_AH25 ; QSF Assignment ;
+; Location ; ; ; GPIO[25] ; PIN_AE25 ; QSF Assignment ;
+; Location ; ; ; GPIO[26] ; PIN_AG22 ; QSF Assignment ;
+; Location ; ; ; GPIO[27] ; PIN_AE24 ; QSF Assignment ;
+; Location ; ; ; GPIO[28] ; PIN_AH22 ; QSF Assignment ;
+; Location ; ; ; GPIO[29] ; PIN_AF26 ; QSF Assignment ;
+; Location ; ; ; GPIO[2] ; PIN_AB21 ; QSF Assignment ;
+; Location ; ; ; GPIO[30] ; PIN_AE20 ; QSF Assignment ;
+; Location ; ; ; GPIO[31] ; PIN_AG23 ; QSF Assignment ;
+; Location ; ; ; GPIO[32] ; PIN_AF20 ; QSF Assignment ;
+; Location ; ; ; GPIO[33] ; PIN_AH26 ; QSF Assignment ;
+; Location ; ; ; GPIO[34] ; PIN_AH23 ; QSF Assignment ;
+; Location ; ; ; GPIO[35] ; PIN_AG26 ; QSF Assignment ;
+; Location ; ; ; GPIO[3] ; PIN_Y17 ; QSF Assignment ;
+; Location ; ; ; GPIO[4] ; PIN_AC21 ; QSF Assignment ;
+; Location ; ; ; GPIO[5] ; PIN_Y16 ; QSF Assignment ;
+; Location ; ; ; GPIO[6] ; PIN_AD21 ; QSF Assignment ;
+; Location ; ; ; GPIO[7] ; PIN_AE16 ; QSF Assignment ;
+; Location ; ; ; GPIO[8] ; PIN_AD15 ; QSF Assignment ;
+; Location ; ; ; GPIO[9] ; PIN_AE15 ; QSF Assignment ;
+; Location ; ; ; HEX0[0] ; PIN_G18 ; QSF Assignment ;
+; Location ; ; ; HEX0[1] ; PIN_F22 ; QSF Assignment ;
+; Location ; ; ; HEX0[2] ; PIN_E17 ; QSF Assignment ;
+; Location ; ; ; HEX0[3] ; PIN_L26 ; QSF Assignment ;
+; Location ; ; ; HEX0[4] ; PIN_L25 ; QSF Assignment ;
+; Location ; ; ; HEX0[5] ; PIN_J22 ; QSF Assignment ;
+; Location ; ; ; HEX0[6] ; PIN_H22 ; QSF Assignment ;
+; Location ; ; ; HEX1[0] ; PIN_M24 ; QSF Assignment ;
+; Location ; ; ; HEX1[1] ; PIN_Y22 ; QSF Assignment ;
+; Location ; ; ; HEX1[2] ; PIN_W21 ; QSF Assignment ;
+; Location ; ; ; HEX1[3] ; PIN_W22 ; QSF Assignment ;
+; Location ; ; ; HEX1[4] ; PIN_W25 ; QSF Assignment ;
+; Location ; ; ; HEX1[5] ; PIN_U23 ; QSF Assignment ;
+; Location ; ; ; HEX1[6] ; PIN_U24 ; QSF Assignment ;
+; Location ; ; ; HEX2[0] ; PIN_AA25 ; QSF Assignment ;
+; Location ; ; ; HEX2[1] ; PIN_AA26 ; QSF Assignment ;
+; Location ; ; ; HEX2[2] ; PIN_Y25 ; QSF Assignment ;
+; Location ; ; ; HEX2[3] ; PIN_W26 ; QSF Assignment ;
+; Location ; ; ; HEX2[4] ; PIN_Y26 ; QSF Assignment ;
+; Location ; ; ; HEX2[5] ; PIN_W27 ; QSF Assignment ;
+; Location ; ; ; HEX2[6] ; PIN_W28 ; QSF Assignment ;
+; Location ; ; ; HEX3[0] ; PIN_V21 ; QSF Assignment ;
+; Location ; ; ; HEX3[1] ; PIN_U21 ; QSF Assignment ;
+; Location ; ; ; HEX3[2] ; PIN_AB20 ; QSF Assignment ;
+; Location ; ; ; HEX3[3] ; PIN_AA21 ; QSF Assignment ;
+; Location ; ; ; HEX3[4] ; PIN_AD24 ; QSF Assignment ;
+; Location ; ; ; HEX3[5] ; PIN_AF23 ; QSF Assignment ;
+; Location ; ; ; HEX3[6] ; PIN_Y19 ; QSF Assignment ;
+; Location ; ; ; HEX4[0] ; PIN_AB19 ; QSF Assignment ;
+; Location ; ; ; HEX4[1] ; PIN_AA19 ; QSF Assignment ;
+; Location ; ; ; HEX4[2] ; PIN_AG21 ; QSF Assignment ;
+; Location ; ; ; HEX4[3] ; PIN_AH21 ; QSF Assignment ;
+; Location ; ; ; HEX4[4] ; PIN_AE19 ; QSF Assignment ;
+; Location ; ; ; HEX4[5] ; PIN_AF19 ; QSF Assignment ;
+; Location ; ; ; HEX4[6] ; PIN_AE18 ; QSF Assignment ;
+; Location ; ; ; HEX5[0] ; PIN_AD18 ; QSF Assignment ;
+; Location ; ; ; HEX5[1] ; PIN_AC18 ; QSF Assignment ;
+; Location ; ; ; HEX5[2] ; PIN_AB18 ; QSF Assignment ;
+; Location ; ; ; HEX5[3] ; PIN_AH19 ; QSF Assignment ;
+; Location ; ; ; HEX5[4] ; PIN_AG19 ; QSF Assignment ;
+; Location ; ; ; HEX5[5] ; PIN_AF18 ; QSF Assignment ;
+; Location ; ; ; HEX5[6] ; PIN_AH18 ; QSF Assignment ;
+; Location ; ; ; HEX6[0] ; PIN_AA17 ; QSF Assignment ;
+; Location ; ; ; HEX6[1] ; PIN_AB16 ; QSF Assignment ;
+; Location ; ; ; HEX6[2] ; PIN_AA16 ; QSF Assignment ;
+; Location ; ; ; HEX6[3] ; PIN_AB17 ; QSF Assignment ;
+; Location ; ; ; HEX6[4] ; PIN_AB15 ; QSF Assignment ;
+; Location ; ; ; HEX6[5] ; PIN_AA15 ; QSF Assignment ;
+; Location ; ; ; HEX6[6] ; PIN_AC17 ; QSF Assignment ;
+; Location ; ; ; HEX7[0] ; PIN_AD17 ; QSF Assignment ;
+; Location ; ; ; HEX7[1] ; PIN_AE17 ; QSF Assignment ;
+; Location ; ; ; HEX7[2] ; PIN_AG17 ; QSF Assignment ;
+; Location ; ; ; HEX7[3] ; PIN_AH17 ; QSF Assignment ;
+; Location ; ; ; HEX7[4] ; PIN_AF17 ; QSF Assignment ;
+; Location ; ; ; HEX7[5] ; PIN_AG18 ; QSF Assignment ;
+; Location ; ; ; HEX7[6] ; PIN_AA14 ; QSF Assignment ;
+; Location ; ; ; HSMC_CLKIN0 ; PIN_AH15 ; QSF Assignment ;
+; Location ; ; ; HSMC_CLKIN_N1 ; PIN_J28 ; QSF Assignment ;
+; Location ; ; ; HSMC_CLKIN_N2 ; PIN_Y28 ; QSF Assignment ;
+; Location ; ; ; HSMC_CLKIN_P1 ; PIN_J27 ; QSF Assignment ;
+; Location ; ; ; HSMC_CLKIN_P2 ; PIN_Y27 ; QSF Assignment ;
+; Location ; ; ; HSMC_CLKOUT0 ; PIN_AD28 ; QSF Assignment ;
+; Location ; ; ; HSMC_CLKOUT_N1 ; PIN_G24 ; QSF Assignment ;
+; Location ; ; ; HSMC_CLKOUT_N2 ; PIN_V24 ; QSF Assignment ;
+; Location ; ; ; HSMC_CLKOUT_P1 ; PIN_G23 ; QSF Assignment ;
+; Location ; ; ; HSMC_CLKOUT_P2 ; PIN_V23 ; QSF Assignment ;
+; Location ; ; ; HSMC_D[0] ; PIN_AE26 ; QSF Assignment ;
+; Location ; ; ; HSMC_D[1] ; PIN_AE28 ; QSF Assignment ;
+; Location ; ; ; HSMC_D[2] ; PIN_AE27 ; QSF Assignment ;
+; Location ; ; ; HSMC_D[3] ; PIN_AF27 ; QSF Assignment ;
+; Location ; ; ; HSMC_RX_D_N[0] ; PIN_F25 ; QSF Assignment ;
+; Location ; ; ; HSMC_RX_D_N[10] ; PIN_U26 ; QSF Assignment ;
+; Location ; ; ; HSMC_RX_D_N[11] ; PIN_L22 ; QSF Assignment ;
+; Location ; ; ; HSMC_RX_D_N[12] ; PIN_N26 ; QSF Assignment ;
+; Location ; ; ; HSMC_RX_D_N[13] ; PIN_P26 ; QSF Assignment ;
+; Location ; ; ; HSMC_RX_D_N[14] ; PIN_R21 ; QSF Assignment ;
+; Location ; ; ; HSMC_RX_D_N[15] ; PIN_R23 ; QSF Assignment ;
+; Location ; ; ; HSMC_RX_D_N[16] ; PIN_T22 ; QSF Assignment ;
+; Location ; ; ; HSMC_RX_D_N[1] ; PIN_C27 ; QSF Assignment ;
+; Location ; ; ; HSMC_RX_D_N[2] ; PIN_E26 ; QSF Assignment ;
+; Location ; ; ; HSMC_RX_D_N[3] ; PIN_G26 ; QSF Assignment ;
+; Location ; ; ; HSMC_RX_D_N[4] ; PIN_H26 ; QSF Assignment ;
+; Location ; ; ; HSMC_RX_D_N[5] ; PIN_K26 ; QSF Assignment ;
+; Location ; ; ; HSMC_RX_D_N[6] ; PIN_L24 ; QSF Assignment ;
+; Location ; ; ; HSMC_RX_D_N[7] ; PIN_M26 ; QSF Assignment ;
+; Location ; ; ; HSMC_RX_D_N[8] ; PIN_R26 ; QSF Assignment ;
+; Location ; ; ; HSMC_RX_D_N[9] ; PIN_T26 ; QSF Assignment ;
+; Location ; ; ; HSMC_RX_D_P[0] ; PIN_F24 ; QSF Assignment ;
+; Location ; ; ; HSMC_RX_D_P[10] ; PIN_U25 ; QSF Assignment ;
+; Location ; ; ; HSMC_RX_D_P[11] ; PIN_L21 ; QSF Assignment ;
+; Location ; ; ; HSMC_RX_D_P[12] ; PIN_N25 ; QSF Assignment ;
+; Location ; ; ; HSMC_RX_D_P[13] ; PIN_P25 ; QSF Assignment ;
+; Location ; ; ; HSMC_RX_D_P[14] ; PIN_P21 ; QSF Assignment ;
+; Location ; ; ; HSMC_RX_D_P[15] ; PIN_R22 ; QSF Assignment ;
+; Location ; ; ; HSMC_RX_D_P[16] ; PIN_T21 ; QSF Assignment ;
+; Location ; ; ; HSMC_RX_D_P[1] ; PIN_D26 ; QSF Assignment ;
+; Location ; ; ; HSMC_RX_D_P[2] ; PIN_F26 ; QSF Assignment ;
+; Location ; ; ; HSMC_RX_D_P[3] ; PIN_G25 ; QSF Assignment ;
+; Location ; ; ; HSMC_RX_D_P[4] ; PIN_H25 ; QSF Assignment ;
+; Location ; ; ; HSMC_RX_D_P[5] ; PIN_K25 ; QSF Assignment ;
+; Location ; ; ; HSMC_RX_D_P[6] ; PIN_L23 ; QSF Assignment ;
+; Location ; ; ; HSMC_RX_D_P[7] ; PIN_M25 ; QSF Assignment ;
+; Location ; ; ; HSMC_RX_D_P[8] ; PIN_R25 ; QSF Assignment ;
+; Location ; ; ; HSMC_RX_D_P[9] ; PIN_T25 ; QSF Assignment ;
+; Location ; ; ; HSMC_TX_D_N[0] ; PIN_D28 ; QSF Assignment ;
+; Location ; ; ; HSMC_TX_D_N[10] ; PIN_J26 ; QSF Assignment ;
+; Location ; ; ; HSMC_TX_D_N[11] ; PIN_L28 ; QSF Assignment ;
+; Location ; ; ; HSMC_TX_D_N[12] ; PIN_V26 ; QSF Assignment ;
+; Location ; ; ; HSMC_TX_D_N[13] ; PIN_R28 ; QSF Assignment ;
+; Location ; ; ; HSMC_TX_D_N[14] ; PIN_U28 ; QSF Assignment ;
+; Location ; ; ; HSMC_TX_D_N[15] ; PIN_V28 ; QSF Assignment ;
+; Location ; ; ; HSMC_TX_D_N[16] ; PIN_V22 ; QSF Assignment ;
+; Location ; ; ; HSMC_TX_D_N[1] ; PIN_E28 ; QSF Assignment ;
+; Location ; ; ; HSMC_TX_D_N[2] ; PIN_F28 ; QSF Assignment ;
+; Location ; ; ; HSMC_TX_D_N[3] ; PIN_G28 ; QSF Assignment ;
+; Location ; ; ; HSMC_TX_D_N[4] ; PIN_K28 ; QSF Assignment ;
+; Location ; ; ; HSMC_TX_D_N[5] ; PIN_M28 ; QSF Assignment ;
+; Location ; ; ; HSMC_TX_D_N[6] ; PIN_K22 ; QSF Assignment ;
+; Location ; ; ; HSMC_TX_D_N[7] ; PIN_H24 ; QSF Assignment ;
+; Location ; ; ; HSMC_TX_D_N[8] ; PIN_J24 ; QSF Assignment ;
+; Location ; ; ; HSMC_TX_D_N[9] ; PIN_P28 ; QSF Assignment ;
+; Location ; ; ; HSMC_TX_D_P[0] ; PIN_D27 ; QSF Assignment ;
+; Location ; ; ; HSMC_TX_D_P[10] ; PIN_J25 ; QSF Assignment ;
+; Location ; ; ; HSMC_TX_D_P[11] ; PIN_L27 ; QSF Assignment ;
+; Location ; ; ; HSMC_TX_D_P[12] ; PIN_V25 ; QSF Assignment ;
+; Location ; ; ; HSMC_TX_D_P[13] ; PIN_R27 ; QSF Assignment ;
+; Location ; ; ; HSMC_TX_D_P[14] ; PIN_U27 ; QSF Assignment ;
+; Location ; ; ; HSMC_TX_D_P[15] ; PIN_V27 ; QSF Assignment ;
+; Location ; ; ; HSMC_TX_D_P[16] ; PIN_U22 ; QSF Assignment ;
+; Location ; ; ; HSMC_TX_D_P[1] ; PIN_E27 ; QSF Assignment ;
+; Location ; ; ; HSMC_TX_D_P[2] ; PIN_F27 ; QSF Assignment ;
+; Location ; ; ; HSMC_TX_D_P[3] ; PIN_G27 ; QSF Assignment ;
+; Location ; ; ; HSMC_TX_D_P[4] ; PIN_K27 ; QSF Assignment ;
+; Location ; ; ; HSMC_TX_D_P[5] ; PIN_M27 ; QSF Assignment ;
+; Location ; ; ; HSMC_TX_D_P[6] ; PIN_K21 ; QSF Assignment ;
+; Location ; ; ; HSMC_TX_D_P[7] ; PIN_H23 ; QSF Assignment ;
+; Location ; ; ; HSMC_TX_D_P[8] ; PIN_J23 ; QSF Assignment ;
+; Location ; ; ; HSMC_TX_D_P[9] ; PIN_P27 ; QSF Assignment ;
+; Location ; ; ; I2C_SCLK ; PIN_B7 ; QSF Assignment ;
+; Location ; ; ; I2C_SDAT ; PIN_A8 ; QSF Assignment ;
+; Location ; ; ; IRDA_RXD ; PIN_Y15 ; QSF Assignment ;
+; Location ; ; ; KEY[1] ; PIN_M21 ; QSF Assignment ;
+; Location ; ; ; KEY[2] ; PIN_N21 ; QSF Assignment ;
+; Location ; ; ; KEY[3] ; PIN_R24 ; QSF Assignment ;
+; Location ; ; ; LCD_BLON ; PIN_L6 ; QSF Assignment ;
+; Location ; ; ; LCD_DATA[0] ; PIN_L3 ; QSF Assignment ;
+; Location ; ; ; LCD_DATA[1] ; PIN_L1 ; QSF Assignment ;
+; Location ; ; ; LCD_DATA[2] ; PIN_L2 ; QSF Assignment ;
+; Location ; ; ; LCD_DATA[3] ; PIN_K7 ; QSF Assignment ;
+; Location ; ; ; LCD_DATA[4] ; PIN_K1 ; QSF Assignment ;
+; Location ; ; ; LCD_DATA[5] ; PIN_K2 ; QSF Assignment ;
+; Location ; ; ; LCD_DATA[6] ; PIN_M3 ; QSF Assignment ;
+; Location ; ; ; LCD_DATA[7] ; PIN_M5 ; QSF Assignment ;
+; Location ; ; ; LCD_EN ; PIN_L4 ; QSF Assignment ;
+; Location ; ; ; LCD_ON ; PIN_L5 ; QSF Assignment ;
+; Location ; ; ; LCD_RS ; PIN_M2 ; QSF Assignment ;
+; Location ; ; ; LCD_RW ; PIN_M1 ; QSF Assignment ;
+; Location ; ; ; LEDG[0] ; PIN_E21 ; QSF Assignment ;
+; Location ; ; ; LEDG[1] ; PIN_E22 ; QSF Assignment ;
+; Location ; ; ; LEDG[2] ; PIN_E25 ; QSF Assignment ;
+; Location ; ; ; LEDG[3] ; PIN_E24 ; QSF Assignment ;
+; Location ; ; ; LEDG[4] ; PIN_H21 ; QSF Assignment ;
+; Location ; ; ; LEDG[5] ; PIN_G20 ; QSF Assignment ;
+; Location ; ; ; LEDG[6] ; PIN_G22 ; QSF Assignment ;
+; Location ; ; ; LEDG[7] ; PIN_G21 ; QSF Assignment ;
+; Location ; ; ; LEDG[8] ; PIN_F17 ; QSF Assignment ;
+; Location ; ; ; LEDR[10] ; PIN_J15 ; QSF Assignment ;
+; Location ; ; ; LEDR[11] ; PIN_H16 ; QSF Assignment ;
+; Location ; ; ; LEDR[12] ; PIN_J16 ; QSF Assignment ;
+; Location ; ; ; LEDR[13] ; PIN_H17 ; QSF Assignment ;
+; Location ; ; ; LEDR[14] ; PIN_F15 ; QSF Assignment ;
+; Location ; ; ; LEDR[15] ; PIN_G15 ; QSF Assignment ;
+; Location ; ; ; LEDR[16] ; PIN_G16 ; QSF Assignment ;
+; Location ; ; ; LEDR[17] ; PIN_H15 ; QSF Assignment ;
+; Location ; ; ; LEDR[8] ; PIN_J17 ; QSF Assignment ;
+; Location ; ; ; LEDR[9] ; PIN_G17 ; QSF Assignment ;
+; Location ; ; ; OTG_ADDR[0] ; PIN_H7 ; QSF Assignment ;
+; Location ; ; ; OTG_ADDR[1] ; PIN_C3 ; QSF Assignment ;
+; Location ; ; ; OTG_CS_N ; PIN_A3 ; QSF Assignment ;
+; Location ; ; ; OTG_DATA[0] ; PIN_J6 ; QSF Assignment ;
+; Location ; ; ; OTG_DATA[10] ; PIN_G1 ; QSF Assignment ;
+; Location ; ; ; OTG_DATA[11] ; PIN_G2 ; QSF Assignment ;
+; Location ; ; ; OTG_DATA[12] ; PIN_G3 ; QSF Assignment ;
+; Location ; ; ; OTG_DATA[13] ; PIN_F1 ; QSF Assignment ;
+; Location ; ; ; OTG_DATA[14] ; PIN_F3 ; QSF Assignment ;
+; Location ; ; ; OTG_DATA[15] ; PIN_G4 ; QSF Assignment ;
+; Location ; ; ; OTG_DATA[1] ; PIN_K4 ; QSF Assignment ;
+; Location ; ; ; OTG_DATA[2] ; PIN_J5 ; QSF Assignment ;
+; Location ; ; ; OTG_DATA[3] ; PIN_K3 ; QSF Assignment ;
+; Location ; ; ; OTG_DATA[4] ; PIN_J4 ; QSF Assignment ;
+; Location ; ; ; OTG_DATA[5] ; PIN_J3 ; QSF Assignment ;
+; Location ; ; ; OTG_DATA[6] ; PIN_J7 ; QSF Assignment ;
+; Location ; ; ; OTG_DATA[7] ; PIN_H6 ; QSF Assignment ;
+; Location ; ; ; OTG_DATA[8] ; PIN_H3 ; QSF Assignment ;
+; Location ; ; ; OTG_DATA[9] ; PIN_H4 ; QSF Assignment ;
+; Location ; ; ; OTG_DREQ[0] ; PIN_J1 ; QSF Assignment ;
+; Location ; ; ; OTG_INT ; PIN_D5 ; QSF Assignment ;
+; Location ; ; ; OTG_RD_N ; PIN_B3 ; QSF Assignment ;
+; Location ; ; ; OTG_RST_N ; PIN_C5 ; QSF Assignment ;
+; Location ; ; ; OTG_WR_N ; PIN_A4 ; QSF Assignment ;
+; Location ; ; ; PS2_CLK ; PIN_G6 ; QSF Assignment ;
+; Location ; ; ; PS2_CLK2 ; PIN_G5 ; QSF Assignment ;
+; Location ; ; ; PS2_DAT ; PIN_H5 ; QSF Assignment ;
+; Location ; ; ; PS2_DAT2 ; PIN_F5 ; QSF Assignment ;
+; Location ; ; ; SD_CLK ; PIN_AE13 ; QSF Assignment ;
+; Location ; ; ; SD_CMD ; PIN_AD14 ; QSF Assignment ;
+; Location ; ; ; SD_DAT[0] ; PIN_AE14 ; QSF Assignment ;
+; Location ; ; ; SD_DAT[1] ; PIN_AF13 ; QSF Assignment ;
+; Location ; ; ; SD_DAT[2] ; PIN_AB14 ; QSF Assignment ;
+; Location ; ; ; SD_DAT[3] ; PIN_AC14 ; QSF Assignment ;
+; Location ; ; ; SD_WP_N ; PIN_AF14 ; QSF Assignment ;
+; Location ; ; ; SMA_CLKIN ; PIN_AH14 ; QSF Assignment ;
+; Location ; ; ; SMA_CLKOUT ; PIN_AE23 ; QSF Assignment ;
+; Location ; ; ; SRAM_ADDR[0] ; PIN_AB7 ; QSF Assignment ;
+; Location ; ; ; SRAM_ADDR[10] ; PIN_AF2 ; QSF Assignment ;
+; Location ; ; ; SRAM_ADDR[11] ; PIN_AD3 ; QSF Assignment ;
+; Location ; ; ; SRAM_ADDR[12] ; PIN_AB4 ; QSF Assignment ;
+; Location ; ; ; SRAM_ADDR[13] ; PIN_AC3 ; QSF Assignment ;
+; Location ; ; ; SRAM_ADDR[14] ; PIN_AA4 ; QSF Assignment ;
+; Location ; ; ; SRAM_ADDR[15] ; PIN_AB11 ; QSF Assignment ;
+; Location ; ; ; SRAM_ADDR[16] ; PIN_AC11 ; QSF Assignment ;
+; Location ; ; ; SRAM_ADDR[17] ; PIN_AB9 ; QSF Assignment ;
+; Location ; ; ; SRAM_ADDR[18] ; PIN_AB8 ; QSF Assignment ;
+; Location ; ; ; SRAM_ADDR[19] ; PIN_T8 ; QSF Assignment ;
+; Location ; ; ; SRAM_ADDR[1] ; PIN_AD7 ; QSF Assignment ;
+; Location ; ; ; SRAM_ADDR[2] ; PIN_AE7 ; QSF Assignment ;
+; Location ; ; ; SRAM_ADDR[3] ; PIN_AC7 ; QSF Assignment ;
+; Location ; ; ; SRAM_ADDR[4] ; PIN_AB6 ; QSF Assignment ;
+; Location ; ; ; SRAM_ADDR[5] ; PIN_AE6 ; QSF Assignment ;
+; Location ; ; ; SRAM_ADDR[6] ; PIN_AB5 ; QSF Assignment ;
+; Location ; ; ; SRAM_ADDR[7] ; PIN_AC5 ; QSF Assignment ;
+; Location ; ; ; SRAM_ADDR[8] ; PIN_AF5 ; QSF Assignment ;
+; Location ; ; ; SRAM_ADDR[9] ; PIN_T7 ; QSF Assignment ;
+; Location ; ; ; SRAM_CE_N ; PIN_AF8 ; QSF Assignment ;
+; Location ; ; ; SRAM_DQ[0] ; PIN_AH3 ; QSF Assignment ;
+; Location ; ; ; SRAM_DQ[10] ; PIN_AE2 ; QSF Assignment ;
+; Location ; ; ; SRAM_DQ[11] ; PIN_AE1 ; QSF Assignment ;
+; Location ; ; ; SRAM_DQ[12] ; PIN_AE3 ; QSF Assignment ;
+; Location ; ; ; SRAM_DQ[13] ; PIN_AE4 ; QSF Assignment ;
+; Location ; ; ; SRAM_DQ[14] ; PIN_AF3 ; QSF Assignment ;
+; Location ; ; ; SRAM_DQ[15] ; PIN_AG3 ; QSF Assignment ;
+; Location ; ; ; SRAM_DQ[1] ; PIN_AF4 ; QSF Assignment ;
+; Location ; ; ; SRAM_DQ[2] ; PIN_AG4 ; QSF Assignment ;
+; Location ; ; ; SRAM_DQ[3] ; PIN_AH4 ; QSF Assignment ;
+; Location ; ; ; SRAM_DQ[4] ; PIN_AF6 ; QSF Assignment ;
+; Location ; ; ; SRAM_DQ[5] ; PIN_AG6 ; QSF Assignment ;
+; Location ; ; ; SRAM_DQ[6] ; PIN_AH6 ; QSF Assignment ;
+; Location ; ; ; SRAM_DQ[7] ; PIN_AF7 ; QSF Assignment ;
+; Location ; ; ; SRAM_DQ[8] ; PIN_AD1 ; QSF Assignment ;
+; Location ; ; ; SRAM_DQ[9] ; PIN_AD2 ; QSF Assignment ;
+; Location ; ; ; SRAM_LB_N ; PIN_AD4 ; QSF Assignment ;
+; Location ; ; ; SRAM_OE_N ; PIN_AD5 ; QSF Assignment ;
+; Location ; ; ; SRAM_UB_N ; PIN_AC4 ; QSF Assignment ;
+; Location ; ; ; SRAM_WE_N ; PIN_AE8 ; QSF Assignment ;
+; Location ; ; ; SW[10] ; PIN_AC24 ; QSF Assignment ;
+; Location ; ; ; SW[11] ; PIN_AB24 ; QSF Assignment ;
+; Location ; ; ; SW[12] ; PIN_AB23 ; QSF Assignment ;
+; Location ; ; ; SW[13] ; PIN_AA24 ; QSF Assignment ;
+; Location ; ; ; SW[14] ; PIN_AA23 ; QSF Assignment ;
+; Location ; ; ; SW[15] ; PIN_AA22 ; QSF Assignment ;
+; Location ; ; ; SW[16] ; PIN_Y24 ; QSF Assignment ;
+; Location ; ; ; SW[17] ; PIN_Y23 ; QSF Assignment ;
+; Location ; ; ; SW[9] ; PIN_AB25 ; QSF Assignment ;
+; Location ; ; ; TD_CLK27 ; PIN_B14 ; QSF Assignment ;
+; Location ; ; ; TD_DATA[0] ; PIN_E8 ; QSF Assignment ;
+; Location ; ; ; TD_DATA[1] ; PIN_A7 ; QSF Assignment ;
+; Location ; ; ; TD_DATA[2] ; PIN_D8 ; QSF Assignment ;
+; Location ; ; ; TD_DATA[3] ; PIN_C7 ; QSF Assignment ;
+; Location ; ; ; TD_DATA[4] ; PIN_D7 ; QSF Assignment ;
+; Location ; ; ; TD_DATA[5] ; PIN_D6 ; QSF Assignment ;
+; Location ; ; ; TD_DATA[6] ; PIN_E7 ; QSF Assignment ;
+; Location ; ; ; TD_DATA[7] ; PIN_F7 ; QSF Assignment ;
+; Location ; ; ; TD_HS ; PIN_E5 ; QSF Assignment ;
+; Location ; ; ; TD_RESET_N ; PIN_G7 ; QSF Assignment ;
+; Location ; ; ; TD_VS ; PIN_E4 ; QSF Assignment ;
+; Location ; ; ; UART_CTS ; PIN_G14 ; QSF Assignment ;
+; Location ; ; ; UART_RTS ; PIN_J13 ; QSF Assignment ;
+; Location ; ; ; UART_RXD ; PIN_G12 ; QSF Assignment ;
+; Location ; ; ; UART_TXD ; PIN_G9 ; QSF Assignment ;
+; Location ; ; ; VGA_BLANK_N ; PIN_F11 ; QSF Assignment ;
+; Location ; ; ; VGA_B[0] ; PIN_B10 ; QSF Assignment ;
+; Location ; ; ; VGA_B[1] ; PIN_A10 ; QSF Assignment ;
+; Location ; ; ; VGA_B[2] ; PIN_C11 ; QSF Assignment ;
+; Location ; ; ; VGA_B[3] ; PIN_B11 ; QSF Assignment ;
+; Location ; ; ; VGA_B[4] ; PIN_A11 ; QSF Assignment ;
+; Location ; ; ; VGA_B[5] ; PIN_C12 ; QSF Assignment ;
+; Location ; ; ; VGA_B[6] ; PIN_D11 ; QSF Assignment ;
+; Location ; ; ; VGA_B[7] ; PIN_D12 ; QSF Assignment ;
+; Location ; ; ; VGA_CLK ; PIN_A12 ; QSF Assignment ;
+; Location ; ; ; VGA_G[0] ; PIN_G8 ; QSF Assignment ;
+; Location ; ; ; VGA_G[1] ; PIN_G11 ; QSF Assignment ;
+; Location ; ; ; VGA_G[2] ; PIN_F8 ; QSF Assignment ;
+; Location ; ; ; VGA_G[3] ; PIN_H12 ; QSF Assignment ;
+; Location ; ; ; VGA_G[4] ; PIN_C8 ; QSF Assignment ;
+; Location ; ; ; VGA_G[5] ; PIN_B8 ; QSF Assignment ;
+; Location ; ; ; VGA_G[6] ; PIN_F10 ; QSF Assignment ;
+; Location ; ; ; VGA_G[7] ; PIN_C9 ; QSF Assignment ;
+; Location ; ; ; VGA_HS ; PIN_G13 ; QSF Assignment ;
+; Location ; ; ; VGA_R[0] ; PIN_E12 ; QSF Assignment ;
+; Location ; ; ; VGA_R[1] ; PIN_E11 ; QSF Assignment ;
+; Location ; ; ; VGA_R[2] ; PIN_D10 ; QSF Assignment ;
+; Location ; ; ; VGA_R[3] ; PIN_F12 ; QSF Assignment ;
+; Location ; ; ; VGA_R[4] ; PIN_G10 ; QSF Assignment ;
+; Location ; ; ; VGA_R[5] ; PIN_J12 ; QSF Assignment ;
+; Location ; ; ; VGA_R[6] ; PIN_H8 ; QSF Assignment ;
+; Location ; ; ; VGA_R[7] ; PIN_H10 ; QSF Assignment ;
+; Location ; ; ; VGA_SYNC_N ; PIN_C10 ; QSF Assignment ;
+; Location ; ; ; VGA_VS ; PIN_C13 ; QSF Assignment ;
++----------+----------------+--------------+------------------+---------------+----------------+
+
+
++-------------------------------------------------------------------------------------------------+
+; Incremental Compilation Preservation Summary ;
++---------------------+-------------------+----------------------------+--------------------------+
+; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ;
++---------------------+-------------------+----------------------------+--------------------------+
+; Placement (by node) ; ; ; ;
+; -- Requested ; 0.00 % ( 0 / 55 ) ; 0.00 % ( 0 / 55 ) ; 0.00 % ( 0 / 55 ) ;
+; -- Achieved ; 0.00 % ( 0 / 55 ) ; 0.00 % ( 0 / 55 ) ; 0.00 % ( 0 / 55 ) ;
+; ; ; ; ;
+; Routing (by net) ; ; ; ;
+; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
+; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
++---------------------+-------------------+----------------------------+--------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Partition Settings ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ;
+; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Placement Preservation ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Top ; 0.00 % ( 0 / 45 ) ; N/A ; Source File ; N/A ; ;
+; hard_block:auto_generated_inst ; 0.00 % ( 0 / 10 ) ; N/A ; Source File ; N/A ; ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.pin.
+
+
++---------------------------------------------------------------------+
+; Fitter Resource Usage Summary ;
++---------------------------------------------+-----------------------+
+; Resource ; Usage ;
++---------------------------------------------+-----------------------+
+; Total logic elements ; 8 / 114,480 ( < 1 % ) ;
+; -- Combinational with no register ; 0 ;
+; -- Register only ; 8 ;
+; -- Combinational with a register ; 0 ;
+; ; ;
+; Logic element usage by number of LUT inputs ; ;
+; -- 4 input functions ; 0 ;
+; -- 3 input functions ; 0 ;
+; -- <=2 input functions ; 0 ;
+; -- Register only ; 8 ;
+; ; ;
+; Logic elements by mode ; ;
+; -- normal mode ; 0 ;
+; -- arithmetic mode ; 0 ;
+; ; ;
+; Total registers* ; 8 / 117,053 ( < 1 % ) ;
+; -- Dedicated logic registers ; 8 / 114,480 ( < 1 % ) ;
+; -- I/O registers ; 0 / 2,573 ( 0 % ) ;
+; ; ;
+; Total LABs: partially or completely used ; 1 / 7,155 ( < 1 % ) ;
+; Virtual pins ; 0 ;
+; I/O pins ; 18 / 529 ( 3 % ) ;
+; -- Clock pins ; 0 / 7 ( 0 % ) ;
+; -- Dedicated input pins ; 0 / 9 ( 0 % ) ;
+; ; ;
+; M9Ks ; 0 / 432 ( 0 % ) ;
+; Total block memory bits ; 0 / 3,981,312 ( 0 % ) ;
+; Total block memory implementation bits ; 0 / 3,981,312 ( 0 % ) ;
+; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ;
+; PLLs ; 0 / 4 ( 0 % ) ;
+; Global signals ; 0 ;
+; -- Global clocks ; 0 / 20 ( 0 % ) ;
+; JTAGs ; 0 / 1 ( 0 % ) ;
+; CRC blocks ; 0 / 1 ( 0 % ) ;
+; ASMI blocks ; 0 / 1 ( 0 % ) ;
+; Oscillator blocks ; 0 / 1 ( 0 % ) ;
+; Impedance control blocks ; 0 / 4 ( 0 % ) ;
+; Average interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.1% ;
+; Peak interconnect usage (total/H/V) ; 0.5% / 0.4% / 0.8% ;
+; Maximum fan-out ; 8 ;
+; Highest non-global fan-out ; 8 ;
+; Total fan-out ; 57 ;
+; Average fan-out ; 1.02 ;
++---------------------------------------------+-----------------------+
+* Register count does not include registers inside RAM blocks or DSP blocks.
+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Fitter Partition Statistics ;
++---------------------------------------------+----------------------+--------------------------------+
+; Statistic ; Top ; hard_block:auto_generated_inst ;
++---------------------------------------------+----------------------+--------------------------------+
+; Difficulty Clustering Region ; Low ; Low ;
+; ; ; ;
+; Total logic elements ; 8 / 114480 ( < 1 % ) ; 0 / 114480 ( 0 % ) ;
+; -- Combinational with no register ; 0 ; 0 ;
+; -- Register only ; 8 ; 0 ;
+; -- Combinational with a register ; 0 ; 0 ;
+; ; ; ;
+; Logic element usage by number of LUT inputs ; ; ;
+; -- 4 input functions ; 0 ; 0 ;
+; -- 3 input functions ; 0 ; 0 ;
+; -- <=2 input functions ; 0 ; 0 ;
+; -- Register only ; 8 ; 0 ;
+; ; ; ;
+; Logic elements by mode ; ; ;
+; -- normal mode ; 0 ; 0 ;
+; -- arithmetic mode ; 0 ; 0 ;
+; ; ; ;
+; Total registers ; 8 ; 0 ;
+; -- Dedicated logic registers ; 8 / 114480 ( < 1 % ) ; 0 / 114480 ( 0 % ) ;
+; -- I/O registers ; 0 ; 0 ;
+; ; ; ;
+; Total LABs: partially or completely used ; 1 / 7155 ( < 1 % ) ; 0 / 7155 ( 0 % ) ;
+; ; ; ;
+; Virtual pins ; 0 ; 0 ;
+; I/O pins ; 18 ; 0 ;
+; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ; 0 / 532 ( 0 % ) ;
+; Total memory bits ; 0 ; 0 ;
+; Total RAM block bits ; 0 ; 0 ;
+; ; ; ;
+; Connections ; ; ;
+; -- Input Connections ; 0 ; 0 ;
+; -- Registered Input Connections ; 0 ; 0 ;
+; -- Output Connections ; 0 ; 0 ;
+; -- Registered Output Connections ; 0 ; 0 ;
+; ; ; ;
+; Internal Connections ; ; ;
+; -- Total Connections ; 52 ; 5 ;
+; -- Registered Connections ; 8 ; 0 ;
+; ; ; ;
+; External Connections ; ; ;
+; -- Top ; 0 ; 0 ;
+; -- hard_block:auto_generated_inst ; 0 ; 0 ;
+; ; ; ;
+; Partition Interface ; ; ;
+; -- Input Ports ; 10 ; 0 ;
+; -- Output Ports ; 8 ; 0 ;
+; -- Bidir Ports ; 0 ; 0 ;
+; ; ; ;
+; Registered Ports ; ; ;
+; -- Registered Input Ports ; 0 ; 0 ;
+; -- Registered Output Ports ; 0 ; 0 ;
+; ; ; ;
+; Port Connectivity ; ; ;
+; -- Input Ports driven by GND ; 0 ; 0 ;
+; -- Output Ports driven by GND ; 0 ; 0 ;
+; -- Input Ports driven by VCC ; 0 ; 0 ;
+; -- Output Ports driven by VCC ; 0 ; 0 ;
+; -- Input Ports with no Source ; 0 ; 0 ;
+; -- Output Ports with no Source ; 0 ; 0 ;
+; -- Input Ports with no Fanout ; 0 ; 0 ;
+; -- Output Ports with no Fanout ; 0 ; 0 ;
++---------------------------------------------+----------------------+--------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins ;
++--------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; Slew Rate ;
++--------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
+; KEY[0] ; M23 ; 6 ; 115 ; 40 ; 7 ; 8 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
+; SW[0] ; AB28 ; 5 ; 115 ; 17 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
+; SW[1] ; AC28 ; 5 ; 115 ; 14 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
+; SW[2] ; AC27 ; 5 ; 115 ; 15 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
+; SW[3] ; AD27 ; 5 ; 115 ; 13 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
+; SW[4] ; AB27 ; 5 ; 115 ; 18 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
+; SW[5] ; AC26 ; 5 ; 115 ; 11 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
+; SW[6] ; AD26 ; 5 ; 115 ; 10 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
+; SW[7] ; AB26 ; 5 ; 115 ; 15 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
+; SW[8] ; AC25 ; 5 ; 115 ; 4 ; 21 ; 8 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
++--------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins ;
++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+; LEDR[0] ; G19 ; 7 ; 69 ; 73 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
+; LEDR[1] ; F19 ; 7 ; 94 ; 73 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
+; LEDR[2] ; E19 ; 7 ; 94 ; 73 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
+; LEDR[3] ; F21 ; 7 ; 107 ; 73 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
+; LEDR[4] ; F18 ; 7 ; 87 ; 73 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
+; LEDR[5] ; E18 ; 7 ; 87 ; 73 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
+; LEDR[6] ; J19 ; 7 ; 72 ; 73 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
+; LEDR[7] ; H19 ; 7 ; 72 ; 73 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
++---------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------+
+; Dual Purpose and Dedicated Pins ;
++----------+-----------------------------+--------------------------+-------------------------+---------------------------+
+; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ;
++----------+-----------------------------+--------------------------+-------------------------+---------------------------+
+; F4 ; DIFFIO_L5n, DATA1, ASDO ; As input tri-stated ; ~ALTERA_ASDO_DATA1~ ; Dual Purpose Pin ;
+; E2 ; DIFFIO_L8p, FLASH_nCE, nCSO ; As input tri-stated ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin ;
+; M6 ; nSTATUS ; - ; - ; Dedicated Programming Pin ;
+; P3 ; DCLK ; As output driving ground ; ~ALTERA_DCLK~ ; Dual Purpose Pin ;
+; N7 ; DATA0 ; As input tri-stated ; ~ALTERA_DATA0~ ; Dual Purpose Pin ;
+; P4 ; nCONFIG ; - ; - ; Dedicated Programming Pin ;
+; R8 ; nCE ; - ; - ; Dedicated Programming Pin ;
+; P24 ; CONF_DONE ; - ; - ; Dedicated Programming Pin ;
+; N22 ; MSEL0 ; - ; - ; Dedicated Programming Pin ;
+; P23 ; MSEL1 ; - ; - ; Dedicated Programming Pin ;
+; M22 ; MSEL2 ; - ; - ; Dedicated Programming Pin ;
+; P22 ; MSEL3 ; - ; - ; Dedicated Programming Pin ;
+; P28 ; DIFFIO_R23n, nCEO ; Use as programming pin ; ~ALTERA_nCEO~ ; Dual Purpose Pin ;
++----------+-----------------------------+--------------------------+-------------------------+---------------------------+
+
+
++-----------------------------------------------------------+
+; I/O Bank Usage ;
++----------+-----------------+---------------+--------------+
+; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
++----------+-----------------+---------------+--------------+
+; 1 ; 4 / 56 ( 7 % ) ; 2.5V ; -- ;
+; 2 ; 0 / 63 ( 0 % ) ; 2.5V ; -- ;
+; 3 ; 0 / 73 ( 0 % ) ; 2.5V ; -- ;
+; 4 ; 0 / 71 ( 0 % ) ; 2.5V ; -- ;
+; 5 ; 9 / 65 ( 14 % ) ; 2.5V ; -- ;
+; 6 ; 2 / 58 ( 3 % ) ; 2.5V ; -- ;
+; 7 ; 8 / 72 ( 11 % ) ; 2.5V ; -- ;
+; 8 ; 0 / 71 ( 0 % ) ; 2.5V ; -- ;
++----------+-----------------+---------------+--------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; A2 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; A3 ; 535 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A4 ; 532 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A5 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; A6 ; 504 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A7 ; 501 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A8 ; 517 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A9 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; A10 ; 491 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A11 ; 487 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A12 ; 482 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A13 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; A14 ; 472 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
+; A15 ; 470 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
+; A16 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; A17 ; 462 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A18 ; 442 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A19 ; 440 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A20 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; A21 ; 425 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A22 ; 423 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A23 ; 412 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A24 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; A25 ; 405 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A26 ; 404 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; A27 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AA1 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA3 ; 102 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AA4 ; 101 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AA5 ; 119 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AA6 ; 118 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AA7 ; 120 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AA8 ; 154 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA9 ; ; ; GNDA1 ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA10 ; 155 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA11 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AA12 ; 188 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA13 ; 190 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA14 ; 191 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA15 ; 213 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
+; AA16 ; 211 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA17 ; 241 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA18 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AA19 ; 264 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA20 ; ; ; GNDA4 ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA21 ; 269 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AA22 ; 275 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AA23 ; 280 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AA24 ; 279 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
+; AA25 ; 294 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AA26 ; 293 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AA27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AB1 ; 86 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AB2 ; 85 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AB3 ; 99 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AB4 ; 121 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
+; AB5 ; 127 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AB6 ; 126 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AB7 ; 152 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AB8 ; 148 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AB9 ; 147 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AB10 ; 173 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AB11 ; 164 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
+; AB12 ; 180 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AB13 ; 181 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
+; AB14 ; 192 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AB15 ; 214 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AB16 ; 212 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AB17 ; 242 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AB18 ; 254 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AB19 ; 253 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AB20 ; 257 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
+; AB21 ; 266 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AB22 ; 265 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AB23 ; 276 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AB24 ; 274 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AB25 ; 292 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AB26 ; 291 ; 5 ; SW[7] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
+; AB27 ; 296 ; 5 ; SW[4] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
+; AB28 ; 295 ; 5 ; SW[0] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
+; AC1 ; 94 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AC2 ; 93 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AC3 ; 95 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AC4 ; 125 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AC5 ; 124 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AC6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC7 ; 144 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AC8 ; 153 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AC9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC10 ; 174 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AC11 ; 185 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AC12 ; 179 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AC13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC14 ; 195 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AC15 ; 203 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AC16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC17 ; 221 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AC18 ; 240 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
+; AC19 ; 247 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AC20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC21 ; 258 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AC22 ; 267 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AC23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AC24 ; 273 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AC25 ; 272 ; 5 ; SW[8] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
+; AC26 ; 282 ; 5 ; SW[5] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
+; AC27 ; 290 ; 5 ; SW[2] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
+; AC28 ; 289 ; 5 ; SW[1] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
+; AD1 ; 98 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AD2 ; 97 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AD3 ; 96 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AD4 ; 130 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD5 ; 128 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD6 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AD7 ; 134 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD8 ; 143 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AD10 ; 149 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD11 ; 186 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD12 ; 182 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD13 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AD14 ; 196 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD15 ; 204 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD16 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AD17 ; 222 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD18 ; 237 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD19 ; 248 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD20 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AD21 ; 259 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD22 ; 268 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD23 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AD24 ; 260 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD25 ; 255 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AD26 ; 281 ; 5 ; SW[6] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
+; AD27 ; 286 ; 5 ; SW[3] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
+; AD28 ; 285 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AE1 ; 106 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AE2 ; 105 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AE3 ; 122 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AE4 ; 132 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE5 ; 135 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE6 ; 129 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE7 ; 158 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE8 ; 161 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE9 ; 163 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE10 ; 165 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE11 ; 171 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE12 ; 169 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE13 ; 177 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE14 ; 183 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE15 ; 205 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE16 ; 209 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE17 ; 215 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE18 ; 225 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE19 ; 231 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE20 ; 235 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE21 ; 238 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE22 ; 251 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE23 ; 261 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE24 ; 256 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE25 ; 243 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AE26 ; 278 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AE27 ; 284 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AE28 ; 283 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AF1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AF2 ; 123 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AF3 ; 138 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF4 ; 131 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF5 ; 136 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF6 ; 139 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF7 ; 159 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF8 ; 162 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF9 ; 160 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF10 ; 166 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF11 ; 172 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF12 ; 170 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF13 ; 178 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF14 ; 184 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF15 ; 206 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF16 ; 210 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF17 ; 216 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF18 ; 226 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF19 ; 232 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF20 ; 236 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF21 ; 239 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF22 ; 252 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF23 ; 262 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF24 ; 233 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF25 ; 234 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF26 ; 244 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AF27 ; 277 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; AF28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AG1 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AG2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AG3 ; 133 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG4 ; 141 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AG6 ; 145 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG7 ; 150 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG8 ; 156 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AG10 ; 167 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG11 ; 175 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG12 ; 193 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AG14 ; 199 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
+; AG15 ; 201 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
+; AG16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AG17 ; 207 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG18 ; 217 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG19 ; 219 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AG21 ; 223 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG22 ; 227 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG23 ; 229 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AG25 ; 245 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG26 ; 270 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AG27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AG28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AH2 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AH3 ; 137 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH4 ; 142 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH5 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AH6 ; 146 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH7 ; 151 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH8 ; 157 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH9 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AH10 ; 168 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH11 ; 176 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH12 ; 194 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH13 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AH14 ; 200 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
+; AH15 ; 202 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
+; AH16 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AH17 ; 208 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH18 ; 218 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH19 ; 220 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH20 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AH21 ; 224 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH22 ; 228 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH23 ; 230 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH24 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; AH25 ; 246 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH26 ; 271 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; AH27 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; B1 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; B3 ; 534 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B4 ; 533 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; B6 ; 505 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B7 ; 502 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B8 ; 518 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; B10 ; 492 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B11 ; 488 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; B13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; B14 ; 473 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
+; B15 ; 471 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
+; B16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; B17 ; 463 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B18 ; 443 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B19 ; 441 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; B21 ; 426 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B22 ; 424 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B23 ; 413 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; B25 ; 406 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B26 ; 401 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; B27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; B28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; C1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; C2 ; 1 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; C3 ; 543 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C4 ; 539 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C5 ; 538 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C6 ; 536 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C7 ; 521 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C8 ; 519 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C9 ; 510 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C10 ; 495 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C11 ; 508 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C12 ; 478 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C13 ; 474 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C14 ; 476 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C15 ; 468 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C16 ; 460 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C17 ; 438 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C18 ; 429 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C19 ; 435 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C20 ; 431 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C21 ; 422 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C22 ; 418 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C23 ; 415 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C24 ; 416 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C25 ; 411 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C26 ; 400 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; C27 ; 382 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; C28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; D1 ; 3 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; D2 ; 2 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; D3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; D4 ; 540 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D5 ; 537 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D6 ; 524 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D7 ; 522 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D8 ; 520 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D9 ; 511 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D10 ; 496 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D11 ; 509 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D12 ; 479 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D13 ; 475 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D14 ; 477 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D15 ; 469 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D16 ; 461 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D17 ; 439 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D18 ; 430 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D19 ; 436 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D20 ; 432 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D21 ; 419 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D22 ; 402 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D23 ; 414 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D24 ; 417 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D25 ; 410 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; D26 ; 383 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; D27 ; 381 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; D28 ; 380 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; E1 ; 17 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; E2 ; 16 ; 1 ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ;
+; E3 ; 7 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; E4 ; 541 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E5 ; 542 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E6 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; E7 ; 523 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E8 ; 526 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E9 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; E10 ; 516 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E11 ; 499 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E12 ; 497 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E13 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; E14 ; 486 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E15 ; 467 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E16 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; E17 ; 456 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E18 ; 427 ; 7 ; LEDR[5] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
+; E19 ; 421 ; 7 ; LEDR[2] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
+; E20 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; E21 ; 407 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E22 ; 403 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E23 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; E24 ; 433 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E25 ; 434 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; E26 ; 378 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; E27 ; 375 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; E28 ; 374 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; F1 ; 19 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; F2 ; 18 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; F3 ; 8 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; F4 ; 10 ; 1 ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ;
+; F5 ; 9 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; F6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; F7 ; 531 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F8 ; 527 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; F10 ; 512 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F11 ; 500 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F12 ; 498 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; F14 ; 485 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F15 ; 466 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; F17 ; 455 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; F18 ; 428 ; 7 ; LEDR[4] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
+; F19 ; 420 ; 7 ; LEDR[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
+; F20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; F21 ; 408 ; 7 ; LEDR[3] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
+; F22 ; 409 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
+; F23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; F24 ; 396 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; F25 ; 395 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; F26 ; 379 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; F27 ; 373 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; F28 ; 372 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; G1 ; 26 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; G2 ; 25 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; G3 ; 13 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; G4 ; 12 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; G5 ; 6 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; G6 ; 5 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; G7 ; 530 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G8 ; 528 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G9 ; 525 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
+; G10 ; 513 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G11 ; 506 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G12 ; 503 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
+; G13 ; 493 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G14 ; 484 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
+; G15 ; 457 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
+; G16 ; 453 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G17 ; 437 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
+; G18 ; 452 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G19 ; 451 ; 7 ; LEDR[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
+; G20 ; 444 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G21 ; 445 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G22 ; 449 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; G23 ; 398 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; G24 ; 397 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; G25 ; 393 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; G26 ; 392 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; G27 ; 367 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; G28 ; 366 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; H1 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; H2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; H3 ; 15 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; H4 ; 14 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; H5 ; 20 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; H6 ; 11 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; H7 ; 4 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
+; H8 ; 529 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H9 ; ; ; GNDA3 ; gnd ; ; ; -- ; ; -- ; -- ;
+; H10 ; 514 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H11 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; H12 ; 507 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H13 ; 494 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H14 ; 480 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H15 ; 464 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H16 ; 459 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H17 ; 454 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H18 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; H19 ; 446 ; 7 ; LEDR[7] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
+; H20 ; ; ; GNDA2 ; gnd ; ; ; -- ; ; -- ; -- ;
+; H21 ; 448 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; H22 ; 399 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; H23 ; 391 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; H24 ; 390 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; H25 ; 377 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; H26 ; 376 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; H27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; H28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; J1 ; 64 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
+; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; J3 ; 23 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; J4 ; 22 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; J5 ; 36 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; J6 ; 35 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; J7 ; 37 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; J8 ; ; -- ; VCCA3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; J9 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; J10 ; 515 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; J11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; J12 ; 490 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; J13 ; 489 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; J14 ; 481 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; J15 ; 465 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; J16 ; 458 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; J17 ; 450 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; J18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; J19 ; 447 ; 7 ; LEDR[6] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
+; J20 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; J21 ; ; -- ; VCCA2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; J22 ; 394 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
+; J23 ; 387 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; J24 ; 386 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; J25 ; 365 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; J26 ; 364 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; J27 ; 338 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
+; J28 ; 337 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
+; K1 ; 28 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K2 ; 27 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K3 ; 30 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K4 ; 29 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K5 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; K6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K7 ; 38 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K8 ; 39 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; K14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; K16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; K18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; K20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K21 ; 389 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K22 ; 388 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K24 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; K25 ; 371 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K26 ; 370 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K27 ; 362 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; K28 ; 361 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; L1 ; 49 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; L2 ; 48 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; L3 ; 32 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; L4 ; 31 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; L5 ; 21 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
+; L6 ; 43 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; L7 ; 42 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; L8 ; 40 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; L9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; L15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; L17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; L19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; L21 ; 385 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; L22 ; 384 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; L23 ; 360 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; L24 ; 359 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; L25 ; 369 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; L26 ; 363 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; L27 ; 358 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; L28 ; 357 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M1 ; 51 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M2 ; 50 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M3 ; 34 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M4 ; 33 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M5 ; 41 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
+; M6 ; 24 ; 1 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;
+; M7 ; 47 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M8 ; 46 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; M14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; M16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; M18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; M20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M21 ; 368 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
+; M22 ; 342 ; 6 ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ;
+; M23 ; 344 ; 6 ; KEY[0] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
+; M24 ; 347 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M25 ; 356 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M26 ; 355 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M27 ; 354 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; M28 ; 353 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N1 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; N2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N3 ; 45 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N4 ; 44 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N5 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; N6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N7 ; 56 ; 1 ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ;
+; N8 ; 54 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; N15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; N17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; N19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; N21 ; 348 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
+; N22 ; 340 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;
+; N23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N24 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; N25 ; 352 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N26 ; 351 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; N27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N28 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; P1 ; 53 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; P2 ; 52 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; P3 ; 55 ; 1 ; ~ALTERA_DCLK~ ; output ; 2.5 V ; ; Row I/O ; N ; no ; On ;
+; P4 ; 57 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
+; P5 ; 59 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
+; P6 ; 61 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
+; P7 ; 58 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
+; P8 ; 60 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
+; P9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; P10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; P12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; P14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; P16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; P18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; P20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P21 ; 334 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; P22 ; 343 ; 6 ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ;
+; P23 ; 341 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;
+; P24 ; 339 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ;
+; P25 ; 346 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; P26 ; 345 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; P27 ; 350 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; P28 ; 349 ; 6 ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
+; R1 ; 68 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R2 ; 67 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R3 ; 73 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R4 ; 74 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R5 ; 77 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R6 ; 70 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R7 ; 69 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R8 ; 62 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ;
+; R9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; R11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; R13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; R15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; R17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; R19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; R21 ; 333 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R22 ; 332 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R23 ; 331 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R24 ; 330 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R25 ; 327 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R26 ; 326 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R27 ; 329 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; R28 ; 328 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; T1 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; T2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T3 ; 76 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; T4 ; 75 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; T5 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; T6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T7 ; 78 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
+; T8 ; 100 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
+; T9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; T12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; T14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; T16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; T18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T21 ; 325 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; T22 ; 324 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; T23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T24 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; T25 ; 323 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; T26 ; 322 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; T27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; T28 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; U1 ; 80 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; U2 ; 79 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; U3 ; 71 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; U4 ; 72 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; U5 ; 90 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; U6 ; 89 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; U7 ; 103 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; U8 ; 104 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; U9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; U11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; U13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; U15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; U17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; U19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; U20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; U21 ; 319 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; U22 ; 313 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; U23 ; 305 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
+; U24 ; 316 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
+; U25 ; 315 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; U26 ; 314 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; U27 ; 318 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; U28 ; 317 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; V1 ; 84 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; V2 ; 83 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; V3 ; 82 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; V4 ; 81 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; V5 ; 108 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; V6 ; 107 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; V7 ; 110 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; V8 ; 109 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; V9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; V10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; V12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; V14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; V16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; V18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; V20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; V21 ; 311 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; V22 ; 312 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; V23 ; 309 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; V24 ; 308 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; V25 ; 307 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; V26 ; 306 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; V27 ; 304 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; V28 ; 303 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W1 ; 88 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W2 ; 87 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W3 ; 112 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W4 ; 111 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W5 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; W6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W7 ; 115 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W8 ; 116 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; W11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; W13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; W15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; W17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; W19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; W21 ; 310 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W22 ; 321 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; W24 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; W25 ; 300 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W26 ; 299 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W27 ; 301 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; W28 ; 302 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y1 ; 66 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
+; Y2 ; 65 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
+; Y3 ; 92 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y4 ; 91 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y5 ; 114 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y6 ; 113 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y7 ; 117 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y8 ; ; -- ; VCCA1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; Y9 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; Y10 ; 140 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
+; Y11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y12 ; 187 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; Y13 ; 189 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; Y14 ; 197 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; Y15 ; 198 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; Y16 ; 250 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; Y17 ; 249 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; Y18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; Y19 ; 263 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; Y20 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; Y21 ; ; -- ; VCCA4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
+; Y22 ; 320 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y23 ; 288 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y24 ; 287 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y25 ; 298 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y26 ; 297 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; Y27 ; 336 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
+; Y28 ; 335 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++------------------------------------------+
+; I/O Assignment Warnings ;
++----------+-------------------------------+
+; Pin Name ; Reason ;
++----------+-------------------------------+
+; LEDR[7] ; Incomplete set of assignments ;
+; LEDR[6] ; Incomplete set of assignments ;
+; LEDR[5] ; Incomplete set of assignments ;
+; LEDR[4] ; Incomplete set of assignments ;
+; LEDR[3] ; Incomplete set of assignments ;
+; LEDR[2] ; Incomplete set of assignments ;
+; LEDR[1] ; Incomplete set of assignments ;
+; LEDR[0] ; Incomplete set of assignments ;
+; SW[7] ; Incomplete set of assignments ;
+; KEY[0] ; Incomplete set of assignments ;
+; SW[8] ; Incomplete set of assignments ;
+; SW[6] ; Incomplete set of assignments ;
+; SW[5] ; Incomplete set of assignments ;
+; SW[4] ; Incomplete set of assignments ;
+; SW[3] ; Incomplete set of assignments ;
+; SW[2] ; Incomplete set of assignments ;
+; SW[1] ; Incomplete set of assignments ;
+; SW[0] ; Incomplete set of assignments ;
++----------+-------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity ;
++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------------+--------------+--------------+
+; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------------+--------------+--------------+
+; |RegisterDemo ; 8 (0) ; 8 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 18 ; 0 ; 0 (0) ; 8 (0) ; 0 (0) ; |RegisterDemo ; RegisterDemo ; work ;
+; |Register8:inst| ; 8 (8) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 8 (8) ; 0 (0) ; |RegisterDemo|Register8:inst ; Register8 ; work ;
++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------------+--------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++-----------------------------------------------------------------------------------------+
+; Delay Chain Summary ;
++---------+----------+---------------+---------------+-----------------------+-----+------+
+; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
++---------+----------+---------------+---------------+-----------------------+-----+------+
+; LEDR[7] ; Output ; -- ; -- ; -- ; -- ; -- ;
+; LEDR[6] ; Output ; -- ; -- ; -- ; -- ; -- ;
+; LEDR[5] ; Output ; -- ; -- ; -- ; -- ; -- ;
+; LEDR[4] ; Output ; -- ; -- ; -- ; -- ; -- ;
+; LEDR[3] ; Output ; -- ; -- ; -- ; -- ; -- ;
+; LEDR[2] ; Output ; -- ; -- ; -- ; -- ; -- ;
+; LEDR[1] ; Output ; -- ; -- ; -- ; -- ; -- ;
+; LEDR[0] ; Output ; -- ; -- ; -- ; -- ; -- ;
+; SW[7] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
+; KEY[0] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ;
+; SW[8] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ;
+; SW[6] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
+; SW[5] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ;
+; SW[4] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ;
+; SW[3] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ;
+; SW[2] ; Input ; -- ; (6) 1314 ps ; -- ; -- ; -- ;
+; SW[1] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
+; SW[0] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
++---------+----------+---------------+---------------+-----------------------+-----+------+
+
+
++-----------------------------------------------------------------------+
+; Pad To Core Delay Chain Fanout ;
++-----------------------------------------+-------------------+---------+
+; Source Pin / Fanout ; Pad To Core Index ; Setting ;
++-----------------------------------------+-------------------+---------+
+; SW[7] ; ; ;
+; - Register8:inst|dataOut[7]~feeder ; 0 ; 6 ;
+; KEY[0] ; ; ;
+; - Register8:inst|dataOut[0] ; 0 ; 0 ;
+; - Register8:inst|dataOut[1] ; 0 ; 0 ;
+; - Register8:inst|dataOut[2] ; 0 ; 0 ;
+; - Register8:inst|dataOut[3] ; 0 ; 0 ;
+; - Register8:inst|dataOut[4] ; 0 ; 0 ;
+; - Register8:inst|dataOut[5] ; 0 ; 0 ;
+; - Register8:inst|dataOut[6] ; 0 ; 0 ;
+; - Register8:inst|dataOut[7] ; 0 ; 0 ;
+; SW[8] ; ; ;
+; - Register8:inst|dataOut[0] ; 1 ; 6 ;
+; - Register8:inst|dataOut[1] ; 1 ; 6 ;
+; - Register8:inst|dataOut[2] ; 1 ; 6 ;
+; - Register8:inst|dataOut[3] ; 1 ; 6 ;
+; - Register8:inst|dataOut[4] ; 1 ; 6 ;
+; - Register8:inst|dataOut[5] ; 1 ; 6 ;
+; - Register8:inst|dataOut[6] ; 1 ; 6 ;
+; - Register8:inst|dataOut[7] ; 1 ; 6 ;
+; SW[6] ; ; ;
+; - Register8:inst|dataOut[6] ; 0 ; 6 ;
+; SW[5] ; ; ;
+; - Register8:inst|dataOut[5]~feeder ; 1 ; 6 ;
+; SW[4] ; ; ;
+; - Register8:inst|dataOut[4] ; 1 ; 6 ;
+; SW[3] ; ; ;
+; - Register8:inst|dataOut[3] ; 1 ; 6 ;
+; SW[2] ; ; ;
+; - Register8:inst|dataOut[2] ; 1 ; 6 ;
+; SW[1] ; ; ;
+; - Register8:inst|dataOut[1] ; 0 ; 6 ;
+; SW[0] ; ; ;
+; - Register8:inst|dataOut[0] ; 0 ; 6 ;
++-----------------------------------------+-------------------+---------+
+
+
++---------------------------------------------------------------------------------------------------------------------------+
+; Control Signals ;
++--------+----------+---------+--------------+--------+----------------------+------------------+---------------------------+
+; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++--------+----------+---------+--------------+--------+----------------------+------------------+---------------------------+
+; KEY[0] ; PIN_M23 ; 8 ; Clock ; no ; -- ; -- ; -- ;
+; SW[8] ; PIN_AC25 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
++--------+----------+---------+--------------+--------+----------------------+------------------+---------------------------+
+
+
++------------------------------------------------+
+; Routing Usage Summary ;
++-----------------------+------------------------+
+; Routing Resource Type ; Usage ;
++-----------------------+------------------------+
+; Block interconnects ; 18 / 342,891 ( < 1 % ) ;
+; C16 interconnects ; 25 / 10,120 ( < 1 % ) ;
+; C4 interconnects ; 45 / 209,544 ( < 1 % ) ;
+; Direct links ; 0 / 342,891 ( 0 % ) ;
+; Global clocks ; 0 / 20 ( 0 % ) ;
+; Local interconnects ; 0 / 119,088 ( 0 % ) ;
+; R24 interconnects ; 16 / 9,963 ( < 1 % ) ;
+; R4 interconnects ; 29 / 289,782 ( < 1 % ) ;
++-----------------------+------------------------+
+
+
++--------------------------------------------------------------------------+
+; LAB Logic Elements ;
++--------------------------------------------+-----------------------------+
+; Number of Logic Elements (Average = 8.00) ; Number of LABs (Total = 1) ;
++--------------------------------------------+-----------------------------+
+; 1 ; 0 ;
+; 2 ; 0 ;
+; 3 ; 0 ;
+; 4 ; 0 ;
+; 5 ; 0 ;
+; 6 ; 0 ;
+; 7 ; 0 ;
+; 8 ; 1 ;
+; 9 ; 0 ;
+; 10 ; 0 ;
+; 11 ; 0 ;
+; 12 ; 0 ;
+; 13 ; 0 ;
+; 14 ; 0 ;
+; 15 ; 0 ;
+; 16 ; 0 ;
++--------------------------------------------+-----------------------------+
+
+
++------------------------------------------------------------------+
+; LAB-wide Signals ;
++------------------------------------+-----------------------------+
+; LAB-wide Signals (Average = 2.00) ; Number of LABs (Total = 1) ;
++------------------------------------+-----------------------------+
+; 1 Clock ; 1 ;
+; 1 Clock enable ; 1 ;
++------------------------------------+-----------------------------+
+
+
++----------------------------------------------------------------------------+
+; LAB Signals Sourced ;
++----------------------------------------------+-----------------------------+
+; Number of Signals Sourced (Average = 10.00) ; Number of LABs (Total = 1) ;
++----------------------------------------------+-----------------------------+
+; 0 ; 0 ;
+; 1 ; 0 ;
+; 2 ; 0 ;
+; 3 ; 0 ;
+; 4 ; 0 ;
+; 5 ; 0 ;
+; 6 ; 0 ;
+; 7 ; 0 ;
+; 8 ; 0 ;
+; 9 ; 0 ;
+; 10 ; 1 ;
++----------------------------------------------+-----------------------------+
+
+
++-------------------------------------------------------------------------------+
+; LAB Signals Sourced Out ;
++-------------------------------------------------+-----------------------------+
+; Number of Signals Sourced Out (Average = 8.00) ; Number of LABs (Total = 1) ;
++-------------------------------------------------+-----------------------------+
+; 0 ; 0 ;
+; 1 ; 0 ;
+; 2 ; 0 ;
+; 3 ; 0 ;
+; 4 ; 0 ;
+; 5 ; 0 ;
+; 6 ; 0 ;
+; 7 ; 0 ;
+; 8 ; 1 ;
++-------------------------------------------------+-----------------------------+
+
+
++----------------------------------------------------------------------------+
+; LAB Distinct Inputs ;
++----------------------------------------------+-----------------------------+
+; Number of Distinct Inputs (Average = 10.00) ; Number of LABs (Total = 1) ;
++----------------------------------------------+-----------------------------+
+; 0 ; 0 ;
+; 1 ; 0 ;
+; 2 ; 0 ;
+; 3 ; 0 ;
+; 4 ; 0 ;
+; 5 ; 0 ;
+; 6 ; 0 ;
+; 7 ; 0 ;
+; 8 ; 0 ;
+; 9 ; 0 ;
+; 10 ; 1 ;
++----------------------------------------------+-----------------------------+
+
+
++------------------------------------------+
+; I/O Rules Summary ;
++----------------------------------+-------+
+; I/O Rules Statistic ; Total ;
++----------------------------------+-------+
+; Total I/O Rules ; 30 ;
+; Number of I/O Rules Passed ; 12 ;
+; Number of I/O Rules Failed ; 0 ;
+; Number of I/O Rules Unchecked ; 0 ;
+; Number of I/O Rules Inapplicable ; 18 ;
++----------------------------------+-------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Details ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ;
+; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
+; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
+; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ;
+; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ;
+; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ;
+; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ;
+; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ;
+; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
+; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
+; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
+; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ;
+; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ;
+; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
+; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ;
+; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
+; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
+; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ;
+; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
+; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
+; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ;
+; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
+; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
+; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
+; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
+; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ;
+; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ;
+; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ;
+; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ;
+; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ;
+; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Matrix ;
++--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+
+; Pin/Rules ; IO_000002 ; IO_000001 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000047 ; IO_000046 ; IO_000045 ; IO_000027 ; IO_000026 ; IO_000024 ; IO_000023 ; IO_000022 ; IO_000021 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000033 ; IO_000034 ; IO_000042 ;
++--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+
+; Total Pass ; 0 ; 18 ; 18 ; 0 ; 0 ; 18 ; 18 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 10 ; 8 ; 0 ; 10 ; 0 ; 0 ; 8 ; 0 ; 18 ; 18 ; 18 ; 0 ; 0 ;
+; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; Total Inapplicable ; 18 ; 0 ; 0 ; 18 ; 18 ; 0 ; 0 ; 18 ; 18 ; 18 ; 18 ; 18 ; 18 ; 10 ; 18 ; 18 ; 18 ; 8 ; 10 ; 18 ; 8 ; 18 ; 18 ; 10 ; 18 ; 0 ; 0 ; 0 ; 18 ; 18 ;
+; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; LEDR[7] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
+; LEDR[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
+; LEDR[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
+; LEDR[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
+; LEDR[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
+; LEDR[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
+; LEDR[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
+; LEDR[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
+; SW[7] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
+; KEY[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
+; SW[8] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
+; SW[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
+; SW[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
+; SW[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
+; SW[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
+; SW[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
+; SW[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
+; SW[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ;
++--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+
+
+
++---------------------------------------------------------------------------------------------+
+; Fitter Device Options ;
++------------------------------------------------------------------+--------------------------+
+; Option ; Setting ;
++------------------------------------------------------------------+--------------------------+
+; Enable user-supplied start-up clock (CLKUSR) ; Off ;
+; Enable device-wide reset (DEV_CLRn) ; Off ;
+; Enable device-wide output enable (DEV_OE) ; Off ;
+; Enable INIT_DONE output ; Off ;
+; Configuration scheme ; Active Serial ;
+; Error detection CRC ; Off ;
+; Enable open drain on CRC_ERROR pin ; Off ;
+; Enable input tri-state on active configuration pins in user mode ; Off ;
+; Configuration Voltage Level ; Auto ;
+; Force Configuration Voltage Level ; Off ;
+; nCEO ; As output driving ground ;
+; Data[0] ; As input tri-stated ;
+; Data[1]/ASDO ; As input tri-stated ;
+; Data[7..2] ; Unreserved ;
+; FLASH_nCE/nCSO ; As input tri-stated ;
+; Other Active Parallel pins ; Unreserved ;
+; DCLK ; As output driving ground ;
++------------------------------------------------------------------+--------------------------+
+
+
++------------------------------------+
+; Operating Settings and Conditions ;
++---------------------------+--------+
+; Setting ; Value ;
++---------------------------+--------+
+; Nominal Core Voltage ; 1.20 V ;
+; Low Junction Temperature ; 0 °C ;
+; High Junction Temperature ; 85 °C ;
++---------------------------+--------+
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info (119006): Selected device EP4CE115F29C7 for design "RegisterDemo"
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
+Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
+ Info (176445): Device EP4CE40F29C7 is compatible
+ Info (176445): Device EP4CE40F29I7 is compatible
+ Info (176445): Device EP4CE30F29C7 is compatible
+ Info (176445): Device EP4CE30F29I7 is compatible
+ Info (176445): Device EP4CE55F29C7 is compatible
+ Info (176445): Device EP4CE55F29I7 is compatible
+ Info (176445): Device EP4CE75F29C7 is compatible
+ Info (176445): Device EP4CE75F29I7 is compatible
+ Info (176445): Device EP4CE115F29I7 is compatible
+Info (169124): Fitter converted 5 user pins into dedicated programming pins
+ Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4
+ Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2
+ Info (169125): Pin ~ALTERA_DCLK~ is reserved at location P3
+ Info (169125): Pin ~ALTERA_DATA0~ is reserved at location N7
+ Info (169125): Pin ~ALTERA_nCEO~ is reserved at location P28
+Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'RegisterDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332144): No user constrained base clocks found in the design
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
+Info (176233): Starting register packing
+Info (176235): Finished register packing
+ Extra Info (176219): No registers were packed into other blocks
+Warning (15705): Ignored locations or region assignments to the following nodes
+ Warning (15706): Node "AUD_ADCDAT" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "AUD_ADCLRCK" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "AUD_BCLK" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "AUD_DACDAT" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "AUD_DACLRCK" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "AUD_XCK" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "CLOCK2_50" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "CLOCK3_50" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "CLOCK_50" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DRAM_ADDR[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DRAM_ADDR[10]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DRAM_ADDR[11]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DRAM_ADDR[12]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DRAM_ADDR[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DRAM_ADDR[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DRAM_ADDR[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DRAM_ADDR[4]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DRAM_ADDR[5]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DRAM_ADDR[6]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DRAM_ADDR[7]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DRAM_ADDR[8]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DRAM_ADDR[9]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DRAM_BA[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DRAM_BA[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DRAM_CAS_N" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DRAM_CKE" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DRAM_CLK" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DRAM_CS_N" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DRAM_DQM[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DRAM_DQM[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DRAM_DQM[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DRAM_DQM[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DRAM_DQ[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DRAM_DQ[10]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DRAM_DQ[11]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DRAM_DQ[12]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DRAM_DQ[13]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DRAM_DQ[14]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DRAM_DQ[15]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DRAM_DQ[16]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DRAM_DQ[17]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DRAM_DQ[18]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DRAM_DQ[19]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DRAM_DQ[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DRAM_DQ[20]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DRAM_DQ[21]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DRAM_DQ[22]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DRAM_DQ[23]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DRAM_DQ[24]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DRAM_DQ[25]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DRAM_DQ[26]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DRAM_DQ[27]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DRAM_DQ[28]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DRAM_DQ[29]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DRAM_DQ[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DRAM_DQ[30]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DRAM_DQ[31]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DRAM_DQ[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DRAM_DQ[4]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DRAM_DQ[5]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DRAM_DQ[6]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DRAM_DQ[7]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DRAM_DQ[8]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DRAM_DQ[9]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DRAM_RAS_N" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "DRAM_WE_N" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "EEP_I2C_SCLK" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "EEP_I2C_SDAT" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ENET0_GTX_CLK" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ENET0_INT_N" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ENET0_LINK100" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ENET0_MDC" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ENET0_MDIO" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ENET0_RST_N" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ENET0_RX_CLK" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ENET0_RX_COL" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ENET0_RX_CRS" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ENET0_RX_DATA[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ENET0_RX_DATA[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ENET0_RX_DATA[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ENET0_RX_DATA[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ENET0_RX_DV" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ENET0_RX_ER" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ENET0_TX_CLK" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ENET0_TX_DATA[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ENET0_TX_DATA[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ENET0_TX_DATA[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ENET0_TX_DATA[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ENET0_TX_EN" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ENET0_TX_ER" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ENET1_GTX_CLK" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ENET1_INT_N" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ENET1_LINK100" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ENET1_MDC" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ENET1_MDIO" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ENET1_RST_N" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ENET1_RX_CLK" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ENET1_RX_COL" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ENET1_RX_CRS" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ENET1_RX_DATA[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ENET1_RX_DATA[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ENET1_RX_DATA[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ENET1_RX_DATA[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ENET1_RX_DV" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ENET1_RX_ER" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ENET1_TX_CLK" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ENET1_TX_DATA[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ENET1_TX_DATA[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ENET1_TX_DATA[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ENET1_TX_DATA[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ENET1_TX_EN" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ENET1_TX_ER" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "ENETCLK_25" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "EX_IO[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "EX_IO[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "EX_IO[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "EX_IO[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "EX_IO[4]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "EX_IO[5]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "EX_IO[6]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "FL_ADDR[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "FL_ADDR[10]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "FL_ADDR[11]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "FL_ADDR[12]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "FL_ADDR[13]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "FL_ADDR[14]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "FL_ADDR[15]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "FL_ADDR[16]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "FL_ADDR[17]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "FL_ADDR[18]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "FL_ADDR[19]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "FL_ADDR[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "FL_ADDR[20]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "FL_ADDR[21]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "FL_ADDR[22]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "FL_ADDR[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "FL_ADDR[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "FL_ADDR[4]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "FL_ADDR[5]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "FL_ADDR[6]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "FL_ADDR[7]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "FL_ADDR[8]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "FL_ADDR[9]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "FL_CE_N" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "FL_DQ[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "FL_DQ[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "FL_DQ[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "FL_DQ[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "FL_DQ[4]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "FL_DQ[5]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "FL_DQ[6]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "FL_DQ[7]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "FL_OE_N" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "FL_RST_N" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "FL_RY" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "FL_WE_N" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "FL_WP_N" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "GPIO[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "GPIO[10]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "GPIO[11]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "GPIO[12]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "GPIO[13]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "GPIO[14]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "GPIO[15]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "GPIO[16]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "GPIO[17]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "GPIO[18]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "GPIO[19]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "GPIO[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "GPIO[20]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "GPIO[21]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "GPIO[22]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "GPIO[23]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "GPIO[24]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "GPIO[25]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "GPIO[26]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "GPIO[27]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "GPIO[28]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "GPIO[29]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "GPIO[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "GPIO[30]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "GPIO[31]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "GPIO[32]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "GPIO[33]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "GPIO[34]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "GPIO[35]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "GPIO[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "GPIO[4]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "GPIO[5]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "GPIO[6]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "GPIO[7]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "GPIO[8]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "GPIO[9]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX0[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX0[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX0[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX0[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX0[4]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX0[5]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX0[6]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX1[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX1[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX1[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX1[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX1[4]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX1[5]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX1[6]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX2[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX2[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX2[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX2[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX2[4]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX2[5]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX2[6]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX3[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX3[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX3[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX3[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX3[4]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX3[5]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX3[6]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX4[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX4[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX4[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX4[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX4[4]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX4[5]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX4[6]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX5[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX5[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX5[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX5[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX5[4]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX5[5]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX5[6]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX6[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX6[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX6[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX6[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX6[4]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX6[5]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX6[6]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX7[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX7[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX7[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX7[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX7[4]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX7[5]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HEX7[6]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_CLKIN0" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_CLKIN_N1" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_CLKIN_N2" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_CLKIN_P1" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_CLKIN_P2" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_CLKOUT0" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_CLKOUT_N1" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_CLKOUT_N2" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_CLKOUT_P1" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_CLKOUT_P2" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_D[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_D[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_D[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_D[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_RX_D_N[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_RX_D_N[10]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_RX_D_N[11]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_RX_D_N[12]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_RX_D_N[13]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_RX_D_N[14]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_RX_D_N[15]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_RX_D_N[16]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_RX_D_N[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_RX_D_N[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_RX_D_N[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_RX_D_N[4]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_RX_D_N[5]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_RX_D_N[6]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_RX_D_N[7]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_RX_D_N[8]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_RX_D_N[9]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_RX_D_P[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_RX_D_P[10]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_RX_D_P[11]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_RX_D_P[12]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_RX_D_P[13]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_RX_D_P[14]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_RX_D_P[15]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_RX_D_P[16]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_RX_D_P[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_RX_D_P[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_RX_D_P[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_RX_D_P[4]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_RX_D_P[5]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_RX_D_P[6]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_RX_D_P[7]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_RX_D_P[8]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_RX_D_P[9]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_TX_D_N[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_TX_D_N[10]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_TX_D_N[11]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_TX_D_N[12]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_TX_D_N[13]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_TX_D_N[14]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_TX_D_N[15]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_TX_D_N[16]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_TX_D_N[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_TX_D_N[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_TX_D_N[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_TX_D_N[4]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_TX_D_N[5]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_TX_D_N[6]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_TX_D_N[7]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_TX_D_N[8]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_TX_D_N[9]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_TX_D_P[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_TX_D_P[10]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_TX_D_P[11]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_TX_D_P[12]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_TX_D_P[13]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_TX_D_P[14]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_TX_D_P[15]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_TX_D_P[16]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_TX_D_P[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_TX_D_P[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_TX_D_P[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_TX_D_P[4]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_TX_D_P[5]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_TX_D_P[6]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_TX_D_P[7]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_TX_D_P[8]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "HSMC_TX_D_P[9]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "I2C_SCLK" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "I2C_SDAT" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "IRDA_RXD" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "KEY[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "KEY[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "KEY[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LCD_BLON" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LCD_DATA[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LCD_DATA[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LCD_DATA[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LCD_DATA[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LCD_DATA[4]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LCD_DATA[5]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LCD_DATA[6]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LCD_DATA[7]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LCD_EN" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LCD_ON" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LCD_RS" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LCD_RW" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDG[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDG[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDG[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDG[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDG[4]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDG[5]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDG[6]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDG[7]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDG[8]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDR[10]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDR[11]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDR[12]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDR[13]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDR[14]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDR[15]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDR[16]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDR[17]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDR[8]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "LEDR[9]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "OTG_ADDR[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "OTG_ADDR[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "OTG_CS_N" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "OTG_DATA[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "OTG_DATA[10]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "OTG_DATA[11]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "OTG_DATA[12]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "OTG_DATA[13]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "OTG_DATA[14]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "OTG_DATA[15]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "OTG_DATA[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "OTG_DATA[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "OTG_DATA[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "OTG_DATA[4]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "OTG_DATA[5]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "OTG_DATA[6]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "OTG_DATA[7]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "OTG_DATA[8]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "OTG_DATA[9]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "OTG_DREQ[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "OTG_INT" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "OTG_RD_N" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "OTG_RST_N" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "OTG_WR_N" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "PS2_CLK" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "PS2_CLK2" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "PS2_DAT" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "PS2_DAT2" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SD_CLK" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SD_CMD" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SD_DAT[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SD_DAT[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SD_DAT[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SD_DAT[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SD_WP_N" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SMA_CLKIN" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SMA_CLKOUT" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SRAM_ADDR[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SRAM_ADDR[10]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SRAM_ADDR[11]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SRAM_ADDR[12]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SRAM_ADDR[13]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SRAM_ADDR[14]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SRAM_ADDR[15]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SRAM_ADDR[16]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SRAM_ADDR[17]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SRAM_ADDR[18]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SRAM_ADDR[19]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SRAM_ADDR[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SRAM_ADDR[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SRAM_ADDR[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SRAM_ADDR[4]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SRAM_ADDR[5]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SRAM_ADDR[6]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SRAM_ADDR[7]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SRAM_ADDR[8]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SRAM_ADDR[9]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SRAM_CE_N" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SRAM_DQ[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SRAM_DQ[10]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SRAM_DQ[11]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SRAM_DQ[12]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SRAM_DQ[13]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SRAM_DQ[14]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SRAM_DQ[15]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SRAM_DQ[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SRAM_DQ[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SRAM_DQ[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SRAM_DQ[4]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SRAM_DQ[5]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SRAM_DQ[6]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SRAM_DQ[7]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SRAM_DQ[8]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SRAM_DQ[9]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SRAM_LB_N" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SRAM_OE_N" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SRAM_UB_N" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SRAM_WE_N" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SW[10]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SW[11]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SW[12]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SW[13]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SW[14]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SW[15]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SW[16]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SW[17]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "SW[9]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "TD_CLK27" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "TD_DATA[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "TD_DATA[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "TD_DATA[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "TD_DATA[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "TD_DATA[4]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "TD_DATA[5]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "TD_DATA[6]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "TD_DATA[7]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "TD_HS" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "TD_RESET_N" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "TD_VS" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "UART_CTS" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "UART_RTS" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "UART_RXD" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "UART_TXD" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "VGA_BLANK_N" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "VGA_B[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "VGA_B[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "VGA_B[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "VGA_B[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "VGA_B[4]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "VGA_B[5]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "VGA_B[6]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "VGA_B[7]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "VGA_CLK" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "VGA_G[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "VGA_G[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "VGA_G[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "VGA_G[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "VGA_G[4]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "VGA_G[5]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "VGA_G[6]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "VGA_G[7]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "VGA_HS" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "VGA_R[0]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "VGA_R[1]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "VGA_R[2]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "VGA_R[3]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "VGA_R[4]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "VGA_R[5]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "VGA_R[6]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "VGA_R[7]" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "VGA_SYNC_N" is assigned to location or region, but does not exist in design
+ Warning (15706): Node "VGA_VS" is assigned to location or region, but does not exist in design
+Info (171121): Fitter preparation operations ending: elapsed time is 00:00:02
+Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
+Info (170189): Fitter placement preparation operations beginning
+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
+Info (170191): Fitter placement operations beginning
+Info (170137): Fitter placement was successful
+Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
+Info (170193): Fitter routing operations beginning
+Info (170195): Router estimated average interconnect usage is 0% of the available device resources
+ Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X104_Y37 to location X115_Y48
+Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
+ Info (170201): Optimizations that may affect the design's routability were skipped
+ Info (170200): Optimizations that may affect the design's timing were skipped
+Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
+Info (11888): Total time spent on timing analysis during the Fitter is 0.03 seconds.
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:02
+Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
+Info (144001): Generated suppressed messages file /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.fit.smsg
+Info: Quartus Prime Fitter was successful. 0 errors, 507 warnings
+ Info: Peak virtual memory: 1151 megabytes
+ Info: Processing ended: Wed Mar 22 09:19:57 2023
+ Info: Elapsed time: 00:00:17
+ Info: Total CPU time (on all processors): 00:00:24
+
+
++----------------------------+
+; Fitter Suppressed Messages ;
++----------------------------+
+The suppressed messages can be found in /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.fit.smsg.
+
+
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.fit.smsg b/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.fit.smsg
new file mode 100644
index 0000000..7121cbb
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.fit.smsg
@@ -0,0 +1,8 @@
+Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
+Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
+Extra Info (176236): Started Fast Input/Output/OE register processing
+Extra Info (176237): Finished Fast Input/Output/OE register processing
+Extra Info (176238): Start inferring scan chains for DSP blocks
+Extra Info (176239): Inferring scan chains for DSP blocks is complete
+Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
+Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.fit.summary b/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.fit.summary
new file mode 100644
index 0000000..90909a4
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.fit.summary
@@ -0,0 +1,16 @@
+Fitter Status : Successful - Wed Mar 22 09:19:56 2023
+Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+Revision Name : RegisterDemo
+Top-level Entity Name : RegisterDemo
+Family : Cyclone IV E
+Device : EP4CE115F29C7
+Timing Models : Final
+Total logic elements : 8 / 114,480 ( < 1 % )
+ Total combinational functions : 0 / 114,480 ( 0 % )
+ Dedicated logic registers : 8 / 114,480 ( < 1 % )
+Total registers : 8
+Total pins : 18 / 529 ( 3 % )
+Total virtual pins : 0
+Total memory bits : 0 / 3,981,312 ( 0 % )
+Embedded Multiplier 9-bit elements : 0 / 532 ( 0 % )
+Total PLLs : 0 / 4 ( 0 % )
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.flow.rpt b/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.flow.rpt
new file mode 100644
index 0000000..40fc3f4
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.flow.rpt
@@ -0,0 +1,136 @@
+Flow report for RegisterDemo
+Wed Mar 22 09:20:09 2023
+Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Flow Summary
+ 3. Flow Settings
+ 4. Flow Non-Default Global Settings
+ 5. Flow Elapsed Time
+ 6. Flow OS Summary
+ 7. Flow Log
+ 8. Flow Messages
+ 9. Flow Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2020 Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions
+and other software and tools, and any partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Intel Program License
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors. Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+
+
+
++----------------------------------------------------------------------------------+
+; Flow Summary ;
++------------------------------------+---------------------------------------------+
+; Flow Status ; Successful - Wed Mar 22 09:20:09 2023 ;
+; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
+; Revision Name ; RegisterDemo ;
+; Top-level Entity Name ; RegisterDemo ;
+; Family ; Cyclone IV E ;
+; Device ; EP4CE115F29C7 ;
+; Timing Models ; Final ;
+; Total logic elements ; 8 / 114,480 ( < 1 % ) ;
+; Total combinational functions ; 0 / 114,480 ( 0 % ) ;
+; Dedicated logic registers ; 8 / 114,480 ( < 1 % ) ;
+; Total registers ; 8 ;
+; Total pins ; 18 / 529 ( 3 % ) ;
+; Total virtual pins ; 0 ;
+; Total memory bits ; 0 / 3,981,312 ( 0 % ) ;
+; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ;
+; Total PLLs ; 0 / 4 ( 0 % ) ;
++------------------------------------+---------------------------------------------+
+
+
++-----------------------------------------+
+; Flow Settings ;
++-------------------+---------------------+
+; Option ; Setting ;
++-------------------+---------------------+
+; Start date & time ; 03/22/2023 09:19:27 ;
+; Main task ; Compilation ;
+; Revision Name ; RegisterDemo ;
++-------------------+---------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings ;
++-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
+; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
++-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
+; COMPILER_SIGNATURE_ID ; 198516037997543.167947676707173 ; -- ; -- ; -- ;
+; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
+; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
+; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
+; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_symbol ;
+; EDA_OUTPUT_DATA_FORMAT ; Vhdl ; -- ; -- ; eda_simulation ;
+; EDA_SIMULATION_TOOL ; ModelSim-Altera (VHDL) ; ; -- ; -- ;
+; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
+; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
+; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
+; NOMINAL_CORE_SUPPLY_VOLTAGE ; 1.2V ; -- ; -- ; -- ;
+; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
+; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
+; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
+; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ;
+; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ;
+; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
++-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time ;
++----------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++----------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis ; 00:00:12 ; 1.0 ; 429 MB ; 00:00:32 ;
+; Fitter ; 00:00:16 ; 1.0 ; 1151 MB ; 00:00:24 ;
+; Assembler ; 00:00:06 ; 1.0 ; 364 MB ; 00:00:05 ;
+; Timing Analyzer ; 00:00:03 ; 1.0 ; 534 MB ; 00:00:03 ;
+; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 612 MB ; 00:00:01 ;
+; Total ; 00:00:37 ; -- ; -- ; 00:01:05 ;
++----------------------+--------------+-------------------------+---------------------+------------------------------------+
+
+
++----------------------------------------------------------------------------------------+
+; Flow OS Summary ;
++----------------------+------------------+----------------+------------+----------------+
+; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
++----------------------+------------------+----------------+------------+----------------+
+; Analysis & Synthesis ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
+; Fitter ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
+; Assembler ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
+; Timing Analyzer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
+; EDA Netlist Writer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
++----------------------+------------------+----------------+------------+----------------+
+
+
+------------
+; Flow Log ;
+------------
+quartus_map --read_settings_files=on --write_settings_files=off RegisterDemo -c RegisterDemo
+quartus_fit --read_settings_files=off --write_settings_files=off RegisterDemo -c RegisterDemo
+quartus_asm --read_settings_files=off --write_settings_files=off RegisterDemo -c RegisterDemo
+quartus_sta RegisterDemo -c RegisterDemo
+quartus_eda --read_settings_files=off --write_settings_files=off RegisterDemo -c RegisterDemo
+
+
+
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.jdi b/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.jdi
new file mode 100644
index 0000000..bca186f
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.jdi
@@ -0,0 +1,8 @@
+
+
+
+
+
+
+
+
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.map.rpt b/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.map.rpt
new file mode 100644
index 0000000..b78f94c
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.map.rpt
@@ -0,0 +1,286 @@
+Analysis & Synthesis report for RegisterDemo
+Wed Mar 22 09:19:39 2023
+Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Analysis & Synthesis Summary
+ 3. Analysis & Synthesis Settings
+ 4. Parallel Compilation
+ 5. Analysis & Synthesis Source Files Read
+ 6. Analysis & Synthesis Resource Usage Summary
+ 7. Analysis & Synthesis Resource Utilization by Entity
+ 8. General Register Statistics
+ 9. Post-Synthesis Netlist Statistics for Top Partition
+ 10. Elapsed Time Per Partition
+ 11. Analysis & Synthesis Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2020 Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions
+and other software and tools, and any partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Intel Program License
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors. Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+
+
+
++----------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary ;
++------------------------------------+---------------------------------------------+
+; Analysis & Synthesis Status ; Successful - Wed Mar 22 09:19:39 2023 ;
+; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
+; Revision Name ; RegisterDemo ;
+; Top-level Entity Name ; RegisterDemo ;
+; Family ; Cyclone IV E ;
+; Total logic elements ; 8 ;
+; Total combinational functions ; 0 ;
+; Dedicated logic registers ; 8 ;
+; Total registers ; 8 ;
+; Total pins ; 18 ;
+; Total virtual pins ; 0 ;
+; Total memory bits ; 0 ;
+; Embedded Multiplier 9-bit elements ; 0 ;
+; Total PLLs ; 0 ;
++------------------------------------+---------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings ;
++------------------------------------------------------------------+--------------------+--------------------+
+; Option ; Setting ; Default Value ;
++------------------------------------------------------------------+--------------------+--------------------+
+; Device ; EP4CE115F29C7 ; ;
+; Top-level entity name ; RegisterDemo ; RegisterDemo ;
+; Family name ; Cyclone IV E ; Cyclone V ;
+; Use smart compilation ; Off ; Off ;
+; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
+; Enable compact report table ; Off ; Off ;
+; Restructure Multiplexers ; Auto ; Auto ;
+; Create Debugging Nodes for IP Cores ; Off ; Off ;
+; Preserve fewer node names ; On ; On ;
+; Intel FPGA IP Evaluation Mode ; Enable ; Enable ;
+; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
+; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
+; State Machine Processing ; Auto ; Auto ;
+; Safe State Machine ; Off ; Off ;
+; Extract Verilog State Machines ; On ; On ;
+; Extract VHDL State Machines ; On ; On ;
+; Ignore Verilog initial constructs ; Off ; Off ;
+; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
+; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
+; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
+; Infer RAMs from Raw Logic ; On ; On ;
+; Parallel Synthesis ; On ; On ;
+; DSP Block Balancing ; Auto ; Auto ;
+; NOT Gate Push-Back ; On ; On ;
+; Power-Up Don't Care ; On ; On ;
+; Remove Redundant Logic Cells ; Off ; Off ;
+; Remove Duplicate Registers ; On ; On ;
+; Ignore CARRY Buffers ; Off ; Off ;
+; Ignore CASCADE Buffers ; Off ; Off ;
+; Ignore GLOBAL Buffers ; Off ; Off ;
+; Ignore ROW GLOBAL Buffers ; Off ; Off ;
+; Ignore LCELL Buffers ; Off ; Off ;
+; Ignore SOFT Buffers ; On ; On ;
+; Limit AHDL Integers to 32 Bits ; Off ; Off ;
+; Optimization Technique ; Balanced ; Balanced ;
+; Carry Chain Length ; 70 ; 70 ;
+; Auto Carry Chains ; On ; On ;
+; Auto Open-Drain Pins ; On ; On ;
+; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
+; Auto ROM Replacement ; On ; On ;
+; Auto RAM Replacement ; On ; On ;
+; Auto DSP Block Replacement ; On ; On ;
+; Auto Shift Register Replacement ; Auto ; Auto ;
+; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
+; Auto Clock Enable Replacement ; On ; On ;
+; Strict RAM Replacement ; Off ; Off ;
+; Allow Synchronous Control Signals ; On ; On ;
+; Force Use of Synchronous Clear Signals ; Off ; Off ;
+; Auto RAM Block Balancing ; On ; On ;
+; Auto RAM to Logic Cell Conversion ; Off ; Off ;
+; Auto Resource Sharing ; Off ; Off ;
+; Allow Any RAM Size For Recognition ; Off ; Off ;
+; Allow Any ROM Size For Recognition ; Off ; Off ;
+; Allow Any Shift Register Size For Recognition ; Off ; Off ;
+; Use LogicLock Constraints during Resource Balancing ; On ; On ;
+; Ignore translate_off and synthesis_off directives ; Off ; Off ;
+; Timing-Driven Synthesis ; On ; On ;
+; Report Parameter Settings ; On ; On ;
+; Report Source Assignments ; On ; On ;
+; Report Connectivity Checks ; On ; On ;
+; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
+; Synchronization Register Chain Length ; 2 ; 2 ;
+; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
+; HDL message level ; Level2 ; Level2 ;
+; Suppress Register Optimization Related Messages ; Off ; Off ;
+; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
+; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
+; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
+; Clock MUX Protection ; On ; On ;
+; Auto Gated Clock Conversion ; Off ; Off ;
+; Block Design Naming ; Auto ; Auto ;
+; SDC constraint protection ; Off ; Off ;
+; Synthesis Effort ; Auto ; Auto ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
+; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
+; Analysis & Synthesis Message Level ; Medium ; Medium ;
+; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
+; Resource Aware Inference For Block RAM ; On ; On ;
++------------------------------------------------------------------+--------------------+--------------------+
+
+
++------------------------------------------+
+; Parallel Compilation ;
++----------------------------+-------------+
+; Processors ; Number ;
++----------------------------+-------------+
+; Number detected on machine ; 8 ;
+; Maximum allowed ; 4 ;
+; ; ;
+; Average used ; 1.00 ;
+; Maximum used ; 1 ;
+; ; ;
+; Usage by Processor ; % Time Used ;
+; Processor 1 ; 100.0% ;
++----------------------------+-------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read ;
++----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------------------------------+---------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
++----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------------------------------+---------+
+; Register8.vhd ; yes ; User VHDL File ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/Register8.vhd ; ;
+; RegisterDemo.bdf ; yes ; User Block Diagram/Schematic File ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/RegisterDemo.bdf ; ;
++----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------------------------------+---------+
+
+
++------------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary ;
++---------------------------------------------+--------------+
+; Resource ; Usage ;
++---------------------------------------------+--------------+
+; Estimated Total logic elements ; 8 ;
+; ; ;
+; Total combinational functions ; 0 ;
+; Logic element usage by number of LUT inputs ; ;
+; -- 4 input functions ; 0 ;
+; -- 3 input functions ; 0 ;
+; -- <=2 input functions ; 0 ;
+; ; ;
+; Logic elements by mode ; ;
+; -- normal mode ; 0 ;
+; -- arithmetic mode ; 0 ;
+; ; ;
+; Total registers ; 8 ;
+; -- Dedicated logic registers ; 8 ;
+; -- I/O registers ; 0 ;
+; ; ;
+; I/O pins ; 18 ;
+; ; ;
+; Embedded Multiplier 9-bit elements ; 0 ;
+; ; ;
+; Maximum fan-out node ; KEY[0]~input ;
+; Maximum fan-out ; 8 ;
+; Total fan-out ; 50 ;
+; Average fan-out ; 1.14 ;
++---------------------------------------------+--------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity ;
++----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+------------------------------+--------------+--------------+
+; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
++----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+------------------------------+--------------+--------------+
+; |RegisterDemo ; 0 (0) ; 8 (0) ; 0 ; 0 ; 0 ; 0 ; 18 ; 0 ; |RegisterDemo ; RegisterDemo ; work ;
+; |Register8:inst| ; 0 (0) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |RegisterDemo|Register8:inst ; Register8 ; work ;
++----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+------------------------------+--------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++------------------------------------------------------+
+; General Register Statistics ;
++----------------------------------------------+-------+
+; Statistic ; Value ;
++----------------------------------------------+-------+
+; Total registers ; 8 ;
+; Number of registers using Synchronous Clear ; 0 ;
+; Number of registers using Synchronous Load ; 0 ;
+; Number of registers using Asynchronous Clear ; 0 ;
+; Number of registers using Asynchronous Load ; 0 ;
+; Number of registers using Clock Enable ; 8 ;
+; Number of registers using Preset ; 0 ;
++----------------------------------------------+-------+
+
+
++-----------------------------------------------------+
+; Post-Synthesis Netlist Statistics for Top Partition ;
++-------------------+---------------------------------+
+; Type ; Count ;
++-------------------+---------------------------------+
+; boundary_port ; 18 ;
+; cycloneiii_ff ; 8 ;
+; ENA ; 8 ;
+; ; ;
+; Max LUT depth ; 0.00 ;
+; Average LUT depth ; 0.00 ;
++-------------------+---------------------------------+
+
+
++-------------------------------+
+; Elapsed Time Per Partition ;
++----------------+--------------+
+; Partition Name ; Elapsed Time ;
++----------------+--------------+
+; Top ; 00:00:01 ;
++----------------+--------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Analysis & Synthesis
+ Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+ Info: Processing started: Wed Mar 22 09:19:26 2023
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RegisterDemo -c RegisterDemo
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info (12021): Found 2 design units, including 1 entities, in source file Register8.vhd
+ Info (12022): Found design unit 1: Register8-Behavioral File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/Register8.vhd Line: 14
+ Info (12023): Found entity 1: Register8 File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/Register8.vhd Line: 4
+Info (12021): Found 1 design units, including 1 entities, in source file RegisterDemo.bdf
+ Info (12023): Found entity 1: RegisterDemo
+Info (12127): Elaborating entity "RegisterDemo" for the top level hierarchy
+Info (12128): Elaborating entity "Register8" for hierarchy "Register8:inst"
+Info (286030): Timing-Driven Synthesis is running
+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
+ Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
+Info (21057): Implemented 26 device resources after synthesis - the final resource count might be different
+ Info (21058): Implemented 10 input pins
+ Info (21059): Implemented 8 output pins
+ Info (21061): Implemented 8 logic cells
+Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning
+ Info: Peak virtual memory: 429 megabytes
+ Info: Processing ended: Wed Mar 22 09:19:39 2023
+ Info: Elapsed time: 00:00:13
+ Info: Total CPU time (on all processors): 00:00:32
+
+
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.map.summary b/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.map.summary
new file mode 100644
index 0000000..4744268
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.map.summary
@@ -0,0 +1,14 @@
+Analysis & Synthesis Status : Successful - Wed Mar 22 09:19:39 2023
+Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+Revision Name : RegisterDemo
+Top-level Entity Name : RegisterDemo
+Family : Cyclone IV E
+Total logic elements : 8
+ Total combinational functions : 0
+ Dedicated logic registers : 8
+Total registers : 8
+Total pins : 18
+Total virtual pins : 0
+Total memory bits : 0
+Embedded Multiplier 9-bit elements : 0
+Total PLLs : 0
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.pin b/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.pin
new file mode 100644
index 0000000..bb54ae1
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.pin
@@ -0,0 +1,851 @@
+ -- Copyright (C) 2020 Intel Corporation. All rights reserved.
+ -- Your use of Intel Corporation's design tools, logic functions
+ -- and other software and tools, and any partner logic
+ -- functions, and any output files from any of the foregoing
+ -- (including device programming or simulation files), and any
+ -- associated documentation or information are expressly subject
+ -- to the terms and conditions of the Intel Program License
+ -- Subscription Agreement, the Intel Quartus Prime License Agreement,
+ -- the Intel FPGA IP License Agreement, or other applicable license
+ -- agreement, including, without limitation, that your use is for
+ -- the sole purpose of programming logic devices manufactured by
+ -- Intel and sold by Intel or its authorized distributors. Please
+ -- refer to the applicable agreement for further details, at
+ -- https://fpgasoftware.intel.com/eula.
+ --
+ -- This is a Quartus Prime output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus Prime input file. This file cannot be used
+ -- to make Quartus Prime pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus Prime help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC : No Connect. This pin has no internal connection to the device.
+ -- DNU : Do Not Use. This pin MUST NOT be connected.
+ -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
+ -- VCCIO : Dedicated power pin, which MUST be connected to VCC
+ -- of its bank.
+ -- Bank 1: 2.5V
+ -- Bank 2: 2.5V
+ -- Bank 3: 2.5V
+ -- Bank 4: 2.5V
+ -- Bank 5: 2.5V
+ -- Bank 6: 2.5V
+ -- Bank 7: 2.5V
+ -- Bank 8: 2.5V
+ -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ -- It can also be used to report unused dedicated pins. The connection
+ -- on the board for unused dedicated pins depends on whether this will
+ -- be used in a future design. One example is device migration. When
+ -- using device migration, refer to the device pin-tables. If it is a
+ -- GND pin in the pin table or if it will not be used in a future design
+ -- for another purpose the it MUST be connected to GND. If it is an unused
+ -- dedicated pin, then it can be connected to a valid signal on the board
+ -- (low, high, or toggling) if that signal is required for a different
+ -- revision of the design.
+ -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
+ -- This pin should be connected to GND. It may also be connected to a
+ -- valid signal on the board (low, high, or toggling) if that signal
+ -- is required for a different revision of the design.
+ -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
+ -- or leave it unconnected.
+ -- RESERVED : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+CHIP "RegisterDemo" ASSIGNED TO AN: EP4CE115F29C7
+
+Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
+-------------------------------------------------------------------------------------------------------------
+VCCIO8 : A2 : power : : 2.5V : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8 :
+VCCIO8 : A5 : power : : 2.5V : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A7 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A8 : : : : 8 :
+VCCIO8 : A9 : power : : 2.5V : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A12 : : : : 8 :
+VCCIO8 : A13 : power : : 2.5V : 8 :
+GND+ : A14 : : : : 8 :
+GND+ : A15 : : : : 7 :
+VCCIO7 : A16 : power : : 2.5V : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A17 : : : : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7 :
+VCCIO7 : A20 : power : : 2.5V : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A21 : : : : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A22 : : : : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A23 : : : : 7 :
+VCCIO7 : A24 : power : : 2.5V : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A25 : : : : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : A26 : : : : 7 :
+VCCIO7 : A27 : power : : 2.5V : 7 :
+VCCIO2 : AA1 : power : : 2.5V : 2 :
+GND : AA2 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA3 : : : : 2 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA4 : : : : 2 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA5 : : : : 2 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA6 : : : : 2 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA7 : : : : 2 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA8 : : : : 3 :
+GNDA1 : AA9 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA10 : : : : 3 :
+VCCIO3 : AA11 : power : : 2.5V : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA12 : : : : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA13 : : : : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA14 : : : : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA15 : : : : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA17 : : : : 4 :
+VCCIO4 : AA18 : power : : 2.5V : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA19 : : : : 4 :
+GNDA4 : AA20 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA22 : : : : 5 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA23 : : : : 5 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA24 : : : : 5 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA25 : : : : 5 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AA26 : : : : 5 :
+GND : AA27 : gnd : : : :
+VCCIO5 : AA28 : power : : 2.5V : 5 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB1 : : : : 2 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB2 : : : : 2 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB3 : : : : 2 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB4 : : : : 2 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB5 : : : : 2 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB6 : : : : 2 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB7 : : : : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB8 : : : : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB9 : : : : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB10 : : : : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB11 : : : : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB13 : : : : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB14 : : : : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB16 : : : : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB17 : : : : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB18 : : : : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB19 : : : : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB20 : : : : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB21 : : : : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB22 : : : : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB23 : : : : 5 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB24 : : : : 5 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AB25 : : : : 5 :
+SW[7] : AB26 : input : 2.5 V : : 5 : Y
+SW[4] : AB27 : input : 2.5 V : : 5 : Y
+SW[0] : AB28 : input : 2.5 V : : 5 : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC1 : : : : 2 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC2 : : : : 2 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC3 : : : : 2 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC4 : : : : 2 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC5 : : : : 2 :
+GND : AC6 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC7 : : : : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC8 : : : : 3 :
+GND : AC9 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC10 : : : : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC11 : : : : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC12 : : : : 3 :
+GND : AC13 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC14 : : : : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC15 : : : : 4 :
+GND : AC16 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC17 : : : : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC18 : : : : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC19 : : : : 4 :
+GND : AC20 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC21 : : : : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC22 : : : : 4 :
+GND : AC23 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AC24 : : : : 5 :
+SW[8] : AC25 : input : 2.5 V : : 5 : Y
+SW[5] : AC26 : input : 2.5 V : : 5 : Y
+SW[2] : AC27 : input : 2.5 V : : 5 : Y
+SW[1] : AC28 : input : 2.5 V : : 5 : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD1 : : : : 2 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD2 : : : : 2 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD3 : : : : 2 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD4 : : : : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD5 : : : : 3 :
+VCCIO3 : AD6 : power : : 2.5V : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD7 : : : : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD8 : : : : 3 :
+VCCIO3 : AD9 : power : : 2.5V : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD10 : : : : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD11 : : : : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD12 : : : : 3 :
+VCCIO3 : AD13 : power : : 2.5V : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD14 : : : : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD15 : : : : 4 :
+VCCIO4 : AD16 : power : : 2.5V : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD17 : : : : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD18 : : : : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD19 : : : : 4 :
+VCCIO4 : AD20 : power : : 2.5V : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD21 : : : : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD22 : : : : 4 :
+VCCIO4 : AD23 : power : : 2.5V : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD24 : : : : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD25 : : : : 4 :
+SW[6] : AD26 : input : 2.5 V : : 5 : Y
+SW[3] : AD27 : input : 2.5 V : : 5 : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : AD28 : : : : 5 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE1 : : : : 2 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE2 : : : : 2 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE3 : : : : 2 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE4 : : : : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE5 : : : : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE6 : : : : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE7 : : : : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE8 : : : : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE9 : : : : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE10 : : : : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE11 : : : : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE12 : : : : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE13 : : : : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE14 : : : : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE15 : : : : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE16 : : : : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE17 : : : : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE18 : : : : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE19 : : : : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE20 : : : : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE21 : : : : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE22 : : : : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE23 : : : : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE24 : : : : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE25 : : : : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE26 : : : : 5 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE27 : : : : 5 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AE28 : : : : 5 :
+GND : AF1 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF2 : : : : 2 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF3 : : : : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF4 : : : : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF5 : : : : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF6 : : : : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF7 : : : : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF8 : : : : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF9 : : : : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF10 : : : : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF11 : : : : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF12 : : : : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF13 : : : : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF14 : : : : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF15 : : : : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF16 : : : : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF17 : : : : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF18 : : : : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF19 : : : : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF20 : : : : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF21 : : : : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF22 : : : : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF23 : : : : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF24 : : : : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF25 : : : : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF26 : : : : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AF27 : : : : 5 :
+GND : AF28 : gnd : : : :
+VCCIO2 : AG1 : power : : 2.5V : 2 :
+GND : AG2 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG3 : : : : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG4 : : : : 3 :
+GND : AG5 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG6 : : : : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG7 : : : : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG8 : : : : 3 :
+GND : AG9 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG10 : : : : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG11 : : : : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG12 : : : : 3 :
+GND : AG13 : gnd : : : :
+GND+ : AG14 : : : : 3 :
+GND+ : AG15 : : : : 4 :
+GND : AG16 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG17 : : : : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG18 : : : : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG19 : : : : 4 :
+GND : AG20 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG21 : : : : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG22 : : : : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG23 : : : : 4 :
+GND : AG24 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG25 : : : : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AG26 : : : : 4 :
+GND : AG27 : gnd : : : :
+VCCIO5 : AG28 : power : : 2.5V : 5 :
+VCCIO3 : AH2 : power : : 2.5V : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH3 : : : : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH4 : : : : 3 :
+VCCIO3 : AH5 : power : : 2.5V : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH6 : : : : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH7 : : : : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH8 : : : : 3 :
+VCCIO3 : AH9 : power : : 2.5V : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH10 : : : : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH11 : : : : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH12 : : : : 3 :
+VCCIO3 : AH13 : power : : 2.5V : 3 :
+GND+ : AH14 : : : : 3 :
+GND+ : AH15 : : : : 4 :
+VCCIO4 : AH16 : power : : 2.5V : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH17 : : : : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH18 : : : : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH19 : : : : 4 :
+VCCIO4 : AH20 : power : : 2.5V : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH21 : : : : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH22 : : : : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH23 : : : : 4 :
+VCCIO4 : AH24 : power : : 2.5V : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH25 : : : : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : AH26 : : : : 4 :
+VCCIO4 : AH27 : power : : 2.5V : 4 :
+VCCIO1 : B1 : power : : 2.5V : 1 :
+GND : B2 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 :
+GND : B5 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B7 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 8 :
+GND : B9 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 8 :
+GND : B12 : gnd : : : :
+GND : B13 : gnd : : : :
+GND+ : B14 : : : : 8 :
+GND+ : B15 : : : : 7 :
+GND : B16 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B17 : : : : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B18 : : : : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B19 : : : : 7 :
+GND : B20 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B23 : : : : 7 :
+GND : B24 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B25 : : : : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : B26 : : : : 7 :
+GND : B27 : gnd : : : :
+VCCIO6 : B28 : power : : 2.5V : 6 :
+GND : C1 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 1 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C5 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C6 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C10 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C11 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C12 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C16 : : : : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C17 : : : : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C18 : : : : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C21 : : : : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C23 : : : : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C24 : : : : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C25 : : : : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C26 : : : : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : C27 : : : : 6 :
+GND : C28 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : : : : 1 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : : : : 1 :
+GND : D3 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D4 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D8 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D9 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D10 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D11 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D13 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D16 : : : : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D17 : : : : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D18 : : : : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D19 : : : : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D20 : : : : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D23 : : : : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D24 : : : : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D25 : : : : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D26 : : : : 6 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D27 : : : : 6 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : D28 : : : : 6 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E1 : : : : 1 :
+~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : E2 : input : 2.5 V : : 1 : N
+RESERVED_INPUT_WITH_WEAK_PULLUP : E3 : : : : 1 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E4 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E5 : : : : 8 :
+VCCIO8 : E6 : power : : 2.5V : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E7 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8 :
+VCCIO8 : E9 : power : : 2.5V : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E10 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E12 : : : : 8 :
+VCCIO8 : E13 : power : : 2.5V : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E14 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E15 : : : : 7 :
+VCCIO7 : E16 : power : : 2.5V : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E17 : : : : 7 :
+LEDR[5] : E18 : output : 2.5 V : : 7 : Y
+LEDR[2] : E19 : output : 2.5 V : : 7 : Y
+VCCIO7 : E20 : power : : 2.5V : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E21 : : : : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E22 : : : : 7 :
+VCCIO7 : E23 : power : : 2.5V : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E24 : : : : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E25 : : : : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E26 : : : : 6 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E27 : : : : 6 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : E28 : : : : 6 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F1 : : : : 1 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F2 : : : : 1 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F3 : : : : 1 :
+~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : F4 : input : 2.5 V : : 1 : N
+RESERVED_INPUT_WITH_WEAK_PULLUP : F5 : : : : 1 :
+GND : F6 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F7 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F8 : : : : 8 :
+GND : F9 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F10 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F11 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F12 : : : : 8 :
+GND : F13 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F14 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 7 :
+GND : F16 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F17 : : : : 7 :
+LEDR[4] : F18 : output : 2.5 V : : 7 : Y
+LEDR[1] : F19 : output : 2.5 V : : 7 : Y
+GND : F20 : gnd : : : :
+LEDR[3] : F21 : output : 2.5 V : : 7 : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : F22 : : : : 7 :
+GND : F23 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F24 : : : : 6 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F25 : : : : 6 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F26 : : : : 6 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F27 : : : : 6 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : F28 : : : : 6 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G1 : : : : 1 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G2 : : : : 1 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G3 : : : : 1 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G4 : : : : 1 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G5 : : : : 1 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G6 : : : : 1 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G7 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G8 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G9 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G10 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G11 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G12 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G13 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G14 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G15 : : : : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G16 : : : : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G17 : : : : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G18 : : : : 7 :
+LEDR[0] : G19 : output : 2.5 V : : 7 : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : G20 : : : : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G21 : : : : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G22 : : : : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G23 : : : : 6 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G24 : : : : 6 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G25 : : : : 6 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G26 : : : : 6 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G27 : : : : 6 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : G28 : : : : 6 :
+VCCIO1 : H1 : power : : 2.5V : 1 :
+GND : H2 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H3 : : : : 1 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H4 : : : : 1 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H5 : : : : 1 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H6 : : : : 1 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H7 : : : : 1 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H8 : : : : 8 :
+GNDA3 : H9 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H10 : : : : 8 :
+VCCIO8 : H11 : power : : 2.5V : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H12 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H15 : : : : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H16 : : : : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 7 :
+VCCIO7 : H18 : power : : 2.5V : 7 :
+LEDR[7] : H19 : output : 2.5 V : : 7 : Y
+GNDA2 : H20 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H21 : : : : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H22 : : : : 6 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H23 : : : : 6 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H24 : : : : 6 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H25 : : : : 6 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : H26 : : : : 6 :
+GND : H27 : gnd : : : :
+VCCIO6 : H28 : power : : 2.5V : 6 :
+GND+ : J1 : : : : 1 :
+GND : J2 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J3 : : : : 1 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J4 : : : : 1 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J5 : : : : 1 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J6 : : : : 1 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J7 : : : : 1 :
+VCCA3 : J8 : power : : 2.5V : :
+VCCD_PLL3 : J9 : power : : 1.2V : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J10 : : : : 8 :
+GND : J11 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J13 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J14 : : : : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J15 : : : : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J16 : : : : 7 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J17 : : : : 7 :
+GND : J18 : gnd : : : :
+LEDR[6] : J19 : output : 2.5 V : : 7 : Y
+VCCD_PLL2 : J20 : power : : 1.2V : :
+VCCA2 : J21 : power : : 2.5V : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J22 : : : : 6 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J23 : : : : 6 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J24 : : : : 6 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J25 : : : : 6 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : J26 : : : : 6 :
+GND+ : J27 : : : : 6 :
+GND+ : J28 : : : : 6 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K1 : : : : 1 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K2 : : : : 1 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K3 : : : : 1 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K4 : : : : 1 :
+VCCIO1 : K5 : power : : 2.5V : 1 :
+GND : K6 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K7 : : : : 1 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 1 :
+VCCINT : K9 : power : : 1.2V : :
+GND : K10 : gnd : : : :
+VCCINT : K11 : power : : 1.2V : :
+GND : K12 : gnd : : : :
+VCCINT : K13 : power : : 1.2V : :
+GND : K14 : gnd : : : :
+VCCINT : K15 : power : : 1.2V : :
+GND : K16 : gnd : : : :
+VCCINT : K17 : power : : 1.2V : :
+GND : K18 : gnd : : : :
+VCCINT : K19 : power : : 1.2V : :
+GND : K20 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K22 : : : : 6 :
+GND : K23 : gnd : : : :
+VCCIO6 : K24 : power : : 2.5V : 6 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K25 : : : : 6 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K26 : : : : 6 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K27 : : : : 6 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : K28 : : : : 6 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L1 : : : : 1 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L2 : : : : 1 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L3 : : : : 1 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L4 : : : : 1 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L5 : : : : 1 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L6 : : : : 1 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L7 : : : : 1 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L8 : : : : 1 :
+GND : L9 : gnd : : : :
+VCCINT : L10 : power : : 1.2V : :
+GND : L11 : gnd : : : :
+VCCINT : L12 : power : : 1.2V : :
+GND : L13 : gnd : : : :
+VCCINT : L14 : power : : 1.2V : :
+GND : L15 : gnd : : : :
+VCCINT : L16 : power : : 1.2V : :
+GND : L17 : gnd : : : :
+VCCINT : L18 : power : : 1.2V : :
+GND : L19 : gnd : : : :
+VCCINT : L20 : power : : 1.2V : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L21 : : : : 6 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L22 : : : : 6 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L23 : : : : 6 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L24 : : : : 6 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L25 : : : : 6 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L26 : : : : 6 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L27 : : : : 6 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : L28 : : : : 6 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M1 : : : : 1 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M2 : : : : 1 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M3 : : : : 1 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M4 : : : : 1 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M5 : : : : 1 :
+nSTATUS : M6 : : : : 1 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M7 : : : : 1 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M8 : : : : 1 :
+VCCINT : M9 : power : : 1.2V : :
+GND : M10 : gnd : : : :
+VCCINT : M11 : power : : 1.2V : :
+GND : M12 : gnd : : : :
+VCCINT : M13 : power : : 1.2V : :
+GND : M14 : gnd : : : :
+VCCINT : M15 : power : : 1.2V : :
+GND : M16 : gnd : : : :
+VCCINT : M17 : power : : 1.2V : :
+GND : M18 : gnd : : : :
+VCCINT : M19 : power : : 1.2V : :
+GND : M20 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M21 : : : : 6 :
+MSEL2 : M22 : : : : 6 :
+KEY[0] : M23 : input : 2.5 V : : 6 : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : M24 : : : : 6 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M25 : : : : 6 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M26 : : : : 6 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M27 : : : : 6 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : M28 : : : : 6 :
+VCCIO1 : N1 : power : : 2.5V : 1 :
+GND : N2 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N3 : : : : 1 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N4 : : : : 1 :
+VCCIO1 : N5 : power : : 2.5V : 1 :
+GND : N6 : gnd : : : :
+~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : N7 : input : 2.5 V : : 1 : N
+RESERVED_INPUT_WITH_WEAK_PULLUP : N8 : : : : 1 :
+GND : N9 : gnd : : : :
+VCCINT : N10 : power : : 1.2V : :
+GND : N11 : gnd : : : :
+VCCINT : N12 : power : : 1.2V : :
+GND : N13 : gnd : : : :
+VCCINT : N14 : power : : 1.2V : :
+GND : N15 : gnd : : : :
+VCCINT : N16 : power : : 1.2V : :
+GND : N17 : gnd : : : :
+VCCINT : N18 : power : : 1.2V : :
+GND : N19 : gnd : : : :
+VCCINT : N20 : power : : 1.2V : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N21 : : : : 6 :
+MSEL0 : N22 : : : : 6 :
+GND : N23 : gnd : : : :
+VCCIO6 : N24 : power : : 2.5V : 6 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N25 : : : : 6 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : N26 : : : : 6 :
+GND : N27 : gnd : : : :
+VCCIO6 : N28 : power : : 2.5V : 6 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : P1 : : : : 1 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : P2 : : : : 1 :
+~ALTERA_DCLK~ : P3 : output : 2.5 V : : 1 : N
+nCONFIG : P4 : : : : 1 :
+TCK : P5 : input : : : 1 :
+TDO : P6 : output : : : 1 :
+TDI : P7 : input : : : 1 :
+TMS : P8 : input : : : 1 :
+VCCINT : P9 : power : : 1.2V : :
+GND : P10 : gnd : : : :
+VCCINT : P11 : power : : 1.2V : :
+GND : P12 : gnd : : : :
+VCCINT : P13 : power : : 1.2V : :
+GND : P14 : gnd : : : :
+VCCINT : P15 : power : : 1.2V : :
+GND : P16 : gnd : : : :
+VCCINT : P17 : power : : 1.2V : :
+GND : P18 : gnd : : : :
+VCCINT : P19 : power : : 1.2V : :
+GND : P20 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : P21 : : : : 5 :
+MSEL3 : P22 : : : : 6 :
+MSEL1 : P23 : : : : 6 :
+CONF_DONE : P24 : : : : 6 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : P25 : : : : 6 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : P26 : : : : 6 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : P27 : : : : 6 :
+~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : P28 : output : 2.5 V : : 6 : N
+RESERVED_INPUT_WITH_WEAK_PULLUP : R1 : : : : 2 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R2 : : : : 2 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R3 : : : : 2 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R4 : : : : 2 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R5 : : : : 2 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R6 : : : : 2 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R7 : : : : 2 :
+nCE : R8 : : : : 1 :
+GND : R9 : gnd : : : :
+VCCINT : R10 : power : : 1.2V : :
+GND : R11 : gnd : : : :
+VCCINT : R12 : power : : 1.2V : :
+GND : R13 : gnd : : : :
+VCCINT : R14 : power : : 1.2V : :
+GND : R15 : gnd : : : :
+VCCINT : R16 : power : : 1.2V : :
+GND : R17 : gnd : : : :
+VCCINT : R18 : power : : 1.2V : :
+GND : R19 : gnd : : : :
+VCCINT : R20 : power : : 1.2V : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R21 : : : : 5 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R22 : : : : 5 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R23 : : : : 5 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R24 : : : : 5 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R25 : : : : 5 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R26 : : : : 5 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R27 : : : : 5 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : R28 : : : : 5 :
+VCCIO2 : T1 : power : : 2.5V : 2 :
+GND : T2 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T3 : : : : 2 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T4 : : : : 2 :
+VCCIO2 : T5 : power : : 2.5V : 2 :
+GND : T6 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T7 : : : : 2 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T8 : : : : 2 :
+VCCINT : T9 : power : : 1.2V : :
+GND : T10 : gnd : : : :
+VCCINT : T11 : power : : 1.2V : :
+GND : T12 : gnd : : : :
+VCCINT : T13 : power : : 1.2V : :
+GND : T14 : gnd : : : :
+VCCINT : T15 : power : : 1.2V : :
+GND : T16 : gnd : : : :
+VCCINT : T17 : power : : 1.2V : :
+GND : T18 : gnd : : : :
+VCCINT : T19 : power : : 1.2V : :
+GND : T20 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T21 : : : : 5 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T22 : : : : 5 :
+GND : T23 : gnd : : : :
+VCCIO5 : T24 : power : : 2.5V : 5 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T25 : : : : 5 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : T26 : : : : 5 :
+GND : T27 : gnd : : : :
+VCCIO5 : T28 : power : : 2.5V : 5 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U1 : : : : 2 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U2 : : : : 2 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U3 : : : : 2 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U4 : : : : 2 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U5 : : : : 2 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U6 : : : : 2 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 2 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U8 : : : : 2 :
+GND : U9 : gnd : : : :
+VCCINT : U10 : power : : 1.2V : :
+GND : U11 : gnd : : : :
+VCCINT : U12 : power : : 1.2V : :
+GND : U13 : gnd : : : :
+VCCINT : U14 : power : : 1.2V : :
+GND : U15 : gnd : : : :
+VCCINT : U16 : power : : 1.2V : :
+GND : U17 : gnd : : : :
+VCCINT : U18 : power : : 1.2V : :
+GND : U19 : gnd : : : :
+VCCINT : U20 : power : : 1.2V : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U21 : : : : 5 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U22 : : : : 5 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U23 : : : : 5 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U24 : : : : 5 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U25 : : : : 5 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U26 : : : : 5 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U27 : : : : 5 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : U28 : : : : 5 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V1 : : : : 2 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V2 : : : : 2 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V3 : : : : 2 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V4 : : : : 2 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V5 : : : : 2 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V6 : : : : 2 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V7 : : : : 2 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V8 : : : : 2 :
+VCCINT : V9 : power : : 1.2V : :
+GND : V10 : gnd : : : :
+VCCINT : V11 : power : : 1.2V : :
+GND : V12 : gnd : : : :
+VCCINT : V13 : power : : 1.2V : :
+GND : V14 : gnd : : : :
+VCCINT : V15 : power : : 1.2V : :
+GND : V16 : gnd : : : :
+VCCINT : V17 : power : : 1.2V : :
+GND : V18 : gnd : : : :
+VCCINT : V19 : power : : 1.2V : :
+GND : V20 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V21 : : : : 5 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 5 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V23 : : : : 5 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V24 : : : : 5 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V25 : : : : 5 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V26 : : : : 5 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V27 : : : : 5 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : V28 : : : : 5 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W1 : : : : 2 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W2 : : : : 2 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W3 : : : : 2 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W4 : : : : 2 :
+VCCIO2 : W5 : power : : 2.5V : 2 :
+GND : W6 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W7 : : : : 2 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W8 : : : : 2 :
+GND : W9 : gnd : : : :
+VCCINT : W10 : power : : 1.2V : :
+GND : W11 : gnd : : : :
+VCCINT : W12 : power : : 1.2V : :
+GND : W13 : gnd : : : :
+VCCINT : W14 : power : : 1.2V : :
+GND : W15 : gnd : : : :
+VCCINT : W16 : power : : 1.2V : :
+GND : W17 : gnd : : : :
+VCCINT : W18 : power : : 1.2V : :
+GND : W19 : gnd : : : :
+VCCINT : W20 : power : : 1.2V : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W21 : : : : 5 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W22 : : : : 5 :
+GND : W23 : gnd : : : :
+VCCIO5 : W24 : power : : 2.5V : 5 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W25 : : : : 5 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W26 : : : : 5 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W27 : : : : 5 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : W28 : : : : 5 :
+GND+ : Y1 : : : : 2 :
+GND+ : Y2 : : : : 2 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y3 : : : : 2 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y4 : : : : 2 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y5 : : : : 2 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y6 : : : : 2 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y7 : : : : 2 :
+VCCA1 : Y8 : power : : 2.5V : :
+VCCD_PLL1 : Y9 : power : : 1.2V : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y10 : : : : 3 :
+GND : Y11 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y12 : : : : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y13 : : : : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y14 : : : : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y15 : : : : 3 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y16 : : : : 4 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y17 : : : : 4 :
+GND : Y18 : gnd : : : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y19 : : : : 4 :
+VCCD_PLL4 : Y20 : power : : 1.2V : :
+VCCA4 : Y21 : power : : 2.5V : :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y22 : : : : 5 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y23 : : : : 5 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y24 : : : : 5 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y25 : : : : 5 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : Y26 : : : : 5 :
+GND+ : Y27 : : : : 5 :
+GND+ : Y28 : : : : 5 :
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.sld b/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.sld
new file mode 100644
index 0000000..f7d3ed7
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.sld
@@ -0,0 +1 @@
+
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.sof b/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.sof
new file mode 100644
index 0000000..e66135f
Binary files /dev/null and b/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.sof differ
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.sta.rpt b/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.sta.rpt
new file mode 100644
index 0000000..4634ce2
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.sta.rpt
@@ -0,0 +1,527 @@
+Timing Analyzer report for RegisterDemo
+Wed Mar 22 09:20:08 2023
+Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Timing Analyzer Summary
+ 3. Parallel Compilation
+ 4. Clocks
+ 5. Slow 1200mV 85C Model Fmax Summary
+ 6. Timing Closure Recommendations
+ 7. Slow 1200mV 85C Model Setup Summary
+ 8. Slow 1200mV 85C Model Hold Summary
+ 9. Slow 1200mV 85C Model Recovery Summary
+ 10. Slow 1200mV 85C Model Removal Summary
+ 11. Slow 1200mV 85C Model Minimum Pulse Width Summary
+ 12. Slow 1200mV 85C Model Metastability Summary
+ 13. Slow 1200mV 0C Model Fmax Summary
+ 14. Slow 1200mV 0C Model Setup Summary
+ 15. Slow 1200mV 0C Model Hold Summary
+ 16. Slow 1200mV 0C Model Recovery Summary
+ 17. Slow 1200mV 0C Model Removal Summary
+ 18. Slow 1200mV 0C Model Minimum Pulse Width Summary
+ 19. Slow 1200mV 0C Model Metastability Summary
+ 20. Fast 1200mV 0C Model Setup Summary
+ 21. Fast 1200mV 0C Model Hold Summary
+ 22. Fast 1200mV 0C Model Recovery Summary
+ 23. Fast 1200mV 0C Model Removal Summary
+ 24. Fast 1200mV 0C Model Minimum Pulse Width Summary
+ 25. Fast 1200mV 0C Model Metastability Summary
+ 26. Multicorner Timing Analysis Summary
+ 27. Board Trace Model Assignments
+ 28. Input Transition Times
+ 29. Signal Integrity Metrics (Slow 1200mv 0c Model)
+ 30. Signal Integrity Metrics (Slow 1200mv 85c Model)
+ 31. Signal Integrity Metrics (Fast 1200mv 0c Model)
+ 32. Clock Transfers
+ 33. Report TCCS
+ 34. Report RSKM
+ 35. Unconstrained Paths Summary
+ 36. Clock Status Summary
+ 37. Unconstrained Input Ports
+ 38. Unconstrained Output Ports
+ 39. Unconstrained Input Ports
+ 40. Unconstrained Output Ports
+ 41. Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2020 Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions
+and other software and tools, and any partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Intel Program License
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors. Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+
+
+
++-----------------------------------------------------------------------------+
+; Timing Analyzer Summary ;
++-----------------------+-----------------------------------------------------+
+; Quartus Prime Version ; Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
+; Timing Analyzer ; Legacy Timing Analyzer ;
+; Revision Name ; RegisterDemo ;
+; Device Family ; Cyclone IV E ;
+; Device Name ; EP4CE115F29C7 ;
+; Timing Models ; Final ;
+; Delay Model ; Combined ;
+; Rise/Fall Delays ; Enabled ;
++-----------------------+-----------------------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation ;
++----------------------------+-------------+
+; Processors ; Number ;
++----------------------------+-------------+
+; Number detected on machine ; 8 ;
+; Maximum allowed ; 4 ;
+; ; ;
+; Average used ; 1.01 ;
+; Maximum used ; 4 ;
+; ; ;
+; Usage by Processor ; % Time Used ;
+; Processor 1 ; 100.0% ;
+; Processors 2-4 ; 0.2% ;
++----------------------------+-------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clocks ;
++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+------------+
+; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+------------+
+; KEY[0] ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { KEY[0] } ;
++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+------------+
+
+
+--------------------------------------
+; Slow 1200mV 85C Model Fmax Summary ;
+--------------------------------------
+No paths to report.
+
+
+----------------------------------
+; Timing Closure Recommendations ;
+----------------------------------
+HTML report is unavailable in plain text report export.
+
+
+---------------------------------------
+; Slow 1200mV 85C Model Setup Summary ;
+---------------------------------------
+No paths to report.
+
+
+--------------------------------------
+; Slow 1200mV 85C Model Hold Summary ;
+--------------------------------------
+No paths to report.
+
+
+------------------------------------------
+; Slow 1200mV 85C Model Recovery Summary ;
+------------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Slow 1200mV 85C Model Removal Summary ;
+-----------------------------------------
+No paths to report.
+
+
++---------------------------------------------------+
+; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
++--------+--------+---------------------------------+
+; Clock ; Slack ; End Point TNS ;
++--------+--------+---------------------------------+
+; KEY[0] ; -3.000 ; -13.280 ;
++--------+--------+---------------------------------+
+
+
+-----------------------------------------------
+; Slow 1200mV 85C Model Metastability Summary ;
+-----------------------------------------------
+No synchronizer chains to report.
+
+
+-------------------------------------
+; Slow 1200mV 0C Model Fmax Summary ;
+-------------------------------------
+No paths to report.
+
+
+--------------------------------------
+; Slow 1200mV 0C Model Setup Summary ;
+--------------------------------------
+No paths to report.
+
+
+-------------------------------------
+; Slow 1200mV 0C Model Hold Summary ;
+-------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Slow 1200mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Slow 1200mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
++--------------------------------------------------+
+; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
++--------+--------+--------------------------------+
+; Clock ; Slack ; End Point TNS ;
++--------+--------+--------------------------------+
+; KEY[0] ; -3.000 ; -13.280 ;
++--------+--------+--------------------------------+
+
+
+----------------------------------------------
+; Slow 1200mV 0C Model Metastability Summary ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
+--------------------------------------
+; Fast 1200mV 0C Model Setup Summary ;
+--------------------------------------
+No paths to report.
+
+
+-------------------------------------
+; Fast 1200mV 0C Model Hold Summary ;
+-------------------------------------
+No paths to report.
+
+
+-----------------------------------------
+; Fast 1200mV 0C Model Recovery Summary ;
+-----------------------------------------
+No paths to report.
+
+
+----------------------------------------
+; Fast 1200mV 0C Model Removal Summary ;
+----------------------------------------
+No paths to report.
+
+
++--------------------------------------------------+
+; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
++--------+--------+--------------------------------+
+; Clock ; Slack ; End Point TNS ;
++--------+--------+--------------------------------+
+; KEY[0] ; -3.000 ; -11.696 ;
++--------+--------+--------------------------------+
+
+
+----------------------------------------------
+; Fast 1200mV 0C Model Metastability Summary ;
+----------------------------------------------
+No synchronizer chains to report.
+
+
++----------------------------------------------------------------------------+
+; Multicorner Timing Analysis Summary ;
++------------------+-------+------+----------+---------+---------------------+
+; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
++------------------+-------+------+----------+---------+---------------------+
+; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; -3.000 ;
+; KEY[0] ; N/A ; N/A ; N/A ; N/A ; -3.000 ;
+; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; -13.28 ;
+; KEY[0] ; N/A ; N/A ; N/A ; N/A ; -13.280 ;
++------------------+-------+------+----------+---------+---------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Board Trace Model Assignments ;
++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+; LEDR[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; LEDR[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; LEDR[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; LEDR[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; LEDR[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; LEDR[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; LEDR[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; LEDR[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; ~ALTERA_DCLK~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
+; ~ALTERA_nCEO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
+
+
++----------------------------------------------------------------------------+
+; Input Transition Times ;
++-------------------------+--------------+-----------------+-----------------+
+; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
++-------------------------+--------------+-----------------+-----------------+
+; SW[7] ; 2.5 V ; 2000 ps ; 2000 ps ;
+; KEY[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
+; SW[8] ; 2.5 V ; 2000 ps ; 2000 ps ;
+; SW[6] ; 2.5 V ; 2000 ps ; 2000 ps ;
+; SW[5] ; 2.5 V ; 2000 ps ; 2000 ps ;
+; SW[4] ; 2.5 V ; 2000 ps ; 2000 ps ;
+; SW[3] ; 2.5 V ; 2000 ps ; 2000 ps ;
+; SW[2] ; 2.5 V ; 2000 ps ; 2000 ps ;
+; SW[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
+; SW[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
+; ~ALTERA_ASDO_DATA1~ ; 2.5 V ; 2000 ps ; 2000 ps ;
+; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V ; 2000 ps ; 2000 ps ;
+; ~ALTERA_DATA0~ ; 2.5 V ; 2000 ps ; 2000 ps ;
++-------------------------+--------------+-----------------+-----------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Slow 1200mv 0c Model) ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; LEDR[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
+; LEDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
+; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
+; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
+; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
+; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
+; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
+; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ; 2.32 V ; 4.49e-09 V ; 2.38 V ; -0.00552 V ; 0.096 V ; 0.019 V ; 4.18e-10 s ; 3.59e-10 s ; No ; Yes ;
+; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.67e-09 V ; 2.38 V ; -0.0485 V ; 0.167 V ; 0.096 V ; 2.95e-10 s ; 2.73e-10 s ; Yes ; Yes ; 2.32 V ; 2.67e-09 V ; 2.38 V ; -0.0485 V ; 0.167 V ; 0.096 V ; 2.95e-10 s ; 2.73e-10 s ; Yes ; Yes ;
+; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.18e-09 V ; 2.38 V ; -0.00483 V ; 0.152 V ; 0.012 V ; 4.81e-10 s ; 6.29e-10 s ; Yes ; Yes ; 2.32 V ; 4.18e-09 V ; 2.38 V ; -0.00483 V ; 0.152 V ; 0.012 V ; 4.81e-10 s ; 6.29e-10 s ; Yes ; Yes ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Slow 1200mv 85c Model) ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; LEDR[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
+; LEDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
+; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
+; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
+; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
+; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
+; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
+; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ; 2.32 V ; 6.92e-07 V ; 2.35 V ; -0.00996 V ; 0.121 V ; 0.03 V ; 4.64e-10 s ; 4.47e-10 s ; Yes ; Yes ;
+; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.75e-07 V ; 2.35 V ; -0.0109 V ; 0.084 V ; 0.027 V ; 4.31e-10 s ; 3.61e-10 s ; Yes ; Yes ; 2.32 V ; 3.75e-07 V ; 2.35 V ; -0.0109 V ; 0.084 V ; 0.027 V ; 4.31e-10 s ; 3.61e-10 s ; Yes ; Yes ;
+; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.15e-07 V ; 2.35 V ; -0.00712 V ; 0.093 V ; 0.02 V ; 6.21e-10 s ; 7.9e-10 s ; Yes ; Yes ; 2.32 V ; 6.15e-07 V ; 2.35 V ; -0.00712 V ; 0.093 V ; 0.02 V ; 6.21e-10 s ; 7.9e-10 s ; Yes ; Yes ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Signal Integrity Metrics (Fast 1200mv 0c Model) ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+; LEDR[7] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
+; LEDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
+; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
+; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
+; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
+; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
+; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
+; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ;
+; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ;
+; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ;
++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
+
+
+-------------------
+; Clock Transfers ;
+-------------------
+Nothing to report.
+
+
+---------------
+; Report TCCS ;
+---------------
+No dedicated SERDES Transmitter circuitry present in device or used in design
+
+
+---------------
+; Report RSKM ;
+---------------
+No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+
+
++------------------------------------------------+
+; Unconstrained Paths Summary ;
++---------------------------------+-------+------+
+; Property ; Setup ; Hold ;
++---------------------------------+-------+------+
+; Illegal Clocks ; 0 ; 0 ;
+; Unconstrained Clocks ; 0 ; 0 ;
+; Unconstrained Input Ports ; 9 ; 9 ;
+; Unconstrained Input Port Paths ; 16 ; 16 ;
+; Unconstrained Output Ports ; 8 ; 8 ;
+; Unconstrained Output Port Paths ; 8 ; 8 ;
++---------------------------------+-------+------+
+
+
++--------------------------------------+
+; Clock Status Summary ;
++--------+--------+------+-------------+
+; Target ; Clock ; Type ; Status ;
++--------+--------+------+-------------+
+; KEY[0] ; KEY[0] ; Base ; Constrained ;
++--------+--------+------+-------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Unconstrained Input Ports ;
++------------+--------------------------------------------------------------------------------------+
+; Input Port ; Comment ;
++------------+--------------------------------------------------------------------------------------+
+; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
++------------+--------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Unconstrained Output Ports ;
++-------------+---------------------------------------------------------------------------------------+
+; Output Port ; Comment ;
++-------------+---------------------------------------------------------------------------------------+
+; LEDR[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
++-------------+---------------------------------------------------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------------+
+; Unconstrained Input Ports ;
++------------+--------------------------------------------------------------------------------------+
+; Input Port ; Comment ;
++------------+--------------------------------------------------------------------------------------+
+; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; SW[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
++------------+--------------------------------------------------------------------------------------+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Unconstrained Output Ports ;
++-------------+---------------------------------------------------------------------------------------+
+; Output Port ; Comment ;
++-------------+---------------------------------------------------------------------------------------+
+; LEDR[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+; LEDR[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
++-------------+---------------------------------------------------------------------------------------+
+
+
++--------------------------+
+; Timing Analyzer Messages ;
++--------------------------+
+Info: *******************************************************************
+Info: Running Quartus Prime Timing Analyzer
+ Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+ Info: Processing started: Wed Mar 22 09:20:05 2023
+Info: Command: quartus_sta RegisterDemo -c RegisterDemo
+Info: qsta_default_script.tcl version: #1
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'RegisterDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332105): Deriving Clocks
+ Info (332105): create_clock -period 1.000 -name KEY[0] KEY[0]
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
+Info: Analyzing Slow 1200mV 85C Model
+Info (332140): No fmax paths to report
+Info (332140): No Setup paths to report
+Info (332140): No Hold paths to report
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Critical Warning (332148): Timing requirements not met
+ Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer.
+Info (332146): Worst-case minimum pulse width slack is -3.000
+ Info (332119): Slack End Point TNS Clock
+ Info (332119): ========= =================== =====================
+ Info (332119): -3.000 -13.280 KEY[0]
+Info: Analyzing Slow 1200mV 0C Model
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332140): No fmax paths to report
+Info (332140): No Setup paths to report
+Info (332140): No Hold paths to report
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Critical Warning (332148): Timing requirements not met
+ Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer.
+Info (332146): Worst-case minimum pulse width slack is -3.000
+ Info (332119): Slack End Point TNS Clock
+ Info (332119): ========= =================== =====================
+ Info (332119): -3.000 -13.280 KEY[0]
+Info: Analyzing Fast 1200mV 0C Model
+Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
+Info (332140): No Setup paths to report
+Info (332140): No Hold paths to report
+Info (332140): No Recovery paths to report
+Info (332140): No Removal paths to report
+Critical Warning (332148): Timing requirements not met
+ Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer.
+Info (332146): Worst-case minimum pulse width slack is -3.000
+ Info (332119): Slack End Point TNS Clock
+ Info (332119): ========= =================== =====================
+ Info (332119): -3.000 -11.696 KEY[0]
+Info (332102): Design is not fully constrained for setup requirements
+Info (332102): Design is not fully constrained for hold requirements
+Info: Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings
+ Info: Peak virtual memory: 534 megabytes
+ Info: Processing ended: Wed Mar 22 09:20:08 2023
+ Info: Elapsed time: 00:00:03
+ Info: Total CPU time (on all processors): 00:00:03
+
+
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.sta.summary b/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.sta.summary
new file mode 100644
index 0000000..364aeea
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica04/RegisterDemo/output_files/RegisterDemo.sta.summary
@@ -0,0 +1,17 @@
+------------------------------------------------------------
+Timing Analyzer Summary
+------------------------------------------------------------
+
+Type : Slow 1200mV 85C Model Minimum Pulse Width 'KEY[0]'
+Slack : -3.000
+TNS : -13.280
+
+Type : Slow 1200mV 0C Model Minimum Pulse Width 'KEY[0]'
+Slack : -3.000
+TNS : -13.280
+
+Type : Fast 1200mV 0C Model Minimum Pulse Width 'KEY[0]'
+Slack : -3.000
+TNS : -11.696
+
+------------------------------------------------------------
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/modelsim/RegisterDemo.sft b/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/modelsim/RegisterDemo.sft
new file mode 100644
index 0000000..0c5034b
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/modelsim/RegisterDemo.sft
@@ -0,0 +1 @@
+set tool_name "ModelSim-Altera (VHDL)"
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/modelsim/RegisterDemo.vho b/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/modelsim/RegisterDemo.vho
new file mode 100644
index 0000000..d29e86e
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/modelsim/RegisterDemo.vho
@@ -0,0 +1,542 @@
+-- Copyright (C) 2020 Intel Corporation. All rights reserved.
+-- Your use of Intel Corporation's design tools, logic functions
+-- and other software and tools, and any partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Intel Program License
+-- Subscription Agreement, the Intel Quartus Prime License Agreement,
+-- the Intel FPGA IP License Agreement, or other applicable license
+-- agreement, including, without limitation, that your use is for
+-- the sole purpose of programming logic devices manufactured by
+-- Intel and sold by Intel or its authorized distributors. Please
+-- refer to the applicable agreement for further details, at
+-- https://fpgasoftware.intel.com/eula.
+
+-- VENDOR "Altera"
+-- PROGRAM "Quartus Prime"
+-- VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
+
+-- DATE "03/22/2023 09:20:09"
+
+--
+-- Device: Altera EP4CE115F29C7 Package FBGA780
+--
+
+--
+-- This VHDL file should be used for ModelSim-Altera (VHDL) only
+--
+
+LIBRARY CYCLONEIVE;
+LIBRARY IEEE;
+USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY hard_block IS
+ PORT (
+ devoe : IN std_logic;
+ devclrn : IN std_logic;
+ devpor : IN std_logic
+ );
+END hard_block;
+
+-- Design Ports Information
+-- ~ALTERA_ASDO_DATA1~ => Location: PIN_F4, I/O Standard: 2.5 V, Current Strength: Default
+-- ~ALTERA_FLASH_nCE_nCSO~ => Location: PIN_E2, I/O Standard: 2.5 V, Current Strength: Default
+-- ~ALTERA_DCLK~ => Location: PIN_P3, I/O Standard: 2.5 V, Current Strength: Default
+-- ~ALTERA_DATA0~ => Location: PIN_N7, I/O Standard: 2.5 V, Current Strength: Default
+-- ~ALTERA_nCEO~ => Location: PIN_P28, I/O Standard: 2.5 V, Current Strength: 8mA
+
+
+ARCHITECTURE structure OF hard_block IS
+SIGNAL gnd : std_logic := '0';
+SIGNAL vcc : std_logic := '1';
+SIGNAL unknown : std_logic := 'X';
+SIGNAL ww_devoe : std_logic;
+SIGNAL ww_devclrn : std_logic;
+SIGNAL ww_devpor : std_logic;
+SIGNAL \~ALTERA_ASDO_DATA1~~padout\ : std_logic;
+SIGNAL \~ALTERA_FLASH_nCE_nCSO~~padout\ : std_logic;
+SIGNAL \~ALTERA_DATA0~~padout\ : std_logic;
+SIGNAL \~ALTERA_ASDO_DATA1~~ibuf_o\ : std_logic;
+SIGNAL \~ALTERA_FLASH_nCE_nCSO~~ibuf_o\ : std_logic;
+SIGNAL \~ALTERA_DATA0~~ibuf_o\ : std_logic;
+
+BEGIN
+
+ww_devoe <= devoe;
+ww_devclrn <= devclrn;
+ww_devpor <= devpor;
+END structure;
+
+
+LIBRARY ALTERA;
+LIBRARY CYCLONEIVE;
+LIBRARY IEEE;
+USE ALTERA.ALTERA_PRIMITIVES_COMPONENTS.ALL;
+USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY RegisterDemo IS
+ PORT (
+ LEDR : OUT std_logic_vector(7 DOWNTO 0);
+ KEY : IN std_logic_vector(0 DOWNTO 0);
+ SW : IN std_logic_vector(8 DOWNTO 0)
+ );
+END RegisterDemo;
+
+-- Design Ports Information
+-- LEDR[7] => Location: PIN_H19, I/O Standard: 2.5 V, Current Strength: Default
+-- LEDR[6] => Location: PIN_J19, I/O Standard: 2.5 V, Current Strength: Default
+-- LEDR[5] => Location: PIN_E18, I/O Standard: 2.5 V, Current Strength: Default
+-- LEDR[4] => Location: PIN_F18, I/O Standard: 2.5 V, Current Strength: Default
+-- LEDR[3] => Location: PIN_F21, I/O Standard: 2.5 V, Current Strength: Default
+-- LEDR[2] => Location: PIN_E19, I/O Standard: 2.5 V, Current Strength: Default
+-- LEDR[1] => Location: PIN_F19, I/O Standard: 2.5 V, Current Strength: Default
+-- LEDR[0] => Location: PIN_G19, I/O Standard: 2.5 V, Current Strength: Default
+-- SW[7] => Location: PIN_AB26, I/O Standard: 2.5 V, Current Strength: Default
+-- KEY[0] => Location: PIN_M23, I/O Standard: 2.5 V, Current Strength: Default
+-- SW[8] => Location: PIN_AC25, I/O Standard: 2.5 V, Current Strength: Default
+-- SW[6] => Location: PIN_AD26, I/O Standard: 2.5 V, Current Strength: Default
+-- SW[5] => Location: PIN_AC26, I/O Standard: 2.5 V, Current Strength: Default
+-- SW[4] => Location: PIN_AB27, I/O Standard: 2.5 V, Current Strength: Default
+-- SW[3] => Location: PIN_AD27, I/O Standard: 2.5 V, Current Strength: Default
+-- SW[2] => Location: PIN_AC27, I/O Standard: 2.5 V, Current Strength: Default
+-- SW[1] => Location: PIN_AC28, I/O Standard: 2.5 V, Current Strength: Default
+-- SW[0] => Location: PIN_AB28, I/O Standard: 2.5 V, Current Strength: Default
+
+
+ARCHITECTURE structure OF RegisterDemo IS
+SIGNAL gnd : std_logic := '0';
+SIGNAL vcc : std_logic := '1';
+SIGNAL unknown : std_logic := 'X';
+SIGNAL devoe : std_logic := '1';
+SIGNAL devclrn : std_logic := '1';
+SIGNAL devpor : std_logic := '1';
+SIGNAL ww_devoe : std_logic;
+SIGNAL ww_devclrn : std_logic;
+SIGNAL ww_devpor : std_logic;
+SIGNAL ww_LEDR : std_logic_vector(7 DOWNTO 0);
+SIGNAL ww_KEY : std_logic_vector(0 DOWNTO 0);
+SIGNAL ww_SW : std_logic_vector(8 DOWNTO 0);
+SIGNAL \LEDR[7]~output_o\ : std_logic;
+SIGNAL \LEDR[6]~output_o\ : std_logic;
+SIGNAL \LEDR[5]~output_o\ : std_logic;
+SIGNAL \LEDR[4]~output_o\ : std_logic;
+SIGNAL \LEDR[3]~output_o\ : std_logic;
+SIGNAL \LEDR[2]~output_o\ : std_logic;
+SIGNAL \LEDR[1]~output_o\ : std_logic;
+SIGNAL \LEDR[0]~output_o\ : std_logic;
+SIGNAL \KEY[0]~input_o\ : std_logic;
+SIGNAL \SW[7]~input_o\ : std_logic;
+SIGNAL \inst|dataOut[7]~feeder_combout\ : std_logic;
+SIGNAL \SW[8]~input_o\ : std_logic;
+SIGNAL \SW[6]~input_o\ : std_logic;
+SIGNAL \SW[5]~input_o\ : std_logic;
+SIGNAL \inst|dataOut[5]~feeder_combout\ : std_logic;
+SIGNAL \SW[4]~input_o\ : std_logic;
+SIGNAL \SW[3]~input_o\ : std_logic;
+SIGNAL \SW[2]~input_o\ : std_logic;
+SIGNAL \SW[1]~input_o\ : std_logic;
+SIGNAL \SW[0]~input_o\ : std_logic;
+SIGNAL \inst|dataOut\ : std_logic_vector(7 DOWNTO 0);
+
+COMPONENT hard_block
+ PORT (
+ devoe : IN std_logic;
+ devclrn : IN std_logic;
+ devpor : IN std_logic);
+END COMPONENT;
+
+BEGIN
+
+LEDR <= ww_LEDR;
+ww_KEY <= KEY;
+ww_SW <= SW;
+ww_devoe <= devoe;
+ww_devclrn <= devclrn;
+ww_devpor <= devpor;
+auto_generated_inst : hard_block
+PORT MAP (
+ devoe => ww_devoe,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor);
+
+-- Location: IOOBUF_X72_Y73_N2
+\LEDR[7]~output\ : cycloneive_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+ bus_hold => "false",
+ open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+ i => \inst|dataOut\(7),
+ devoe => ww_devoe,
+ o => \LEDR[7]~output_o\);
+
+-- Location: IOOBUF_X72_Y73_N9
+\LEDR[6]~output\ : cycloneive_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+ bus_hold => "false",
+ open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+ i => \inst|dataOut\(6),
+ devoe => ww_devoe,
+ o => \LEDR[6]~output_o\);
+
+-- Location: IOOBUF_X87_Y73_N9
+\LEDR[5]~output\ : cycloneive_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+ bus_hold => "false",
+ open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+ i => \inst|dataOut\(5),
+ devoe => ww_devoe,
+ o => \LEDR[5]~output_o\);
+
+-- Location: IOOBUF_X87_Y73_N16
+\LEDR[4]~output\ : cycloneive_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+ bus_hold => "false",
+ open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+ i => \inst|dataOut\(4),
+ devoe => ww_devoe,
+ o => \LEDR[4]~output_o\);
+
+-- Location: IOOBUF_X107_Y73_N16
+\LEDR[3]~output\ : cycloneive_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+ bus_hold => "false",
+ open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+ i => \inst|dataOut\(3),
+ devoe => ww_devoe,
+ o => \LEDR[3]~output_o\);
+
+-- Location: IOOBUF_X94_Y73_N9
+\LEDR[2]~output\ : cycloneive_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+ bus_hold => "false",
+ open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+ i => \inst|dataOut\(2),
+ devoe => ww_devoe,
+ o => \LEDR[2]~output_o\);
+
+-- Location: IOOBUF_X94_Y73_N2
+\LEDR[1]~output\ : cycloneive_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+ bus_hold => "false",
+ open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+ i => \inst|dataOut\(1),
+ devoe => ww_devoe,
+ o => \LEDR[1]~output_o\);
+
+-- Location: IOOBUF_X69_Y73_N16
+\LEDR[0]~output\ : cycloneive_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+ bus_hold => "false",
+ open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+ i => \inst|dataOut\(0),
+ devoe => ww_devoe,
+ o => \LEDR[0]~output_o\);
+
+-- Location: IOIBUF_X115_Y40_N8
+\KEY[0]~input\ : cycloneive_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+ bus_hold => "false",
+ simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+ i => ww_KEY(0),
+ o => \KEY[0]~input_o\);
+
+-- Location: IOIBUF_X115_Y15_N1
+\SW[7]~input\ : cycloneive_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+ bus_hold => "false",
+ simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+ i => ww_SW(7),
+ o => \SW[7]~input_o\);
+
+-- Location: LCCOMB_X114_Y40_N24
+\inst|dataOut[7]~feeder\ : cycloneive_lcell_comb
+-- Equation(s):
+-- \inst|dataOut[7]~feeder_combout\ = \SW[7]~input_o\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "1111111100000000",
+ sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+ datad => \SW[7]~input_o\,
+ combout => \inst|dataOut[7]~feeder_combout\);
+
+-- Location: IOIBUF_X115_Y4_N22
+\SW[8]~input\ : cycloneive_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+ bus_hold => "false",
+ simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+ i => ww_SW(8),
+ o => \SW[8]~input_o\);
+
+-- Location: FF_X114_Y40_N25
+\inst|dataOut[7]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+ is_wysiwyg => "true",
+ power_up => "low")
+-- pragma translate_on
+PORT MAP (
+ clk => \KEY[0]~input_o\,
+ d => \inst|dataOut[7]~feeder_combout\,
+ ena => \SW[8]~input_o\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ q => \inst|dataOut\(7));
+
+-- Location: IOIBUF_X115_Y10_N1
+\SW[6]~input\ : cycloneive_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+ bus_hold => "false",
+ simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+ i => ww_SW(6),
+ o => \SW[6]~input_o\);
+
+-- Location: FF_X114_Y40_N27
+\inst|dataOut[6]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+ is_wysiwyg => "true",
+ power_up => "low")
+-- pragma translate_on
+PORT MAP (
+ clk => \KEY[0]~input_o\,
+ asdata => \SW[6]~input_o\,
+ sload => VCC,
+ ena => \SW[8]~input_o\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ q => \inst|dataOut\(6));
+
+-- Location: IOIBUF_X115_Y11_N8
+\SW[5]~input\ : cycloneive_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+ bus_hold => "false",
+ simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+ i => ww_SW(5),
+ o => \SW[5]~input_o\);
+
+-- Location: LCCOMB_X114_Y40_N4
+\inst|dataOut[5]~feeder\ : cycloneive_lcell_comb
+-- Equation(s):
+-- \inst|dataOut[5]~feeder_combout\ = \SW[5]~input_o\
+
+-- pragma translate_off
+GENERIC MAP (
+ lut_mask => "1111111100000000",
+ sum_lutc_input => "datac")
+-- pragma translate_on
+PORT MAP (
+ datad => \SW[5]~input_o\,
+ combout => \inst|dataOut[5]~feeder_combout\);
+
+-- Location: FF_X114_Y40_N5
+\inst|dataOut[5]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+ is_wysiwyg => "true",
+ power_up => "low")
+-- pragma translate_on
+PORT MAP (
+ clk => \KEY[0]~input_o\,
+ d => \inst|dataOut[5]~feeder_combout\,
+ ena => \SW[8]~input_o\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ q => \inst|dataOut\(5));
+
+-- Location: IOIBUF_X115_Y18_N8
+\SW[4]~input\ : cycloneive_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+ bus_hold => "false",
+ simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+ i => ww_SW(4),
+ o => \SW[4]~input_o\);
+
+-- Location: FF_X114_Y40_N23
+\inst|dataOut[4]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+ is_wysiwyg => "true",
+ power_up => "low")
+-- pragma translate_on
+PORT MAP (
+ clk => \KEY[0]~input_o\,
+ asdata => \SW[4]~input_o\,
+ sload => VCC,
+ ena => \SW[8]~input_o\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ q => \inst|dataOut\(4));
+
+-- Location: IOIBUF_X115_Y13_N8
+\SW[3]~input\ : cycloneive_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+ bus_hold => "false",
+ simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+ i => ww_SW(3),
+ o => \SW[3]~input_o\);
+
+-- Location: FF_X114_Y40_N1
+\inst|dataOut[3]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+ is_wysiwyg => "true",
+ power_up => "low")
+-- pragma translate_on
+PORT MAP (
+ clk => \KEY[0]~input_o\,
+ asdata => \SW[3]~input_o\,
+ sload => VCC,
+ ena => \SW[8]~input_o\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ q => \inst|dataOut\(3));
+
+-- Location: IOIBUF_X115_Y15_N8
+\SW[2]~input\ : cycloneive_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+ bus_hold => "false",
+ simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+ i => ww_SW(2),
+ o => \SW[2]~input_o\);
+
+-- Location: FF_X114_Y40_N19
+\inst|dataOut[2]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+ is_wysiwyg => "true",
+ power_up => "low")
+-- pragma translate_on
+PORT MAP (
+ clk => \KEY[0]~input_o\,
+ asdata => \SW[2]~input_o\,
+ sload => VCC,
+ ena => \SW[8]~input_o\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ q => \inst|dataOut\(2));
+
+-- Location: IOIBUF_X115_Y14_N1
+\SW[1]~input\ : cycloneive_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+ bus_hold => "false",
+ simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+ i => ww_SW(1),
+ o => \SW[1]~input_o\);
+
+-- Location: FF_X114_Y40_N13
+\inst|dataOut[1]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+ is_wysiwyg => "true",
+ power_up => "low")
+-- pragma translate_on
+PORT MAP (
+ clk => \KEY[0]~input_o\,
+ asdata => \SW[1]~input_o\,
+ sload => VCC,
+ ena => \SW[8]~input_o\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ q => \inst|dataOut\(1));
+
+-- Location: IOIBUF_X115_Y17_N1
+\SW[0]~input\ : cycloneive_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+ bus_hold => "false",
+ simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+ i => ww_SW(0),
+ o => \SW[0]~input_o\);
+
+-- Location: FF_X114_Y40_N7
+\inst|dataOut[0]\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+ is_wysiwyg => "true",
+ power_up => "low")
+-- pragma translate_on
+PORT MAP (
+ clk => \KEY[0]~input_o\,
+ asdata => \SW[0]~input_o\,
+ sload => VCC,
+ ena => \SW[8]~input_o\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ q => \inst|dataOut\(0));
+
+ww_LEDR(7) <= \LEDR[7]~output_o\;
+
+ww_LEDR(6) <= \LEDR[6]~output_o\;
+
+ww_LEDR(5) <= \LEDR[5]~output_o\;
+
+ww_LEDR(4) <= \LEDR[4]~output_o\;
+
+ww_LEDR(3) <= \LEDR[3]~output_o\;
+
+ww_LEDR(2) <= \LEDR[2]~output_o\;
+
+ww_LEDR(1) <= \LEDR[1]~output_o\;
+
+ww_LEDR(0) <= \LEDR[0]~output_o\;
+END structure;
+
+
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/modelsim/RegisterDemo_modelsim.xrf b/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/modelsim/RegisterDemo_modelsim.xrf
new file mode 100644
index 0000000..c7027af
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/modelsim/RegisterDemo_modelsim.xrf
@@ -0,0 +1,39 @@
+vendor_name = ModelSim
+source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/Register8.vhd
+source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/Register8.vwf
+source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/RegisterDemo.bdf
+source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_b.vhd
+source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_p.vhd
+source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_b.vhd
+source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_p.vhd
+source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.cbx.xml
+design_name = hard_block
+design_name = RegisterDemo
+instance = comp, \LEDR[7]~output\, LEDR[7]~output, RegisterDemo, 1
+instance = comp, \LEDR[6]~output\, LEDR[6]~output, RegisterDemo, 1
+instance = comp, \LEDR[5]~output\, LEDR[5]~output, RegisterDemo, 1
+instance = comp, \LEDR[4]~output\, LEDR[4]~output, RegisterDemo, 1
+instance = comp, \LEDR[3]~output\, LEDR[3]~output, RegisterDemo, 1
+instance = comp, \LEDR[2]~output\, LEDR[2]~output, RegisterDemo, 1
+instance = comp, \LEDR[1]~output\, LEDR[1]~output, RegisterDemo, 1
+instance = comp, \LEDR[0]~output\, LEDR[0]~output, RegisterDemo, 1
+instance = comp, \KEY[0]~input\, KEY[0]~input, RegisterDemo, 1
+instance = comp, \SW[7]~input\, SW[7]~input, RegisterDemo, 1
+instance = comp, \inst|dataOut[7]~feeder\, inst|dataOut[7]~feeder, RegisterDemo, 1
+instance = comp, \SW[8]~input\, SW[8]~input, RegisterDemo, 1
+instance = comp, \inst|dataOut[7]\, inst|dataOut[7], RegisterDemo, 1
+instance = comp, \SW[6]~input\, SW[6]~input, RegisterDemo, 1
+instance = comp, \inst|dataOut[6]\, inst|dataOut[6], RegisterDemo, 1
+instance = comp, \SW[5]~input\, SW[5]~input, RegisterDemo, 1
+instance = comp, \inst|dataOut[5]~feeder\, inst|dataOut[5]~feeder, RegisterDemo, 1
+instance = comp, \inst|dataOut[5]\, inst|dataOut[5], RegisterDemo, 1
+instance = comp, \SW[4]~input\, SW[4]~input, RegisterDemo, 1
+instance = comp, \inst|dataOut[4]\, inst|dataOut[4], RegisterDemo, 1
+instance = comp, \SW[3]~input\, SW[3]~input, RegisterDemo, 1
+instance = comp, \inst|dataOut[3]\, inst|dataOut[3], RegisterDemo, 1
+instance = comp, \SW[2]~input\, SW[2]~input, RegisterDemo, 1
+instance = comp, \inst|dataOut[2]\, inst|dataOut[2], RegisterDemo, 1
+instance = comp, \SW[1]~input\, SW[1]~input, RegisterDemo, 1
+instance = comp, \inst|dataOut[1]\, inst|dataOut[1], RegisterDemo, 1
+instance = comp, \SW[0]~input\, SW[0]~input, RegisterDemo, 1
+instance = comp, \inst|dataOut[0]\, inst|dataOut[0], RegisterDemo, 1
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/Register8.vwf.vht b/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/Register8.vwf.vht
new file mode 100644
index 0000000..d6d8948
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/Register8.vwf.vht
@@ -0,0 +1,339 @@
+-- Copyright (C) 2020 Intel Corporation. All rights reserved.
+-- Your use of Intel Corporation's design tools, logic functions
+-- and other software and tools, and any partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Intel Program License
+-- Subscription Agreement, the Intel Quartus Prime License Agreement,
+-- the Intel FPGA IP License Agreement, or other applicable license
+-- agreement, including, without limitation, that your use is for
+-- the sole purpose of programming logic devices manufactured by
+-- Intel and sold by Intel or its authorized distributors. Please
+-- refer to the applicable agreement for further details, at
+-- https://fpgasoftware.intel.com/eula.
+
+-- *****************************************************************************
+-- This file contains a Vhdl test bench with test vectors .The test vectors
+-- are exported from a vector file in the Quartus Waveform Editor and apply to
+-- the top level entity of the current Quartus project .The user can use this
+-- testbench to simulate his design using a third-party simulation tool .
+-- *****************************************************************************
+-- Generated on "03/22/2023 09:15:28"
+
+-- Vhdl Test Bench(with test vectors) for design : Register8
+--
+-- Simulation tool : 3rd Party
+--
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+ENTITY Register8_vhd_vec_tst IS
+END Register8_vhd_vec_tst;
+ARCHITECTURE Register8_arch OF Register8_vhd_vec_tst IS
+-- constants
+-- signals
+SIGNAL clk : STD_LOGIC;
+SIGNAL dataIn : STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL dataOut : STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL wrEn : STD_LOGIC;
+COMPONENT Register8
+ PORT (
+ clk : IN STD_LOGIC;
+ dataIn : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+ dataOut : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+ wrEn : IN STD_LOGIC
+ );
+END COMPONENT;
+BEGIN
+ i1 : Register8
+ PORT MAP (
+-- list connections between master ports and signals
+ clk => clk,
+ dataIn => dataIn,
+ dataOut => dataOut,
+ wrEn => wrEn
+ );
+
+-- wrEn
+t_prcs_wrEn: PROCESS
+BEGIN
+ wrEn <= '0';
+ WAIT FOR 400000 ps;
+ wrEn <= '1';
+ WAIT FOR 400000 ps;
+ wrEn <= '0';
+WAIT;
+END PROCESS t_prcs_wrEn;
+
+-- clk
+t_prcs_clk: PROCESS
+BEGIN
+LOOP
+ clk <= '0';
+ WAIT FOR 20000 ps;
+ clk <= '1';
+ WAIT FOR 20000 ps;
+ IF (NOW >= 1000000 ps) THEN WAIT; END IF;
+END LOOP;
+END PROCESS t_prcs_clk;
+-- dataIn[7]
+t_prcs_dataIn_7: PROCESS
+BEGIN
+ dataIn(7) <= '1';
+ WAIT FOR 200000 ps;
+ dataIn(7) <= '0';
+ WAIT FOR 40000 ps;
+ dataIn(7) <= '1';
+ WAIT FOR 120000 ps;
+ dataIn(7) <= '0';
+ WAIT FOR 40000 ps;
+ dataIn(7) <= '1';
+ WAIT FOR 40000 ps;
+ dataIn(7) <= '0';
+ WAIT FOR 120000 ps;
+ dataIn(7) <= '1';
+ WAIT FOR 40000 ps;
+ dataIn(7) <= '0';
+ WAIT FOR 40000 ps;
+ dataIn(7) <= '1';
+ WAIT FOR 40000 ps;
+ dataIn(7) <= '0';
+ WAIT FOR 40000 ps;
+ dataIn(7) <= '1';
+ WAIT FOR 40000 ps;
+ dataIn(7) <= '0';
+ WAIT FOR 40000 ps;
+ dataIn(7) <= '1';
+ WAIT FOR 40000 ps;
+ dataIn(7) <= '0';
+ WAIT FOR 120000 ps;
+ dataIn(7) <= '1';
+WAIT;
+END PROCESS t_prcs_dataIn_7;
+-- dataIn[6]
+t_prcs_dataIn_6: PROCESS
+BEGIN
+ dataIn(6) <= '0';
+ WAIT FOR 80000 ps;
+ dataIn(6) <= '1';
+ WAIT FOR 80000 ps;
+ dataIn(6) <= '0';
+ WAIT FOR 40000 ps;
+ dataIn(6) <= '1';
+ WAIT FOR 40000 ps;
+ dataIn(6) <= '0';
+ WAIT FOR 40000 ps;
+ dataIn(6) <= '1';
+ WAIT FOR 40000 ps;
+ dataIn(6) <= '0';
+ WAIT FOR 120000 ps;
+ dataIn(6) <= '1';
+ WAIT FOR 120000 ps;
+ dataIn(6) <= '0';
+ WAIT FOR 40000 ps;
+ dataIn(6) <= '1';
+ WAIT FOR 80000 ps;
+ dataIn(6) <= '0';
+ WAIT FOR 120000 ps;
+ dataIn(6) <= '1';
+ WAIT FOR 40000 ps;
+ dataIn(6) <= '0';
+ WAIT FOR 120000 ps;
+ dataIn(6) <= '1';
+WAIT;
+END PROCESS t_prcs_dataIn_6;
+-- dataIn[5]
+t_prcs_dataIn_5: PROCESS
+BEGIN
+ dataIn(5) <= '0';
+ WAIT FOR 80000 ps;
+ dataIn(5) <= '1';
+ WAIT FOR 40000 ps;
+ dataIn(5) <= '0';
+ WAIT FOR 120000 ps;
+ dataIn(5) <= '1';
+ WAIT FOR 40000 ps;
+ dataIn(5) <= '0';
+ WAIT FOR 80000 ps;
+ dataIn(5) <= '1';
+ WAIT FOR 40000 ps;
+ dataIn(5) <= '0';
+ WAIT FOR 80000 ps;
+ dataIn(5) <= '1';
+ WAIT FOR 80000 ps;
+ dataIn(5) <= '0';
+ WAIT FOR 120000 ps;
+ dataIn(5) <= '1';
+ WAIT FOR 40000 ps;
+ dataIn(5) <= '0';
+ WAIT FOR 40000 ps;
+ dataIn(5) <= '1';
+ WAIT FOR 80000 ps;
+ dataIn(5) <= '0';
+ WAIT FOR 40000 ps;
+ dataIn(5) <= '1';
+ WAIT FOR 40000 ps;
+ dataIn(5) <= '0';
+ WAIT FOR 40000 ps;
+ dataIn(5) <= '1';
+WAIT;
+END PROCESS t_prcs_dataIn_5;
+-- dataIn[4]
+t_prcs_dataIn_4: PROCESS
+BEGIN
+ dataIn(4) <= '0';
+ WAIT FOR 200000 ps;
+ dataIn(4) <= '1';
+ WAIT FOR 160000 ps;
+ dataIn(4) <= '0';
+ WAIT FOR 40000 ps;
+ dataIn(4) <= '1';
+ WAIT FOR 320000 ps;
+ dataIn(4) <= '0';
+ WAIT FOR 160000 ps;
+ dataIn(4) <= '1';
+ WAIT FOR 40000 ps;
+ dataIn(4) <= '0';
+WAIT;
+END PROCESS t_prcs_dataIn_4;
+-- dataIn[3]
+t_prcs_dataIn_3: PROCESS
+BEGIN
+ dataIn(3) <= '1';
+ WAIT FOR 160000 ps;
+ dataIn(3) <= '0';
+ WAIT FOR 40000 ps;
+ dataIn(3) <= '1';
+ WAIT FOR 120000 ps;
+ dataIn(3) <= '0';
+ WAIT FOR 40000 ps;
+ dataIn(3) <= '1';
+ WAIT FOR 80000 ps;
+ dataIn(3) <= '0';
+ WAIT FOR 80000 ps;
+ dataIn(3) <= '1';
+ WAIT FOR 40000 ps;
+ dataIn(3) <= '0';
+ WAIT FOR 40000 ps;
+ dataIn(3) <= '1';
+ WAIT FOR 160000 ps;
+ dataIn(3) <= '0';
+ WAIT FOR 40000 ps;
+ dataIn(3) <= '1';
+ WAIT FOR 120000 ps;
+ dataIn(3) <= '0';
+WAIT;
+END PROCESS t_prcs_dataIn_3;
+-- dataIn[2]
+t_prcs_dataIn_2: PROCESS
+BEGIN
+ dataIn(2) <= '0';
+ WAIT FOR 80000 ps;
+ dataIn(2) <= '1';
+ WAIT FOR 40000 ps;
+ dataIn(2) <= '0';
+ WAIT FOR 120000 ps;
+ dataIn(2) <= '1';
+ WAIT FOR 40000 ps;
+ dataIn(2) <= '0';
+ WAIT FOR 40000 ps;
+ dataIn(2) <= '1';
+ WAIT FOR 40000 ps;
+ dataIn(2) <= '0';
+ WAIT FOR 120000 ps;
+ dataIn(2) <= '1';
+ WAIT FOR 40000 ps;
+ dataIn(2) <= '0';
+ WAIT FOR 40000 ps;
+ dataIn(2) <= '1';
+ WAIT FOR 80000 ps;
+ dataIn(2) <= '0';
+ WAIT FOR 40000 ps;
+ dataIn(2) <= '1';
+ WAIT FOR 40000 ps;
+ dataIn(2) <= '0';
+ WAIT FOR 40000 ps;
+ dataIn(2) <= '1';
+ WAIT FOR 80000 ps;
+ dataIn(2) <= '0';
+ WAIT FOR 80000 ps;
+ dataIn(2) <= '1';
+WAIT;
+END PROCESS t_prcs_dataIn_2;
+-- dataIn[1]
+t_prcs_dataIn_1: PROCESS
+BEGIN
+ dataIn(1) <= '1';
+ WAIT FOR 80000 ps;
+ dataIn(1) <= '0';
+ WAIT FOR 80000 ps;
+ dataIn(1) <= '1';
+ WAIT FOR 80000 ps;
+ dataIn(1) <= '0';
+ WAIT FOR 80000 ps;
+ dataIn(1) <= '1';
+ WAIT FOR 40000 ps;
+ dataIn(1) <= '0';
+ WAIT FOR 40000 ps;
+ dataIn(1) <= '1';
+ WAIT FOR 40000 ps;
+ dataIn(1) <= '0';
+ WAIT FOR 80000 ps;
+ dataIn(1) <= '1';
+ WAIT FOR 40000 ps;
+ dataIn(1) <= '0';
+ WAIT FOR 120000 ps;
+ dataIn(1) <= '1';
+ WAIT FOR 40000 ps;
+ dataIn(1) <= '0';
+ WAIT FOR 40000 ps;
+ dataIn(1) <= '1';
+ WAIT FOR 40000 ps;
+ dataIn(1) <= '0';
+ WAIT FOR 40000 ps;
+ dataIn(1) <= '1';
+ WAIT FOR 40000 ps;
+ dataIn(1) <= '0';
+ WAIT FOR 40000 ps;
+ dataIn(1) <= '1';
+ WAIT FOR 40000 ps;
+ dataIn(1) <= '0';
+WAIT;
+END PROCESS t_prcs_dataIn_1;
+-- dataIn[0]
+t_prcs_dataIn_0: PROCESS
+BEGIN
+ dataIn(0) <= '1';
+ WAIT FOR 160000 ps;
+ dataIn(0) <= '0';
+ WAIT FOR 40000 ps;
+ dataIn(0) <= '1';
+ WAIT FOR 120000 ps;
+ dataIn(0) <= '0';
+ WAIT FOR 40000 ps;
+ dataIn(0) <= '1';
+ WAIT FOR 40000 ps;
+ dataIn(0) <= '0';
+ WAIT FOR 40000 ps;
+ dataIn(0) <= '1';
+ WAIT FOR 40000 ps;
+ dataIn(0) <= '0';
+ WAIT FOR 40000 ps;
+ dataIn(0) <= '1';
+ WAIT FOR 40000 ps;
+ dataIn(0) <= '0';
+ WAIT FOR 160000 ps;
+ dataIn(0) <= '1';
+ WAIT FOR 40000 ps;
+ dataIn(0) <= '0';
+ WAIT FOR 80000 ps;
+ dataIn(0) <= '1';
+ WAIT FOR 80000 ps;
+ dataIn(0) <= '0';
+ WAIT FOR 40000 ps;
+ dataIn(0) <= '1';
+WAIT;
+END PROCESS t_prcs_dataIn_0;
+END Register8_arch;
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/RegisterDemo.do b/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/RegisterDemo.do
new file mode 100644
index 0000000..cc16917
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/RegisterDemo.do
@@ -0,0 +1,17 @@
+onerror {exit -code 1}
+vlib work
+vcom -work work RegisterDemo.vho
+vcom -work work Register8.vwf.vht
+vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.Register8_vhd_vec_tst
+vcd file -direction RegisterDemo.msim.vcd
+vcd add -internal Register8_vhd_vec_tst/*
+vcd add -internal Register8_vhd_vec_tst/i1/*
+proc simTimestamp {} {
+ echo "Simulation time: $::now ps"
+ if { [string equal running [runStatus]] } {
+ after 2500 simTimestamp
+ }
+}
+after 2500 simTimestamp
+run -all
+quit -f
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/RegisterDemo.msim.vcd b/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/RegisterDemo.msim.vcd
new file mode 100644
index 0000000..78a0e20
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/RegisterDemo.msim.vcd
@@ -0,0 +1,863 @@
+$comment
+ File created using the following command:
+ vcd file RegisterDemo.msim.vcd -direction
+$end
+$date
+ Wed Mar 22 09:15:32 2023
+$end
+$version
+ ModelSim Version 2020.1
+$end
+$timescale
+ 1ps
+$end
+
+$scope module register8_vhd_vec_tst $end
+$var wire 1 ! clk $end
+$var wire 1 " dataIn [7] $end
+$var wire 1 # dataIn [6] $end
+$var wire 1 $ dataIn [5] $end
+$var wire 1 % dataIn [4] $end
+$var wire 1 & dataIn [3] $end
+$var wire 1 ' dataIn [2] $end
+$var wire 1 ( dataIn [1] $end
+$var wire 1 ) dataIn [0] $end
+$var wire 1 * dataOut [7] $end
+$var wire 1 + dataOut [6] $end
+$var wire 1 , dataOut [5] $end
+$var wire 1 - dataOut [4] $end
+$var wire 1 . dataOut [3] $end
+$var wire 1 / dataOut [2] $end
+$var wire 1 0 dataOut [1] $end
+$var wire 1 1 dataOut [0] $end
+$var wire 1 2 wrEn $end
+
+$scope module i1 $end
+$var wire 1 3 gnd $end
+$var wire 1 4 vcc $end
+$var wire 1 5 unknown $end
+$var wire 1 6 devoe $end
+$var wire 1 7 devclrn $end
+$var wire 1 8 devpor $end
+$var wire 1 9 ww_devoe $end
+$var wire 1 : ww_devclrn $end
+$var wire 1 ; ww_devpor $end
+$var wire 1 < ww_dataIn [7] $end
+$var wire 1 = ww_dataIn [6] $end
+$var wire 1 > ww_dataIn [5] $end
+$var wire 1 ? ww_dataIn [4] $end
+$var wire 1 @ ww_dataIn [3] $end
+$var wire 1 A ww_dataIn [2] $end
+$var wire 1 B ww_dataIn [1] $end
+$var wire 1 C ww_dataIn [0] $end
+$var wire 1 D ww_clk $end
+$var wire 1 E ww_wrEn $end
+$var wire 1 F ww_dataOut [7] $end
+$var wire 1 G ww_dataOut [6] $end
+$var wire 1 H ww_dataOut [5] $end
+$var wire 1 I ww_dataOut [4] $end
+$var wire 1 J ww_dataOut [3] $end
+$var wire 1 K ww_dataOut [2] $end
+$var wire 1 L ww_dataOut [1] $end
+$var wire 1 M ww_dataOut [0] $end
+$var wire 1 N \dataOut[0]~output_o\ $end
+$var wire 1 O \dataOut[1]~output_o\ $end
+$var wire 1 P \dataOut[2]~output_o\ $end
+$var wire 1 Q \dataOut[3]~output_o\ $end
+$var wire 1 R \dataOut[4]~output_o\ $end
+$var wire 1 S \dataOut[5]~output_o\ $end
+$var wire 1 T \dataOut[6]~output_o\ $end
+$var wire 1 U \dataOut[7]~output_o\ $end
+$var wire 1 V \clk~input_o\ $end
+$var wire 1 W \dataIn[0]~input_o\ $end
+$var wire 1 X \wrEn~input_o\ $end
+$var wire 1 Y \dataOut[0]~reg0_q\ $end
+$var wire 1 Z \dataIn[1]~input_o\ $end
+$var wire 1 [ \dataOut[1]~reg0_q\ $end
+$var wire 1 \ \dataIn[2]~input_o\ $end
+$var wire 1 ] \dataOut[2]~reg0_q\ $end
+$var wire 1 ^ \dataIn[3]~input_o\ $end
+$var wire 1 _ \dataOut[3]~reg0_q\ $end
+$var wire 1 ` \dataIn[4]~input_o\ $end
+$var wire 1 a \dataOut[4]~reg0_q\ $end
+$var wire 1 b \dataIn[5]~input_o\ $end
+$var wire 1 c \dataOut[5]~reg0_q\ $end
+$var wire 1 d \dataIn[6]~input_o\ $end
+$var wire 1 e \dataOut[6]~reg0_q\ $end
+$var wire 1 f \dataIn[7]~input_o\ $end
+$var wire 1 g \dataOut[7]~reg0_q\ $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
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diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/RegisterDemo.sft b/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/RegisterDemo.sft
new file mode 100644
index 0000000..0c5034b
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/RegisterDemo.sft
@@ -0,0 +1 @@
+set tool_name "ModelSim-Altera (VHDL)"
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/RegisterDemo.vho b/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/RegisterDemo.vho
new file mode 100644
index 0000000..671d429
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/RegisterDemo.vho
@@ -0,0 +1,414 @@
+-- Copyright (C) 2020 Intel Corporation. All rights reserved.
+-- Your use of Intel Corporation's design tools, logic functions
+-- and other software and tools, and any partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Intel Program License
+-- Subscription Agreement, the Intel Quartus Prime License Agreement,
+-- the Intel FPGA IP License Agreement, or other applicable license
+-- agreement, including, without limitation, that your use is for
+-- the sole purpose of programming logic devices manufactured by
+-- Intel and sold by Intel or its authorized distributors. Please
+-- refer to the applicable agreement for further details, at
+-- https://fpgasoftware.intel.com/eula.
+
+-- VENDOR "Altera"
+-- PROGRAM "Quartus Prime"
+-- VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
+
+-- DATE "03/22/2023 09:15:30"
+
+--
+-- Device: Altera EP4CE115F29C7 Package FBGA780
+--
+
+--
+-- This VHDL file should be used for ModelSim-Altera (VHDL) only
+--
+
+LIBRARY ALTERA;
+LIBRARY CYCLONEIVE;
+LIBRARY IEEE;
+USE ALTERA.ALTERA_PRIMITIVES_COMPONENTS.ALL;
+USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY Register8 IS
+ PORT (
+ dataIn : IN std_logic_vector(7 DOWNTO 0);
+ clk : IN std_logic;
+ wrEn : IN std_logic;
+ dataOut : OUT std_logic_vector(7 DOWNTO 0)
+ );
+END Register8;
+
+ARCHITECTURE structure OF Register8 IS
+SIGNAL gnd : std_logic := '0';
+SIGNAL vcc : std_logic := '1';
+SIGNAL unknown : std_logic := 'X';
+SIGNAL devoe : std_logic := '1';
+SIGNAL devclrn : std_logic := '1';
+SIGNAL devpor : std_logic := '1';
+SIGNAL ww_devoe : std_logic;
+SIGNAL ww_devclrn : std_logic;
+SIGNAL ww_devpor : std_logic;
+SIGNAL ww_dataIn : std_logic_vector(7 DOWNTO 0);
+SIGNAL ww_clk : std_logic;
+SIGNAL ww_wrEn : std_logic;
+SIGNAL ww_dataOut : std_logic_vector(7 DOWNTO 0);
+SIGNAL \dataOut[0]~output_o\ : std_logic;
+SIGNAL \dataOut[1]~output_o\ : std_logic;
+SIGNAL \dataOut[2]~output_o\ : std_logic;
+SIGNAL \dataOut[3]~output_o\ : std_logic;
+SIGNAL \dataOut[4]~output_o\ : std_logic;
+SIGNAL \dataOut[5]~output_o\ : std_logic;
+SIGNAL \dataOut[6]~output_o\ : std_logic;
+SIGNAL \dataOut[7]~output_o\ : std_logic;
+SIGNAL \clk~input_o\ : std_logic;
+SIGNAL \dataIn[0]~input_o\ : std_logic;
+SIGNAL \wrEn~input_o\ : std_logic;
+SIGNAL \dataOut[0]~reg0_q\ : std_logic;
+SIGNAL \dataIn[1]~input_o\ : std_logic;
+SIGNAL \dataOut[1]~reg0_q\ : std_logic;
+SIGNAL \dataIn[2]~input_o\ : std_logic;
+SIGNAL \dataOut[2]~reg0_q\ : std_logic;
+SIGNAL \dataIn[3]~input_o\ : std_logic;
+SIGNAL \dataOut[3]~reg0_q\ : std_logic;
+SIGNAL \dataIn[4]~input_o\ : std_logic;
+SIGNAL \dataOut[4]~reg0_q\ : std_logic;
+SIGNAL \dataIn[5]~input_o\ : std_logic;
+SIGNAL \dataOut[5]~reg0_q\ : std_logic;
+SIGNAL \dataIn[6]~input_o\ : std_logic;
+SIGNAL \dataOut[6]~reg0_q\ : std_logic;
+SIGNAL \dataIn[7]~input_o\ : std_logic;
+SIGNAL \dataOut[7]~reg0_q\ : std_logic;
+
+BEGIN
+
+ww_dataIn <= dataIn;
+ww_clk <= clk;
+ww_wrEn <= wrEn;
+dataOut <= ww_dataOut;
+ww_devoe <= devoe;
+ww_devclrn <= devclrn;
+ww_devpor <= devpor;
+
+\dataOut[0]~output\ : cycloneive_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+ bus_hold => "false",
+ open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+ i => \dataOut[0]~reg0_q\,
+ devoe => ww_devoe,
+ o => \dataOut[0]~output_o\);
+
+\dataOut[1]~output\ : cycloneive_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+ bus_hold => "false",
+ open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+ i => \dataOut[1]~reg0_q\,
+ devoe => ww_devoe,
+ o => \dataOut[1]~output_o\);
+
+\dataOut[2]~output\ : cycloneive_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+ bus_hold => "false",
+ open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+ i => \dataOut[2]~reg0_q\,
+ devoe => ww_devoe,
+ o => \dataOut[2]~output_o\);
+
+\dataOut[3]~output\ : cycloneive_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+ bus_hold => "false",
+ open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+ i => \dataOut[3]~reg0_q\,
+ devoe => ww_devoe,
+ o => \dataOut[3]~output_o\);
+
+\dataOut[4]~output\ : cycloneive_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+ bus_hold => "false",
+ open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+ i => \dataOut[4]~reg0_q\,
+ devoe => ww_devoe,
+ o => \dataOut[4]~output_o\);
+
+\dataOut[5]~output\ : cycloneive_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+ bus_hold => "false",
+ open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+ i => \dataOut[5]~reg0_q\,
+ devoe => ww_devoe,
+ o => \dataOut[5]~output_o\);
+
+\dataOut[6]~output\ : cycloneive_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+ bus_hold => "false",
+ open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+ i => \dataOut[6]~reg0_q\,
+ devoe => ww_devoe,
+ o => \dataOut[6]~output_o\);
+
+\dataOut[7]~output\ : cycloneive_io_obuf
+-- pragma translate_off
+GENERIC MAP (
+ bus_hold => "false",
+ open_drain_output => "false")
+-- pragma translate_on
+PORT MAP (
+ i => \dataOut[7]~reg0_q\,
+ devoe => ww_devoe,
+ o => \dataOut[7]~output_o\);
+
+\clk~input\ : cycloneive_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+ bus_hold => "false",
+ simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+ i => ww_clk,
+ o => \clk~input_o\);
+
+\dataIn[0]~input\ : cycloneive_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+ bus_hold => "false",
+ simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+ i => ww_dataIn(0),
+ o => \dataIn[0]~input_o\);
+
+\wrEn~input\ : cycloneive_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+ bus_hold => "false",
+ simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+ i => ww_wrEn,
+ o => \wrEn~input_o\);
+
+\dataOut[0]~reg0\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+ is_wysiwyg => "true",
+ power_up => "low")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk~input_o\,
+ d => \dataIn[0]~input_o\,
+ ena => \wrEn~input_o\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ q => \dataOut[0]~reg0_q\);
+
+\dataIn[1]~input\ : cycloneive_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+ bus_hold => "false",
+ simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+ i => ww_dataIn(1),
+ o => \dataIn[1]~input_o\);
+
+\dataOut[1]~reg0\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+ is_wysiwyg => "true",
+ power_up => "low")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk~input_o\,
+ d => \dataIn[1]~input_o\,
+ ena => \wrEn~input_o\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ q => \dataOut[1]~reg0_q\);
+
+\dataIn[2]~input\ : cycloneive_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+ bus_hold => "false",
+ simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+ i => ww_dataIn(2),
+ o => \dataIn[2]~input_o\);
+
+\dataOut[2]~reg0\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+ is_wysiwyg => "true",
+ power_up => "low")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk~input_o\,
+ d => \dataIn[2]~input_o\,
+ ena => \wrEn~input_o\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ q => \dataOut[2]~reg0_q\);
+
+\dataIn[3]~input\ : cycloneive_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+ bus_hold => "false",
+ simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+ i => ww_dataIn(3),
+ o => \dataIn[3]~input_o\);
+
+\dataOut[3]~reg0\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+ is_wysiwyg => "true",
+ power_up => "low")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk~input_o\,
+ d => \dataIn[3]~input_o\,
+ ena => \wrEn~input_o\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ q => \dataOut[3]~reg0_q\);
+
+\dataIn[4]~input\ : cycloneive_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+ bus_hold => "false",
+ simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+ i => ww_dataIn(4),
+ o => \dataIn[4]~input_o\);
+
+\dataOut[4]~reg0\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+ is_wysiwyg => "true",
+ power_up => "low")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk~input_o\,
+ d => \dataIn[4]~input_o\,
+ ena => \wrEn~input_o\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ q => \dataOut[4]~reg0_q\);
+
+\dataIn[5]~input\ : cycloneive_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+ bus_hold => "false",
+ simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+ i => ww_dataIn(5),
+ o => \dataIn[5]~input_o\);
+
+\dataOut[5]~reg0\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+ is_wysiwyg => "true",
+ power_up => "low")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk~input_o\,
+ d => \dataIn[5]~input_o\,
+ ena => \wrEn~input_o\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ q => \dataOut[5]~reg0_q\);
+
+\dataIn[6]~input\ : cycloneive_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+ bus_hold => "false",
+ simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+ i => ww_dataIn(6),
+ o => \dataIn[6]~input_o\);
+
+\dataOut[6]~reg0\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+ is_wysiwyg => "true",
+ power_up => "low")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk~input_o\,
+ d => \dataIn[6]~input_o\,
+ ena => \wrEn~input_o\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ q => \dataOut[6]~reg0_q\);
+
+\dataIn[7]~input\ : cycloneive_io_ibuf
+-- pragma translate_off
+GENERIC MAP (
+ bus_hold => "false",
+ simulate_z_as => "z")
+-- pragma translate_on
+PORT MAP (
+ i => ww_dataIn(7),
+ o => \dataIn[7]~input_o\);
+
+\dataOut[7]~reg0\ : dffeas
+-- pragma translate_off
+GENERIC MAP (
+ is_wysiwyg => "true",
+ power_up => "low")
+-- pragma translate_on
+PORT MAP (
+ clk => \clk~input_o\,
+ d => \dataIn[7]~input_o\,
+ ena => \wrEn~input_o\,
+ devclrn => ww_devclrn,
+ devpor => ww_devpor,
+ q => \dataOut[7]~reg0_q\);
+
+ww_dataOut(0) <= \dataOut[0]~output_o\;
+
+ww_dataOut(1) <= \dataOut[1]~output_o\;
+
+ww_dataOut(2) <= \dataOut[2]~output_o\;
+
+ww_dataOut(3) <= \dataOut[3]~output_o\;
+
+ww_dataOut(4) <= \dataOut[4]~output_o\;
+
+ww_dataOut(5) <= \dataOut[5]~output_o\;
+
+ww_dataOut(6) <= \dataOut[6]~output_o\;
+
+ww_dataOut(7) <= \dataOut[7]~output_o\;
+END structure;
+
+
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/RegisterDemo_20230322091532.sim.vwf b/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/RegisterDemo_20230322091532.sim.vwf
new file mode 100644
index 0000000..20e9aaf
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/RegisterDemo_20230322091532.sim.vwf
@@ -0,0 +1,874 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+
+/*
+Copyright (C) 2020 Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions
+and other software and tools, and any partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Intel Program License
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors. Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+*/
+
+HEADER
+{
+ VERSION = 1;
+ TIME_UNIT = ns;
+ DATA_OFFSET = 0.0;
+ DATA_DURATION = 1000.0;
+ SIMULATION_TIME = 0.0;
+ GRID_PHASE = 0.0;
+ GRID_PERIOD = 10.0;
+ GRID_DUTY_CYCLE = 50;
+}
+
+SIGNAL("clk")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = INPUT;
+ PARENT = "";
+}
+
+SIGNAL("dataIn")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = BUS;
+ WIDTH = 8;
+ LSB_INDEX = 0;
+ DIRECTION = INPUT;
+ PARENT = "";
+}
+
+SIGNAL("dataIn[7]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = INPUT;
+ PARENT = "dataIn";
+}
+
+SIGNAL("dataIn[6]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = INPUT;
+ PARENT = "dataIn";
+}
+
+SIGNAL("dataIn[5]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = INPUT;
+ PARENT = "dataIn";
+}
+
+SIGNAL("dataIn[4]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = INPUT;
+ PARENT = "dataIn";
+}
+
+SIGNAL("dataIn[3]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = INPUT;
+ PARENT = "dataIn";
+}
+
+SIGNAL("dataIn[2]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = INPUT;
+ PARENT = "dataIn";
+}
+
+SIGNAL("dataIn[1]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = INPUT;
+ PARENT = "dataIn";
+}
+
+SIGNAL("dataIn[0]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = INPUT;
+ PARENT = "dataIn";
+}
+
+SIGNAL("dataOut")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = BUS;
+ WIDTH = 8;
+ LSB_INDEX = 0;
+ DIRECTION = OUTPUT;
+ PARENT = "";
+}
+
+SIGNAL("dataOut[7]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "dataOut";
+}
+
+SIGNAL("dataOut[6]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "dataOut";
+}
+
+SIGNAL("dataOut[5]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "dataOut";
+}
+
+SIGNAL("dataOut[4]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "dataOut";
+}
+
+SIGNAL("dataOut[3]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "dataOut";
+}
+
+SIGNAL("dataOut[2]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "dataOut";
+}
+
+SIGNAL("dataOut[1]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "dataOut";
+}
+
+SIGNAL("dataOut[0]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "dataOut";
+}
+
+SIGNAL("wrEn")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = INPUT;
+ PARENT = "";
+}
+
+TRANSITION_LIST("clk")
+{
+ NODE
+ {
+ REPEAT = 1;
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL 0 FOR 20.0;
+ LEVEL 1 FOR 20.0;
+ LEVEL 0 FOR 20.0;
+ LEVEL 1 FOR 20.0;
+ LEVEL 0 FOR 20.0;
+ LEVEL 1 FOR 20.0;
+ LEVEL 0 FOR 20.0;
+ LEVEL 1 FOR 20.0;
+ LEVEL 0 FOR 20.0;
+ LEVEL 1 FOR 20.0;
+ LEVEL 0 FOR 20.0;
+ LEVEL 1 FOR 20.0;
+ LEVEL 0 FOR 20.0;
+ LEVEL 1 FOR 20.0;
+ LEVEL 0 FOR 20.0;
+ LEVEL 1 FOR 20.0;
+ LEVEL 0 FOR 20.0;
+ LEVEL 1 FOR 20.0;
+ LEVEL 0 FOR 20.0;
+ LEVEL 1 FOR 20.0;
+ LEVEL 0 FOR 20.0;
+ LEVEL 1 FOR 20.0;
+ LEVEL 0 FOR 20.0;
+ LEVEL 1 FOR 20.0;
+ LEVEL 0 FOR 20.0;
+ LEVEL 1 FOR 20.0;
+ LEVEL 0 FOR 20.0;
+ LEVEL 1 FOR 20.0;
+ LEVEL 0 FOR 20.0;
+ LEVEL 1 FOR 20.0;
+ LEVEL 0 FOR 20.0;
+ LEVEL 1 FOR 20.0;
+ LEVEL 0 FOR 20.0;
+ LEVEL 1 FOR 20.0;
+ LEVEL 0 FOR 20.0;
+ LEVEL 1 FOR 20.0;
+ LEVEL 0 FOR 20.0;
+ LEVEL 1 FOR 20.0;
+ LEVEL 0 FOR 20.0;
+ LEVEL 1 FOR 20.0;
+ LEVEL 0 FOR 20.0;
+ LEVEL 1 FOR 20.0;
+ LEVEL 0 FOR 20.0;
+ LEVEL 1 FOR 20.0;
+ LEVEL 0 FOR 20.0;
+ LEVEL 1 FOR 20.0;
+ LEVEL 0 FOR 20.0;
+ LEVEL 1 FOR 20.0;
+ LEVEL 0 FOR 20.0;
+ LEVEL 1 FOR 20.0;
+ }
+ }
+}
+
+TRANSITION_LIST("dataIn[7]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL 1 FOR 200.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 120.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 120.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 120.0;
+ LEVEL 1 FOR 40.0;
+ }
+ }
+}
+
+TRANSITION_LIST("dataIn[6]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL 0 FOR 80.0;
+ LEVEL 1 FOR 80.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 120.0;
+ LEVEL 1 FOR 120.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 80.0;
+ LEVEL 0 FOR 120.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 120.0;
+ LEVEL 1 FOR 40.0;
+ }
+ }
+}
+
+TRANSITION_LIST("dataIn[5]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL 0 FOR 80.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 120.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 80.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 80.0;
+ LEVEL 1 FOR 80.0;
+ LEVEL 0 FOR 120.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 80.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 40.0;
+ }
+ }
+}
+
+TRANSITION_LIST("dataIn[4]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL 0 FOR 200.0;
+ LEVEL 1 FOR 160.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 320.0;
+ LEVEL 0 FOR 160.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 80.0;
+ }
+ }
+}
+
+TRANSITION_LIST("dataIn[3]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL 1 FOR 160.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 120.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 80.0;
+ LEVEL 0 FOR 80.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 160.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 120.0;
+ LEVEL 0 FOR 80.0;
+ }
+ }
+}
+
+TRANSITION_LIST("dataIn[2]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL 0 FOR 80.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 120.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 120.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 80.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 80.0;
+ LEVEL 0 FOR 80.0;
+ LEVEL 1 FOR 80.0;
+ }
+ }
+}
+
+TRANSITION_LIST("dataIn[1]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL 1 FOR 80.0;
+ LEVEL 0 FOR 80.0;
+ LEVEL 1 FOR 80.0;
+ LEVEL 0 FOR 80.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 80.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 120.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 40.0;
+ }
+ }
+}
+
+TRANSITION_LIST("dataIn[0]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL 1 FOR 160.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 120.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 160.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 80.0;
+ LEVEL 1 FOR 80.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 40.0;
+ }
+ }
+}
+
+TRANSITION_LIST("dataOut[7]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL 0 FOR 420.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 120.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 220.0;
+ }
+ }
+}
+
+TRANSITION_LIST("dataOut[6]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL 0 FOR 460.0;
+ LEVEL 1 FOR 120.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 80.0;
+ LEVEL 0 FOR 300.0;
+ }
+ }
+}
+
+TRANSITION_LIST("dataOut[5]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL 0 FOR 500.0;
+ LEVEL 1 FOR 80.0;
+ LEVEL 0 FOR 120.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 220.0;
+ }
+ }
+}
+
+TRANSITION_LIST("dataOut[4]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL 0 FOR 420.0;
+ LEVEL 1 FOR 320.0;
+ LEVEL 0 FOR 260.0;
+ }
+ }
+}
+
+TRANSITION_LIST("dataOut[3]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL 0 FOR 420.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 80.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 160.0;
+ LEVEL 0 FOR 220.0;
+ }
+ }
+}
+
+TRANSITION_LIST("dataOut[2]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL 0 FOR 500.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 80.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 220.0;
+ }
+ }
+}
+
+TRANSITION_LIST("dataOut[1]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL 0 FOR 420.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 80.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 120.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 220.0;
+ }
+ }
+}
+
+TRANSITION_LIST("dataOut[0]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL 0 FOR 460.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 40.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 160.0;
+ LEVEL 1 FOR 40.0;
+ LEVEL 0 FOR 220.0;
+ }
+ }
+}
+
+TRANSITION_LIST("wrEn")
+{
+ NODE
+ {
+ REPEAT = 1;
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL 0 FOR 400.0;
+ LEVEL 1 FOR 400.0;
+ LEVEL 0 FOR 200.0;
+ }
+ }
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "wrEn";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Binary;
+ TREE_INDEX = 0;
+ TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "clk";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Binary;
+ TREE_INDEX = 1;
+ TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dataIn";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Binary;
+ TREE_INDEX = 2;
+ TREE_LEVEL = 0;
+ CHILDREN = 3, 4, 5, 6, 7, 8, 9, 10;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dataIn[7]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Binary;
+ TREE_INDEX = 3;
+ TREE_LEVEL = 1;
+ PARENT = 2;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dataIn[6]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Binary;
+ TREE_INDEX = 4;
+ TREE_LEVEL = 1;
+ PARENT = 2;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dataIn[5]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Binary;
+ TREE_INDEX = 5;
+ TREE_LEVEL = 1;
+ PARENT = 2;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dataIn[4]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Binary;
+ TREE_INDEX = 6;
+ TREE_LEVEL = 1;
+ PARENT = 2;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dataIn[3]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Binary;
+ TREE_INDEX = 7;
+ TREE_LEVEL = 1;
+ PARENT = 2;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dataIn[2]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Binary;
+ TREE_INDEX = 8;
+ TREE_LEVEL = 1;
+ PARENT = 2;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dataIn[1]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Binary;
+ TREE_INDEX = 9;
+ TREE_LEVEL = 1;
+ PARENT = 2;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dataIn[0]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Binary;
+ TREE_INDEX = 10;
+ TREE_LEVEL = 1;
+ PARENT = 2;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dataOut";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Binary;
+ TREE_INDEX = 11;
+ TREE_LEVEL = 0;
+ CHILDREN = 12, 13, 14, 15, 16, 17, 18, 19;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dataOut[7]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Binary;
+ TREE_INDEX = 12;
+ TREE_LEVEL = 1;
+ PARENT = 11;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dataOut[6]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Binary;
+ TREE_INDEX = 13;
+ TREE_LEVEL = 1;
+ PARENT = 11;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dataOut[5]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Binary;
+ TREE_INDEX = 14;
+ TREE_LEVEL = 1;
+ PARENT = 11;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dataOut[4]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Binary;
+ TREE_INDEX = 15;
+ TREE_LEVEL = 1;
+ PARENT = 11;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dataOut[3]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Binary;
+ TREE_INDEX = 16;
+ TREE_LEVEL = 1;
+ PARENT = 11;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dataOut[2]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Binary;
+ TREE_INDEX = 17;
+ TREE_LEVEL = 1;
+ PARENT = 11;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dataOut[1]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Binary;
+ TREE_INDEX = 18;
+ TREE_LEVEL = 1;
+ PARENT = 11;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "dataOut[0]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Binary;
+ TREE_INDEX = 19;
+ TREE_LEVEL = 1;
+ PARENT = 11;
+}
+
+TIME_BAR
+{
+ TIME = 0;
+ MASTER = TRUE;
+}
+;
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/RegisterDemo_modelsim.xrf b/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/RegisterDemo_modelsim.xrf
new file mode 100644
index 0000000..71f73e4
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/RegisterDemo_modelsim.xrf
@@ -0,0 +1,34 @@
+vendor_name = ModelSim
+source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/Register8.vhd
+source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_b.vhd
+source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_p.vhd
+source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_b.vhd
+source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_p.vhd
+source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.cbx.xml
+design_name = Register8
+instance = comp, \dataOut[0]~output\, dataOut[0]~output, Register8, 1
+instance = comp, \dataOut[1]~output\, dataOut[1]~output, Register8, 1
+instance = comp, \dataOut[2]~output\, dataOut[2]~output, Register8, 1
+instance = comp, \dataOut[3]~output\, dataOut[3]~output, Register8, 1
+instance = comp, \dataOut[4]~output\, dataOut[4]~output, Register8, 1
+instance = comp, \dataOut[5]~output\, dataOut[5]~output, Register8, 1
+instance = comp, \dataOut[6]~output\, dataOut[6]~output, Register8, 1
+instance = comp, \dataOut[7]~output\, dataOut[7]~output, Register8, 1
+instance = comp, \clk~input\, clk~input, Register8, 1
+instance = comp, \dataIn[0]~input\, dataIn[0]~input, Register8, 1
+instance = comp, \wrEn~input\, wrEn~input, Register8, 1
+instance = comp, \dataOut[0]~reg0\, dataOut[0]~reg0, Register8, 1
+instance = comp, \dataIn[1]~input\, dataIn[1]~input, Register8, 1
+instance = comp, \dataOut[1]~reg0\, dataOut[1]~reg0, Register8, 1
+instance = comp, \dataIn[2]~input\, dataIn[2]~input, Register8, 1
+instance = comp, \dataOut[2]~reg0\, dataOut[2]~reg0, Register8, 1
+instance = comp, \dataIn[3]~input\, dataIn[3]~input, Register8, 1
+instance = comp, \dataOut[3]~reg0\, dataOut[3]~reg0, Register8, 1
+instance = comp, \dataIn[4]~input\, dataIn[4]~input, Register8, 1
+instance = comp, \dataOut[4]~reg0\, dataOut[4]~reg0, Register8, 1
+instance = comp, \dataIn[5]~input\, dataIn[5]~input, Register8, 1
+instance = comp, \dataOut[5]~reg0\, dataOut[5]~reg0, Register8, 1
+instance = comp, \dataIn[6]~input\, dataIn[6]~input, Register8, 1
+instance = comp, \dataOut[6]~reg0\, dataOut[6]~reg0, Register8, 1
+instance = comp, \dataIn[7]~input\, dataIn[7]~input, Register8, 1
+instance = comp, \dataOut[7]~reg0\, dataOut[7]~reg0, Register8, 1
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/transcript b/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/transcript
new file mode 100644
index 0000000..0b7a78d
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/transcript
@@ -0,0 +1,47 @@
+# do RegisterDemo.do
+# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
+# Start time: 09:15:31 on Mar 22,2023
+# vcom -work work RegisterDemo.vho
+# -- Loading package STANDARD
+# -- Loading package TEXTIO
+# -- Loading package std_logic_1164
+# -- Loading package VITAL_Timing
+# -- Loading package VITAL_Primitives
+# -- Loading package dffeas_pack
+# -- Loading package altera_primitives_components
+# -- Loading package cycloneive_atom_pack
+# -- Loading package cycloneive_components
+# -- Compiling entity Register8
+# -- Compiling architecture structure of Register8
+# End time: 09:15:32 on Mar 22,2023, Elapsed time: 0:00:01
+# Errors: 0, Warnings: 0
+# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
+# Start time: 09:15:32 on Mar 22,2023
+# vcom -work work Register8.vwf.vht
+# -- Loading package STANDARD
+# -- Loading package TEXTIO
+# -- Loading package std_logic_1164
+# -- Compiling entity Register8_vhd_vec_tst
+# -- Compiling architecture Register8_arch of Register8_vhd_vec_tst
+# End time: 09:15:32 on Mar 22,2023, Elapsed time: 0:00:00
+# Errors: 0, Warnings: 0
+# vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.Register8_vhd_vec_tst
+# Start time: 09:15:32 on Mar 22,2023
+# Loading std.standard
+# Loading std.textio(body)
+# Loading ieee.std_logic_1164(body)
+# Loading work.register8_vhd_vec_tst(register8_arch)
+# Loading ieee.vital_timing(body)
+# Loading ieee.vital_primitives(body)
+# Loading altera.dffeas_pack
+# Loading altera.altera_primitives_components
+# Loading cycloneive.cycloneive_atom_pack(body)
+# Loading cycloneive.cycloneive_components
+# Loading work.register8(structure)
+# Loading ieee.std_logic_arith(body)
+# Loading cycloneive.cycloneive_io_obuf(arch)
+# Loading cycloneive.cycloneive_io_ibuf(arch)
+# Loading altera.dffeas(vital_dffeas)
+# after#31
+# End time: 09:15:32 on Mar 22,2023, Elapsed time: 0:00:00
+# Errors: 0, Warnings: 0
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/vwf_sim_transcript b/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/vwf_sim_transcript
new file mode 100644
index 0000000..87f116b
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/vwf_sim_transcript
@@ -0,0 +1,76 @@
+Determining the location of the ModelSim executable...
+
+Using: /home/tiagorg/intelFPGA_lite/20.1/modelsim_ase/linuxaloem/
+
+To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options
+Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used.
+
+**** Generating the ModelSim Testbench ****
+
+quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off RegisterDemo -c RegisterDemo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/Register8.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/Register8.vwf.vht"
+
+Info: *******************************************************************Info: Running Quartus Prime EDA Netlist Writer Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Info: Copyright (C) 2020 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Wed Mar 22 09:15:27 2023Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off RegisterDemo -c RegisterDemo --vector_source=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/Register8.vwf --testbench_file=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/Register8.vwf.vhtInfo (119006): Selected device EP4CE115F29C7 for design "RegisterDemo"Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Completed successfully.
+
+**** Generating the functional simulation netlist ****
+
+quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/" RegisterDemo -c RegisterDemo
+
+Info: *******************************************************************Info: Running Quartus Prime EDA Netlist Writer Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Info: Copyright (C) 2020 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Wed Mar 22 09:15:29 2023Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/ RegisterDemo -c RegisterDemoInfo (119006): Selected device EP4CE115F29C7 for design "RegisterDemo"Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.Info (204019): Generated file RegisterDemo.vho in folder "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim//" for EDA simulation toolInfo: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning Info: Peak virtual memory: 615 megabytes Info: Processing ended: Wed Mar 22 09:15:30 2023 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01
+Completed successfully.
+
+**** Generating the ModelSim .do script ****
+
+/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/RegisterDemo.do generated.
+
+Completed successfully.
+
+**** Running the ModelSim simulation ****
+
+/home/tiagorg/intelFPGA_lite/20.1/modelsim_ase/linuxaloem//vsim -c -do RegisterDemo.do
+
+Reading pref.tcl
+# 2020.1
+# do RegisterDemo.do
+# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
+# Start time: 09:15:31 on Mar 22,2023# vcom -work work RegisterDemo.vho
+# -- Loading package STANDARD
+# -- Loading package TEXTIO
+# -- Loading package std_logic_1164
+# -- Loading package VITAL_Timing
+# -- Loading package VITAL_Primitives
+# -- Loading package dffeas_pack# -- Loading package altera_primitives_components
+# -- Loading package cycloneive_atom_pack
+# -- Loading package cycloneive_components
+# -- Compiling entity Register8
+# -- Compiling architecture structure of Register8
+# End time: 09:15:32 on Mar 22,2023, Elapsed time: 0:00:01
+# Errors: 0, Warnings: 0
+# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
+# Start time: 09:15:32 on Mar 22,2023# vcom -work work Register8.vwf.vht
+# -- Loading package STANDARD
+# -- Loading package TEXTIO
+# -- Loading package std_logic_1164
+# -- Compiling entity Register8_vhd_vec_tst# -- Compiling architecture Register8_arch of Register8_vhd_vec_tst
+# End time: 09:15:32 on Mar 22,2023, Elapsed time: 0:00:00
+# Errors: 0, Warnings: 0
+# vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.Register8_vhd_vec_tst # Start time: 09:15:32 on Mar 22,2023# Loading std.standard# Loading std.textio(body)# Loading ieee.std_logic_1164(body)# Loading work.register8_vhd_vec_tst(register8_arch)# Loading ieee.vital_timing(body)# Loading ieee.vital_primitives(body)# Loading altera.dffeas_pack# Loading altera.altera_primitives_components# Loading cycloneive.cycloneive_atom_pack(body)# Loading cycloneive.cycloneive_components# Loading work.register8(structure)# Loading ieee.std_logic_arith(body)# Loading cycloneive.cycloneive_io_obuf(arch)# Loading cycloneive.cycloneive_io_ibuf(arch)# Loading altera.dffeas(vital_dffeas)
+# after#31
+# End time: 09:15:32 on Mar 22,2023, Elapsed time: 0:00:00# Errors: 0, Warnings: 0
+Completed successfully.
+
+**** Converting ModelSim VCD to vector waveform ****
+
+Reading /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/Register8.vwf...
+
+Reading /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/RegisterDemo.msim.vcd...
+
+Processing channel transitions...
+
+Writing the resulting VWF to /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/RegisterDemo_20230322091532.sim.vwf
+
+Finished VCD to VWF conversion.
+
+Completed successfully.
+
+All completed.
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/work/_info b/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/work/_info
new file mode 100644
index 0000000..e49f4d7
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diff --git a/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/work/_lib.qdb b/1ano/2semestre/lsd/pratica04/RegisterDemo/simulation/qsim/work/_lib.qdb
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new file mode 100644
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