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[AC2] Aula03 Part2 finished 

Signed-off-by: TiagoRG <tiago.rgarcia@ua.pt>
This commit is contained in:
Tiago Garcia 2024-03-01 22:07:45 +00:00
parent a02118939d
commit 2dde2e5059
Signed by: TiagoRG
GPG Key ID: DFCD48E3F420DB42
7 changed files with 401 additions and 3 deletions
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3
2ano/2semestre/ac2/aula03/part2.s → 2ano/2semestre/ac2/aula03/part2-1.s
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@ -47,9 +47,6 @@ delay:
syscall
move $t6, $v0
# 20,000,000 cycles = 1 second = 1 Hz
# 4,000,000 cycles = 0.2 second = 5 Hz
# 2,000,000 cycles = 0.1 second = 10 Hz
blt $t6, 20000000, delay
addi $t0, $t0, 1 # incrementa o contador

55
2ano/2semestre/ac2/aula03/part2-2.s Normal file
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@ -0,0 +1,55 @@
.equ ADDR_BASE, 0xBF88
.equ TRISB, 0x6040
.equ PORTB, 0x6050
.equ LATB, 0x6060
.equ TRISC, 0x6080
.equ PORTC, 0x6090
.equ LATC, 0x60A0
.equ TRISD, 0x60C0
.equ PORTD, 0x60D0
.equ LATD, 0x60E0
.equ TRISE, 0x6100
.equ PORTE, 0x6110
.equ LATE, 0x6120
.equ READ_CORE_TIMER, 11
.equ RESET_CORE_TIMER, 12
.data
.text
.globl main
# Mapa de registos
# $t7: endereço base periféricos
# $t0: contador
main:
lui $t7, ADDR_BASE
lw $t0, TRISE($t7)
andi $t0, $t0, 0xFFE1 # 1111 1111 1110 0001 (isola bits 4-1)
sw $t0, TRISE($t7) # Configura RE4-RE1 como output
li $t0, 0 # Iniciar contagem
loop:
lw $t1, LATE($t7)
andi $t1, $t1, 0xFFE1 # 1111 1111 1110 0001 (reset bits 4-1)
sll $t2, $t0, 1 # shift do contador para os bits 4-1
or $t1, $t1, $t2 # merge contador com valor do LATE
sw $t1, LATE($t7) # atualiza valor do LATE
li $v0, RESET_CORE_TIMER
syscall
delay:
li $v0, READ_CORE_TIMER
syscall
move $t6, $v0
blt $t6, 5000000, delay
addiu $t0, $t0, -1 # decrementa o contador
andi $t0, $t0, 0x000F # limita o contador com modulo 16
j loop

69
2ano/2semestre/ac2/aula03/part2-3.s Normal file
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@ -0,0 +1,69 @@
.equ ADDR_BASE, 0xBF88
.equ TRISB, 0x6040
.equ PORTB, 0x6050
.equ LATB, 0x6060
.equ TRISC, 0x6080
.equ PORTC, 0x6090
.equ LATC, 0x60A0
.equ TRISD, 0x60C0
.equ PORTD, 0x60D0
.equ LATD, 0x60E0
.equ TRISE, 0x6100
.equ PORTE, 0x6110
.equ LATE, 0x6120
.equ READ_CORE_TIMER, 11
.equ RESET_CORE_TIMER, 12
.data
.text
.globl main
# Mapa de registos
# $t7: endereço base periféricos
# $t0: contador
main:
lui $t7, ADDR_BASE
lw $t0, TRISE($t7)
andi $t0, $t0, 0xFFE1 # 1111 1111 1110 0001 (isola bits 4-1)
sw $t0, TRISE($t7) # Configura RE4-RE1 como output
lw $t1, TRISB($t7)
ori $t1, $t1, 0x0008 # 0000 0000 0000 0010 (isola bit 1)
sw $t1, TRISB($t7) # Configura RB3 como input
li $t0, 0 # Iniciar contagem
loop:
lw $t2, LATE($t7)
andi $t2, $t2, 0xFFE1 # 1111 1111 1110 0001 (reset bits 4-1)
sll $t3, $t0, 1 # shift do contador para os bits 4-1
or $t2, $t2, $t3 # merge contador com valor do LATE
sw $t2, LATE($t7) # atualiza valor do LATE
li $v0, RESET_CORE_TIMER
syscall
delay:
li $v0, READ_CORE_TIMER
syscall
move $t6, $v0
blt $t6, 10000000, delay
if:
lw $t2, PORTB($t7)
andi $t2, $t2, 0x0008 # obtem posição do switch 3
beqz $t2, else # incrementa se bit = 1, decrementa de bit = 0
addiu $t0, $t0, 1 # incrementa o contador
j endif
else:
addiu $t0, $t0, -1 # decrementa o contador
endif:
andi $t0, $t0, 0x000F # limita o contador com modulo 16
j loop

77
2ano/2semestre/ac2/aula03/part2-4.s Normal file
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@ -0,0 +1,77 @@
.equ ADDR_BASE, 0xBF88
.equ TRISB, 0x6040
.equ PORTB, 0x6050
.equ LATB, 0x6060
.equ TRISC, 0x6080
.equ PORTC, 0x6090
.equ LATC, 0x60A0
.equ TRISD, 0x60C0
.equ PORTD, 0x60D0
.equ LATD, 0x60E0
.equ TRISE, 0x6100
.equ PORTE, 0x6110
.equ LATE, 0x6120
.equ READ_CORE_TIMER, 11
.equ RESET_CORE_TIMER, 12
.data
.text
.globl main
# Mapa de registos
# $t7: endereço base periféricos
# $t0: contador
main:
lui $t7, ADDR_BASE
lw $t0, TRISE($t7)
andi $t0, $t0, 0xFFE1 # 1111 1111 1110 0001 (isola bits 4-1)
sw $t0, TRISE($t7) # Configura RE4-RE1 como output
lw $t1, TRISB($t7)
ori $t1, $t1, 0x0002 # 0000 0000 0000 0010 (isola bit 1)
sw $t1, TRISB($t7) # Configura RB1 como input
li $t0, 0x0001 # Iniciar contagem
loop:
lw $t2, LATE($t7)
andi $t2, $t2, 0xFFE1 # 1111 1111 1110 0001 (reset bits 4-1)
sll $t3, $t0, 1 # shift do contador para os bits 4-1
or $t2, $t2, $t3 # merge contador com valor do LATE
sw $t2, LATE($t7) # atualiza valor do LATE
li $v0, RESET_CORE_TIMER
syscall
delay:
li $v0, READ_CORE_TIMER
syscall
move $t6, $v0
blt $t6, 6666666, delay
switch_check:
lw $t2, PORTB($t7)
andi $t2, $t2, 0x0002 # obtem posição do switch 1
beqz $t2, shift_right # shift_left se bit = 1, shift_right de bit = 0
shift_left:
sll $t0, $t0, 1
andi $t5, $t0, 0x000F
bnez $t5, sll_else
li $t0, 0x0001
sll_else:
j switch_end
shift_right:
srl $t0, $t0, 1
bnez $t0, switch_end
li $t0, 0x0008
switch_end:
j loop

60
2ano/2semestre/ac2/aula03/part2-5.s Normal file
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@ -0,0 +1,60 @@
.equ ADDR_BASE, 0xBF88
.equ TRISB, 0x6040
.equ PORTB, 0x6050
.equ LATB, 0x6060
.equ TRISC, 0x6080
.equ PORTC, 0x6090
.equ LATC, 0x60A0
.equ TRISD, 0x60C0
.equ PORTD, 0x60D0
.equ LATD, 0x60E0
.equ TRISE, 0x6100
.equ PORTE, 0x6110
.equ LATE, 0x6120
.equ READ_CORE_TIMER, 11
.equ RESET_CORE_TIMER, 12
.data
.text
.globl main
# Mapa de registos
# $t7: endereço base periféricos
# $t0: contador
main:
lui $t7, ADDR_BASE
lw $t0, TRISE($t7)
andi $t0, $t0, 0xFFE1 # 1111 1111 1110 0001 (isola bits 4-1)
sw $t0, TRISE($t7) # Configura RE4-RE1 como output
li $t0, 0x0001 # Iniciar contagem
loop:
lw $t2, LATE($t7)
andi $t2, $t2, 0xFFE1 # 1111 1111 1110 0001 (reset bits 4-1)
sll $t3, $t0, 1 # shift do contador para os bits 4-1
or $t2, $t2, $t3 # merge contador com valor do LATE
sw $t2, LATE($t7) # atualiza valor do LATE
li $v0, RESET_CORE_TIMER
syscall
delay:
li $v0, READ_CORE_TIMER
syscall
move $t6, $v0
blt $t6, 13333333, delay
lw $t4, LATE($t7) # ler valor dos leds
andi $t4, $t4, 0x0010 # isolar bit 4
srl $t4, $t4, 4 # colocar bit na posição menos significativa para o contador
xori $t4, $t4, 0x0001 # negar bit
sll $t0, $t0, 1 # shift left do contador
or $t0, $t0, $t4 # colocar bit lido no contador
j loop

60
2ano/2semestre/ac2/aula03/part2-6.s Normal file
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@ -0,0 +1,60 @@
.equ ADDR_BASE, 0xBF88
.equ TRISB, 0x6040
.equ PORTB, 0x6050
.equ LATB, 0x6060
.equ TRISC, 0x6080
.equ PORTC, 0x6090
.equ LATC, 0x60A0
.equ TRISD, 0x60C0
.equ PORTD, 0x60D0
.equ LATD, 0x60E0
.equ TRISE, 0x6100
.equ PORTE, 0x6110
.equ LATE, 0x6120
.equ READ_CORE_TIMER, 11
.equ RESET_CORE_TIMER, 12
.data
.text
.globl main
# Mapa de registos
# $t7: endereço base periféricos
# $t0: contador
main:
lui $t7, ADDR_BASE
lw $t0, TRISE($t7)
andi $t0, $t0, 0xFFE1 # 1111 1111 1110 0001 (isola bits 4-1)
sw $t0, TRISE($t7) # Configura RE4-RE1 como output
li $t0, 0x0010 # Iniciar contagem
loop:
lw $t2, LATE($t7)
andi $t2, $t2, 0xFFE1 # 1111 1111 1110 0001 (reset bits 4-1)
sll $t3, $t0, 1 # shift do contador para os bits 4-1
or $t2, $t2, $t3 # merge contador com valor do LATE
sw $t2, LATE($t7) # atualiza valor do LATE
li $v0, RESET_CORE_TIMER
syscall
delay:
li $v0, READ_CORE_TIMER
syscall
move $t6, $v0
blt $t6, 13333333, delay
lw $t4, LATE($t7)
andi $t4, $t4, 0x0002
sll $t4, $t4, 2
xori $t4, $t4, 0x0008
srl $t0, $t0, 1
or $t0, $t0, $t4
j loop

80
2ano/2semestre/ac2/aula03/part2-7.s Normal file
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@ -0,0 +1,80 @@
.equ ADDR_BASE, 0xBF88
.equ TRISB, 0x6040
.equ PORTB, 0x6050
.equ LATB, 0x6060
.equ TRISC, 0x6080
.equ PORTC, 0x6090
.equ LATC, 0x60A0
.equ TRISD, 0x60C0
.equ PORTD, 0x60D0
.equ LATD, 0x60E0
.equ TRISE, 0x6100
.equ PORTE, 0x6110
.equ LATE, 0x6120
.equ READ_CORE_TIMER, 11
.equ RESET_CORE_TIMER, 12
.data
.text
.globl main
# Mapa de registos
# $t7: endereço base periféricos
# $t0: contador
main:
lui $t7, ADDR_BASE
lw $t0, TRISE($t7)
andi $t0, $t0, 0xFFE1 # 1111 1111 1110 0001 (isola bits 4-1)
sw $t0, TRISE($t7) # Configura RE4-RE1 como output
lw $t1, TRISB($t7)
ori $t1, $t1, 0x0004 # 0000 0000 0000 0010 (isola bit 1)
sw $t1, TRISB($t7) # Configura RB1 como input
li $t0, 0x0010 # Iniciar contagem
loop:
lw $t2, LATE($t7)
andi $t2, $t2, 0xFFE1 # 1111 1111 1110 0001 (reset bits 4-1)
sll $t3, $t0, 1 # shift do contador para os bits 4-1
or $t2, $t2, $t3 # merge contador com valor do LATE
sw $t2, LATE($t7) # atualiza valor do LATE
li $v0, RESET_CORE_TIMER
syscall
delay:
li $v0, READ_CORE_TIMER
syscall
move $t6, $v0
blt $t6, 13333333, delay
switch_check:
lw $t6, PORTB($t7)
andi $t6, $t6, 0x0004 # 0000 0000 0000 0100 (isola bit 3)
lw $t4, LATE($t7)
beqz $t6, move_right
move_left:
andi $t4, $t4, 0x0010
srl $t4, $t4, 4
xori $t4, $t4, 0x0001
sll $t0, $t0, 1
or $t0, $t0, $t4
j switch_end
move_right:
andi $t4, $t4, 0x0002
sll $t4, $t4, 2
xori $t4, $t4, 0x0008
srl $t0, $t0, 1
or $t0, $t0, $t4
switch_end:
j loop