diff --git a/2ano/2semestre/ac2/aula03/AC2-P-Aula03.pdf b/2ano/2semestre/ac2/aula03/AC2-P-Aula03.pdf
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diff --git a/2ano/2semestre/ac2/aula03/part1-ex1.s b/2ano/2semestre/ac2/aula03/part1-ex1.s
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+	.equ	ADDR_BASE, 0xBF88
+	.equ	TRISB, 0x6040
+	.equ	PORTB, 0x6050
+	.equ	TRISE, 0x6100
+	.equ	LATE,  0x6120
+
+	.data
+	.text
+	.globl main
+
+main:
+	lui	$t7, ADDR_BASE
+
+	lw	$t0, TRISB($t7)
+	ori	$t0, $t0, 0x0001		# 0000 0000 0000 0001 (isola bit 0)
+	sw	$t0, TRISB($t7)			# Configurar RB0 como input
+
+	lw	$t0, TRISE($t7)
+	andi	$t0, $t0, 0xFFFE		# 1111 1111 1111 1110 (isola bit 0)
+	sw	$t0, TRISE($t7)			# Configurar RE0 como output
+
+loop:
+	lw	$t0, PORTB($t7)
+	andi	$t0, $t0, 0x0001		# 0000 0000 0000 0001 (isola bit 0)
+	xori	$t0, $t0, 0x0001		# Negar RB0
+	lw	$t1, LATE($t7)
+	andi	$t1, $t1, 0xFFFE		# 1111 1111 1111 1110 (isola bit 0)
+
+	or	$t1, $t1, $t0
+	sw	$t1, LATE($t7)
+	j	loop
+
+	jr	$ra
diff --git a/2ano/2semestre/ac2/aula03/part1-ex3.s b/2ano/2semestre/ac2/aula03/part1-ex3.s
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+++ b/2ano/2semestre/ac2/aula03/part1-ex3.s
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+	.equ	ADDR_BASE, 0xBF88
+	.equ	TRISD, 0x60C0
+	.equ	PORTD, 0x60D0
+	.equ	TRISE, 0x6100
+	.equ	LATE,  0x6120
+
+	.data
+	.text
+	.globl main
+
+main:
+	lui	$t7, ADDR_BASE
+
+	lw	$t0, TRISD($t7)
+	ori	$t0, $t0, 0x0100		# 0000 0001 0000 0000 (isola bit 8)
+	sw	$t0, TRISD($t7)			# Configurar RD8 como input
+
+	lw	$t0, TRISE($t7)
+	andi	$t0, $t0, 0xFFFE		# 1111 1111 1111 1110 (isola bit 0)
+	sw	$t0, TRISE($t7)			# Configurar RE0 como output
+
+loop:
+	lw	$t0, PORTD($t7)
+	andi	$t0, $t0, 0x0100		# 0000 0001 0000 0000 (isola bit 8)
+	srl	$t0, $t0, 8			# Necessário colocar o bit lido na posição do bit 0
+	xori	$t0, $t0, 0xFFFF		# Negar RD8
+	lw	$t1, LATE($t7)
+	andi	$t1, $t1, 0xFFFE		# 1111 1111 1111 1110 (isola bit 0)
+
+	or	$t1, $t1, $t0
+	sw	$t1, LATE($t7)
+	j	loop
+
+	jr	$ra
diff --git a/2ano/2semestre/ac2/aula03/part2.s b/2ano/2semestre/ac2/aula03/part2.s
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+	.equ	ADDR_BASE, 0xBF88
+	.equ	TRISB, 0x6040
+	.equ	PORTB, 0x6050
+	.equ	LATB,  0x6060
+	.equ	TRISC, 0x6080
+	.equ	PORTC, 0x6090
+	.equ	LATC,  0x60A0
+	.equ	TRISD, 0x60C0
+	.equ	PORTD, 0x60D0
+	.equ	LATD,  0x60E0
+	.equ	TRISE, 0x6100
+	.equ	PORTE, 0x6110
+	.equ	LATE,  0x6120
+
+	.equ READ_CORE_TIMER, 11
+	.equ RESET_CORE_TIMER, 12
+
+	.data
+	.text
+	.globl main
+
+# Mapa de registos
+# $t7:	endereço base periféricos
+# $t0:	contador
+
+main:
+	lui	$t7, ADDR_BASE
+	
+	lw	$t0, TRISE($t7)
+	andi	$t0, $t0, 0xFFE1		# 1111 1111 1110 0001 (isola bits 4-1)
+	sw	$t0, TRISE($t7)			# Configura RE4-RE1 como output
+
+	li	$t0, 0				# Iniciar contagem
+
+loop:
+	lw	$t1, LATE($t7)
+	andi	$t1, $t1, 0xFFE1		# 1111 1111 1110 0001 (reset bits 4-1)
+	sll	$t2, $t0, 1			# shift do contador para os bits 4-1
+	or	$t1, $t1, $t2			# merge contador com valor do LATE
+	sw	$t1, LATE($t7)			# atualiza valor do LATE
+
+	li	$v0, RESET_CORE_TIMER
+	syscall
+
+delay:
+	li	$v0, READ_CORE_TIMER
+	syscall
+	move	$t6, $v0
+
+	# 20,000,000 cycles = 1 second = 1 Hz
+	# 4,000,000 cycles = 0.2 second = 5 Hz
+	# 2,000,000 cycles = 0.1 second = 10 Hz
+	blt	$t6, 20000000, delay
+
+	addi	$t0, $t0, 1			# incrementa o contador
+	andi	$t0, $t0, 0x000F		# limita o contador com modulo 16
+	j	loop
+