[LSD] CombShiftUnit_Demo added (pratica06 - part3)

1ano/2semestre/lsd/pratica06/CombShiftUnit_Demo/CombShiftUnit.vhd

@@ -0,0 +1,50 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity CombShiftUnit is
+	port
+	(
+		clk      : in  std_logic;
+		dataIn   : in  std_logic_vector(7 downto 0);
+		loadEn, rotate, dirLeft, shArith : in  std_logic;
+		shAmount : in  std_logic_vector(2 downto 0);
+		dataOut  : out std_logic_vector(7 downto 0)
+	);
+end CombShiftUnit;
+
+architecture Behavioral of CombShiftUnit is
+	signal s_shiftReg : std_logic_vector(7 downto 0);
+begin
+	process (clk)
+	begin
+		if (falling_edge(clk)) then
+			if (loaden = '1') then 
+				s_shiftReg <= datain;
+			
+			elsif (rotate = '1') then 
+				if (dirleft = '1') then 
+					s_shiftReg <= std_logic_vector( rotate_left ( unsigned(s_shiftReg), to_integer(unsigned(shAmount)) ) );
+				else 
+					s_shiftReg <= std_logic_vector( rotate_right( unsigned(s_shiftReg), to_integer(unsigned(shAmount)) ) ); 
+				end if;
+			
+			elsif (sharith = '1') then 
+				if (dirleft = '1') then 
+					s_shiftReg <= std_logic_vector( shift_left (    signed(s_shiftReg), to_integer(unsigned(shAmount)) ) );
+				else 
+					s_shiftReg <= std_logic_vector( shift_right(    signed(s_shiftReg), to_integer(unsigned(shAmount)) ) ); 
+				end if;
+			
+			else
+				if (dirleft = '1') then 
+					s_shiftReg <= std_logic_vector( shift_left (  unsigned(s_shiftReg), to_integer(unsigned(shAmount)) ) ); 
+				else 
+					s_shiftReg <= std_logic_vector( shift_right(  unsigned(s_shiftReg), to_integer(unsigned(shAmount)) ) ); 
+				end if;
+			end if;
+		end if;
+	end process;
+	
+	dataOut <= s_shiftReg;
+end Behavioral;

1ano/2semestre/lsd/pratica06/CombShiftUnit_Demo/CombShiftUnit_Demo.vhd

@@ -0,0 +1,34 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity CombShiftUnit_Demo is
+	port
+	(
+		CLOCK_50 : in  std_logic;
+		SW       : in  std_logic_vector(17 downto 0);
+		KEY      : in  std_logic_vector(2 downto 0);
+		LEDR     : out std_logic_vector(7 downto 0)
+	);
+end CombShiftUnit_Demo;
+
+architecture Shell of CombShiftUnit_Demo is
+	signal clk : std_logic;
+begin
+	freq : entity work.FreqDivider(Behavioral)
+	generic map (divFactor => 12_500_000)
+	port map (clkIn => CLOCK_50, clkOut => clk);
+
+	core : entity work.CombShiftUnit(Behavioral)
+	port map
+	(
+		clk      => clk,
+		dataIn   => SW(7 downto 0),
+		loadEn   => SW(8),
+		rotate   => KEY(0),
+		dirLeft  => KEY(1),
+		shArith  => KEY(2),
+		shAmount => SW(17 downto 15),
+		dataOut  => LEDR
+	);
+end Shell;

1ano/2semestre/lsd/pratica06/CombShiftUnit_Demo/FreqDivider.vhd

@@ -0,0 +1,33 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity FreqDivider is
+	generic(divFactor : positive := 10);
+	port
+	(
+		clkIn  : in  std_logic;
+		clkOut : out std_logic
+	);
+end FreqDivider;
+
+architecture Behavioral of FreqDivider is
+	subtype TCounter is natural range 0 to divFactor - 1;
+	signal s_divCounter : TCounter := 0;
+begin
+    assert(divFactor >= 2);
+	process(clkIn)
+	begin
+		if (rising_edge(clkIn)) then
+			if (s_divCounter >= (divFactor - 1)) then
+				clkOut <= '0';
+				s_divCounter <= 0;
+			else
+				if (s_divCounter = (divFactor / 2 - 1)) then
+					clkOut <= '1';
+				end if;
+				s_divCounter <= s_divCounter + 1;
+			end if;
+		end if;
+	end process;
+end Behavioral;