TiagoRG
/
uaveiro-leci
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Some quartus projects added

This commit is contained in:
TiagoRG 2023-01-11 18:07:46 +00:00
parent 0e7c62132a
commit 095c238d66
404 changed files with 47832 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

543
1ano/isd/quartus-projects/AdderDemo/Adder.bdf Normal file
View File

@ -0,0 +1,543 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "graphic" (version "1.4"))
(pin
(input)
(rect 0 288 168 304)
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
(text "Cin" (rect 5 0 22 11)(font "Arial" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
)
(pin
(input)
(rect 0 224 168 240)
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
(text "A[3..0]" (rect 5 0 39 13)(font "Intel Clear" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
)
(pin
(input)
(rect 0 208 168 224)
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
(text "B[3..0]" (rect 5 0 36 11)(font "Arial" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
)
(pin
(output)
(rect 728 288 904 304)
(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
(text "Cout" (rect 90 0 114 11)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
(line (pt 52 4)(pt 78 4))
(line (pt 52 12)(pt 78 12))
(line (pt 52 12)(pt 52 4))
(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
)
(pin
(output)
(rect 728 368 904 384)
(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
(text "S" (rect 90 0 99 11)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
(line (pt 52 4)(pt 78 4))
(line (pt 52 12)(pt 78 12))
(line (pt 52 12)(pt 52 4))
(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
)
(pin
(output)
(rect 808 328 984 344)
(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
(text "Overflow" (rect 90 0 134 11)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
(line (pt 52 4)(pt 78 4))
(line (pt 52 12)(pt 78 12))
(line (pt 52 12)(pt 52 4))
(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
)
(symbol
(rect 200 264 296 360)
(text "AdderDemo" (rect 5 0 75 15)(font "Intel Clear" (font_size 8)))
(text "inst" (rect 8 79 28 92)(font "Intel Clear" ))
(port
(pt 0 32)
(input)
(text "Cin" (rect 0 0 20 15)(font "Intel Clear" (font_size 8)))
(text "Cin" (rect 21 27 41 42)(font "Intel Clear" (font_size 8)))
(line (pt 0 32)(pt 16 32))
)
(port
(pt 0 48)
(input)
(text "A" (rect 0 0 9 15)(font "Intel Clear" (font_size 8)))
(text "A" (rect 21 43 30 58)(font "Intel Clear" (font_size 8)))
(line (pt 0 48)(pt 16 48))
)
(port
(pt 0 64)
(input)
(text "B" (rect 0 0 9 15)(font "Intel Clear" (font_size 8)))
(text "B" (rect 21 59 30 74)(font "Intel Clear" (font_size 8)))
(line (pt 0 64)(pt 16 64))
)
(port
(pt 96 32)
(output)
(text "Cout" (rect 0 0 28 15)(font "Intel Clear" (font_size 8)))
(text "Cout" (rect 47 27 75 42)(font "Intel Clear" (font_size 8)))
(line (pt 96 32)(pt 80 32))
)
(port
(pt 96 48)
(output)
(text "S" (rect 0 0 9 15)(font "Intel Clear" (font_size 8)))
(text "S" (rect 66 43 75 58)(font "Intel Clear" (font_size 8)))
(line (pt 96 48)(pt 80 48))
)
(drawing
(rectangle (rect 16 16 80 80))
)
)
(symbol
(rect 336 264 432 360)
(text "AdderDemo" (rect 5 0 75 15)(font "Intel Clear" (font_size 8)))
(text "inst3" (rect 8 79 32 92)(font "Intel Clear" ))
(port
(pt 0 32)
(input)
(text "Cin" (rect 0 0 20 15)(font "Intel Clear" (font_size 8)))
(text "Cin" (rect 21 27 41 42)(font "Intel Clear" (font_size 8)))
(line (pt 0 32)(pt 16 32))
)
(port
(pt 0 48)
(input)
(text "A" (rect 0 0 9 15)(font "Intel Clear" (font_size 8)))
(text "A" (rect 21 43 30 58)(font "Intel Clear" (font_size 8)))
(line (pt 0 48)(pt 16 48))
)
(port
(pt 0 64)
(input)
(text "B" (rect 0 0 9 15)(font "Intel Clear" (font_size 8)))
(text "B" (rect 21 59 30 74)(font "Intel Clear" (font_size 8)))
(line (pt 0 64)(pt 16 64))
)
(port
(pt 96 32)
(output)
(text "Cout" (rect 0 0 28 15)(font "Intel Clear" (font_size 8)))
(text "Cout" (rect 47 27 75 42)(font "Intel Clear" (font_size 8)))
(line (pt 96 32)(pt 80 32))
)
(port
(pt 96 48)
(output)
(text "S" (rect 0 0 9 15)(font "Intel Clear" (font_size 8)))
(text "S" (rect 66 43 75 58)(font "Intel Clear" (font_size 8)))
(line (pt 96 48)(pt 80 48))
)
(drawing
(rectangle (rect 16 16 80 80))
)
)
(symbol
(rect 472 264 568 360)
(text "AdderDemo" (rect 5 0 75 15)(font "Intel Clear" (font_size 8)))
(text "inst4" (rect 8 79 33 92)(font "Intel Clear" ))
(port
(pt 0 32)
(input)
(text "Cin" (rect 0 0 20 15)(font "Intel Clear" (font_size 8)))
(text "Cin" (rect 21 27 41 42)(font "Intel Clear" (font_size 8)))
(line (pt 0 32)(pt 16 32))
)
(port
(pt 0 48)
(input)
(text "A" (rect 0 0 9 15)(font "Intel Clear" (font_size 8)))
(text "A" (rect 21 43 30 58)(font "Intel Clear" (font_size 8)))
(line (pt 0 48)(pt 16 48))
)
(port
(pt 0 64)
(input)
(text "B" (rect 0 0 9 15)(font "Intel Clear" (font_size 8)))
(text "B" (rect 21 59 30 74)(font "Intel Clear" (font_size 8)))
(line (pt 0 64)(pt 16 64))
)
(port
(pt 96 32)
(output)
(text "Cout" (rect 0 0 28 15)(font "Intel Clear" (font_size 8)))
(text "Cout" (rect 47 27 75 42)(font "Intel Clear" (font_size 8)))
(line (pt 96 32)(pt 80 32))
)
(port
(pt 96 48)
(output)
(text "S" (rect 0 0 9 15)(font "Intel Clear" (font_size 8)))
(text "S" (rect 66 43 75 58)(font "Intel Clear" (font_size 8)))
(line (pt 96 48)(pt 80 48))
)
(drawing
(rectangle (rect 16 16 80 80))
)
)
(symbol
(rect 608 264 704 360)
(text "AdderDemo" (rect 5 0 75 15)(font "Intel Clear" (font_size 8)))
(text "inst6" (rect 8 79 33 92)(font "Intel Clear" ))
(port
(pt 0 32)
(input)
(text "Cin" (rect 0 0 20 15)(font "Intel Clear" (font_size 8)))
(text "Cin" (rect 21 27 41 42)(font "Intel Clear" (font_size 8)))
(line (pt 0 32)(pt 16 32))
)
(port
(pt 0 48)
(input)
(text "A" (rect 0 0 9 15)(font "Intel Clear" (font_size 8)))
(text "A" (rect 21 43 30 58)(font "Intel Clear" (font_size 8)))
(line (pt 0 48)(pt 16 48))
)
(port
(pt 0 64)
(input)
(text "B" (rect 0 0 9 15)(font "Intel Clear" (font_size 8)))
(text "B" (rect 21 59 30 74)(font "Intel Clear" (font_size 8)))
(line (pt 0 64)(pt 16 64))
)
(port
(pt 96 32)
(output)
(text "Cout" (rect 0 0 28 15)(font "Intel Clear" (font_size 8)))
(text "Cout" (rect 47 27 75 42)(font "Intel Clear" (font_size 8)))
(line (pt 96 32)(pt 80 32))
)
(port
(pt 96 48)
(output)
(text "S" (rect 0 0 9 15)(font "Intel Clear" (font_size 8)))
(text "S" (rect 66 43 75 58)(font "Intel Clear" (font_size 8)))
(line (pt 96 48)(pt 80 48))
)
(drawing
(rectangle (rect 16 16 80 80))
)
)
(symbol
(rect 728 312 792 360)
(text "XOR" (rect 1 0 23 10)(font "Arial" (font_size 6)))
(text "inst5" (rect 3 37 27 50)(font "Intel Clear" ))
(port
(pt 0 16)
(input)
(text "IN1" (rect 2 7 23 18)(font "Courier New" (bold))(invisible))
(text "IN1" (rect 2 7 23 18)(font "Courier New" (bold))(invisible))
(line (pt 0 16)(pt 11 16))
)
(port
(pt 0 32)
(input)
(text "IN2" (rect 2 23 23 34)(font "Courier New" (bold))(invisible))
(text "IN2" (rect 2 23 23 34)(font "Courier New" (bold))(invisible))
(line (pt 0 32)(pt 11 32))
)
(port
(pt 64 24)
(output)
(text "OUT" (rect 48 15 69 26)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 69 26)(font "Courier New" (bold))(invisible))
(line (pt 49 24)(pt 64 24))
)
(drawing
(line (pt 14 13)(pt 25 13))
(line (pt 14 36)(pt 25 36))
(arc (pt 7 29)(pt 7 19)(rect -14 8 19 41))
(arc (pt 49 24)(pt 25 13)(rect -6 13 57 76))
(arc (pt 25 35)(pt 49 24)(rect -6 -27 57 36))
(arc (pt 8 36)(pt 8 12)(rect -21 7 14 42))
)
)
(connector
(pt 296 296)
(pt 336 296)
)
(connector
(pt 432 296)
(pt 472 296)
)
(connector
(pt 608 312)
(pt 584 312)
)
(connector
(pt 472 312)
(pt 448 312)
)
(connector
(pt 200 312)
(pt 176 312)
)
(connector
(pt 472 328)
(pt 456 328)
)
(connector
(pt 336 328)
(pt 320 328)
)
(connector
(pt 296 312)
(pt 304 312)
)
(connector
(pt 304 312)
(pt 304 376)
)
(connector
(pt 432 312)
(pt 440 312)
)
(connector
(pt 440 312)
(pt 440 376)
)
(connector
(pt 304 376)
(pt 440 376)
)
(connector
(pt 568 312)
(pt 576 312)
)
(connector
(pt 576 312)
(pt 576 376)
)
(connector
(pt 440 376)
(pt 576 376)
)
(connector
(pt 704 312)
(pt 712 312)
)
(connector
(pt 712 312)
(pt 712 376)
)
(connector
(pt 200 296)
(pt 168 296)
)
(connector
(pt 576 376)
(pt 712 376)
)
(connector
(pt 712 376)
(pt 728 376)
)
(connector
(pt 792 336)
(pt 808 336)
)
(connector
(pt 592 328)
(pt 608 328)
)
(connector
(pt 728 344)
(pt 600 344)
)
(connector
(pt 600 344)
(pt 600 296)
)
(connector
(pt 568 296)
(pt 600 296)
)
(connector
(pt 600 296)
(pt 608 296)
)
(connector
(pt 728 328)
(pt 720 328)
)
(connector
(pt 720 328)
(pt 720 296)
)
(connector
(pt 704 296)
(pt 720 296)
)
(connector
(pt 720 296)
(pt 728 296)
)
(connector
(text "A3" (rect 160 260 173 274)(font "Intel Clear" )(vertical))
(pt 176 232)
(pt 176 312)
)
(connector
(pt 200 328)
(pt 184 328)
)
(connector
(pt 336 312)
(pt 312 312)
)
(connector
(text "A2" (rect 296 268 309 282)(font "Intel Clear" )(vertical))
(pt 312 232)
(pt 312 312)
)
(connector
(text "B2" (rect 304 300 317 314)(font "Intel Clear" )(vertical))
(pt 320 216)
(pt 320 328)
)
(connector
(text "A1" (rect 432 284 445 298)(font "Intel Clear" )(vertical))
(pt 448 312)
(pt 448 232)
)
(connector
(text "B1" (rect 440 300 453 314)(font "Intel Clear" )(vertical))
(pt 456 216)
(pt 456 328)
)
(connector
(text "A0" (rect 568 283 581 298)(font "Intel Clear" )(vertical))
(pt 584 232)
(pt 584 312)
)
(connector
(text "B0" (rect 576 299 589 314)(font "Intel Clear" )(vertical))
(pt 592 328)
(pt 592 216)
)
(connector
(text "B3" (rect 168 260 181 274)(font "Intel Clear" )(vertical))
(pt 184 216)
(pt 184 328)
)
(connector
(pt 168 216)
(pt 184 216)
(bus)
)
(connector
(pt 184 216)
(pt 320 216)
(bus)
)
(connector
(pt 320 216)
(pt 456 216)
(bus)
)
(connector
(pt 456 216)
(pt 592 216)
(bus)
)
(connector
(pt 168 232)
(pt 176 232)
(bus)
)
(connector
(pt 176 232)
(pt 312 232)
(bus)
)
(connector
(pt 312 232)
(pt 448 232)
(bus)
)
(connector
(pt 448 232)
(pt 584 232)
(bus)
)
(junction (pt 440 376))
(junction (pt 576 376))
(junction (pt 712 376))
(junction (pt 600 296))
(junction (pt 720 296))
(junction (pt 184 216))
(junction (pt 320 216))
(junction (pt 456 216))
(junction (pt 176 232))
(junction (pt 312 232))
(junction (pt 448 232))

435
1ano/isd/quartus-projects/AdderDemo/AdderDemo.bdf Normal file
View File

@ -0,0 +1,435 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "graphic" (version "1.4"))
(pin
(input)
(rect 0 -64 168 -48)
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
(text "Cin" (rect 5 0 23 11)(font "Arial" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
)
(pin
(input)
(rect 0 -32 168 -16)
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
(text "A" (rect 5 0 15 13)(font "Intel Clear" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
)
(pin
(input)
(rect 0 0 168 16)
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
(text "B" (rect 5 0 14 13)(font "Intel Clear" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
)
(pin
(output)
(rect 584 8 760 24)
(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
(text "Cout" (rect 90 0 115 13)(font "Intel Clear" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
(line (pt 52 4)(pt 78 4))
(line (pt 52 12)(pt 78 12))
(line (pt 52 12)(pt 52 4))
(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
)
(pin
(output)
(rect 456 136 632 152)
(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
(text "S" (rect 90 0 98 13)(font "Intel Clear" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
(line (pt 52 4)(pt 78 4))
(line (pt 52 12)(pt 78 12))
(line (pt 52 12)(pt 52 4))
(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
)
(symbol
(rect 408 -56 472 -8)
(text "AND2" (rect 1 0 29 10)(font "Arial" (font_size 6)))
(text "inst2" (rect 3 37 27 50)(font "Intel Clear" ))
(port
(pt 0 16)
(input)
(text "IN1" (rect 2 7 23 18)(font "Courier New" (bold))(invisible))
(text "IN1" (rect 2 7 23 18)(font "Courier New" (bold))(invisible))
(line (pt 0 16)(pt 14 16))
)
(port
(pt 0 32)
(input)
(text "IN2" (rect 2 23 23 34)(font "Courier New" (bold))(invisible))
(text "IN2" (rect 2 23 23 34)(font "Courier New" (bold))(invisible))
(line (pt 0 32)(pt 14 32))
)
(port
(pt 64 24)
(output)
(text "OUT" (rect 48 15 69 26)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 69 26)(font "Courier New" (bold))(invisible))
(line (pt 42 24)(pt 64 24))
)
(drawing
(line (pt 14 12)(pt 30 12))
(line (pt 14 37)(pt 31 37))
(line (pt 14 12)(pt 14 37))
(arc (pt 31 37)(pt 30 12)(rect 18 12 43 37))
)
)
(symbol
(rect 496 -8 560 40)
(text "OR2" (rect 1 0 23 10)(font "Arial" (font_size 6)))
(text "inst3" (rect 3 37 27 50)(font "Intel Clear" ))
(port
(pt 0 32)
(input)
(text "IN2" (rect 2 23 23 34)(font "Courier New" (bold))(invisible))
(text "IN2" (rect 2 23 23 34)(font "Courier New" (bold))(invisible))
(line (pt 0 32)(pt 15 32))
)
(port
(pt 0 16)
(input)
(text "IN1" (rect 2 7 23 18)(font "Courier New" (bold))(invisible))
(text "IN1" (rect 2 7 23 18)(font "Courier New" (bold))(invisible))
(line (pt 0 16)(pt 15 16))
)
(port
(pt 64 24)
(output)
(text "OUT" (rect 48 15 69 26)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 69 26)(font "Courier New" (bold))(invisible))
(line (pt 48 24)(pt 64 24))
)
(drawing
(line (pt 14 36)(pt 25 36))
(line (pt 14 13)(pt 25 13))
(arc (pt 7 29)(pt 7 19)(rect -14 8 19 41))
(arc (pt 49 24)(pt 25 13)(rect -6 13 57 76))
(arc (pt 25 35)(pt 49 24)(rect -6 -27 57 36))
)
)
(symbol
(rect 296 96 360 144)
(text "XOR" (rect 1 0 23 10)(font "Arial" (font_size 6)))
(text "inst4" (rect 3 37 28 50)(font "Intel Clear" ))
(port
(pt 0 16)
(input)
(text "IN1" (rect 2 7 23 18)(font "Courier New" (bold))(invisible))
(text "IN1" (rect 2 7 23 18)(font "Courier New" (bold))(invisible))
(line (pt 0 16)(pt 11 16))
)
(port
(pt 0 32)
(input)
(text "IN2" (rect 2 23 23 34)(font "Courier New" (bold))(invisible))
(text "IN2" (rect 2 23 23 34)(font "Courier New" (bold))(invisible))
(line (pt 0 32)(pt 11 32))
)
(port
(pt 64 24)
(output)
(text "OUT" (rect 48 15 69 26)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 69 26)(font "Courier New" (bold))(invisible))
(line (pt 49 24)(pt 64 24))
)
(drawing
(line (pt 14 13)(pt 25 13))
(line (pt 14 36)(pt 25 36))
(arc (pt 7 29)(pt 7 19)(rect -14 8 19 41))
(arc (pt 49 24)(pt 25 13)(rect -6 13 57 76))
(arc (pt 25 35)(pt 49 24)(rect -6 -27 57 36))
(arc (pt 8 36)(pt 8 12)(rect -21 7 14 42))
)
)
(symbol
(rect 376 120 440 168)
(text "XOR" (rect 1 0 23 10)(font "Arial" (font_size 6)))
(text "inst5" (rect 3 37 27 50)(font "Intel Clear" ))
(port
(pt 0 16)
(input)
(text "IN1" (rect 2 7 23 18)(font "Courier New" (bold))(invisible))
(text "IN1" (rect 2 7 23 18)(font "Courier New" (bold))(invisible))
(line (pt 0 16)(pt 11 16))
)
(port
(pt 0 32)
(input)
(text "IN2" (rect 2 23 23 34)(font "Courier New" (bold))(invisible))
(text "IN2" (rect 2 23 23 34)(font "Courier New" (bold))(invisible))
(line (pt 0 32)(pt 11 32))
)
(port
(pt 64 24)
(output)
(text "OUT" (rect 48 15 69 26)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 69 26)(font "Courier New" (bold))(invisible))
(line (pt 49 24)(pt 64 24))
)
(drawing
(line (pt 14 13)(pt 25 13))
(line (pt 14 36)(pt 25 36))
(arc (pt 7 29)(pt 7 19)(rect -14 8 19 41))
(arc (pt 49 24)(pt 25 13)(rect -6 13 57 76))
(arc (pt 25 35)(pt 49 24)(rect -6 -27 57 36))
(arc (pt 8 36)(pt 8 12)(rect -21 7 14 42))
)
)
(symbol
(rect 312 -32 376 16)
(text "OR2" (rect 1 0 23 10)(font "Arial" (font_size 6)))
(text "inst1" (rect 3 37 27 48)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "IN2" (rect 2 23 23 34)(font "Courier New" (bold))(invisible))
(text "IN2" (rect 2 23 23 34)(font "Courier New" (bold))(invisible))
(line (pt 0 32)(pt 15 32))
)
(port
(pt 0 16)
(input)
(text "IN1" (rect 2 7 23 18)(font "Courier New" (bold))(invisible))
(text "IN1" (rect 2 7 23 18)(font "Courier New" (bold))(invisible))
(line (pt 0 16)(pt 15 16))
)
(port
(pt 64 24)
(output)
(text "OUT" (rect 48 15 69 26)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 69 26)(font "Courier New" (bold))(invisible))
(line (pt 48 24)(pt 64 24))
)
(drawing
(line (pt 14 36)(pt 25 36))
(line (pt 14 13)(pt 25 13))
(arc (pt 7 29)(pt 7 19)(rect -14 8 19 41))
(arc (pt 49 24)(pt 25 13)(rect -6 13 57 76))
(arc (pt 25 35)(pt 49 24)(rect -6 -27 57 36))
)
)
(symbol
(rect 312 32 376 80)
(text "AND2" (rect 1 0 29 10)(font "Arial" (font_size 6)))
(text "inst6" (rect 3 37 27 48)(font "Arial" ))
(port
(pt 0 16)
(input)
(text "IN1" (rect 2 7 23 18)(font "Courier New" (bold))(invisible))
(text "IN1" (rect 2 7 23 18)(font "Courier New" (bold))(invisible))
(line (pt 0 16)(pt 14 16))
)
(port
(pt 0 32)
(input)
(text "IN2" (rect 2 23 23 34)(font "Courier New" (bold))(invisible))
(text "IN2" (rect 2 23 23 34)(font "Courier New" (bold))(invisible))
(line (pt 0 32)(pt 14 32))
)
(port
(pt 64 24)
(output)
(text "OUT" (rect 48 15 69 26)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 69 26)(font "Courier New" (bold))(invisible))
(line (pt 42 24)(pt 64 24))
)
(drawing
(line (pt 14 12)(pt 30 12))
(line (pt 14 37)(pt 31 37))
(line (pt 14 12)(pt 14 37))
(arc (pt 31 37)(pt 30 12)(rect 18 12 43 37))
)
)
(connector
(pt 312 -24)
(pt 312 -16)
)
(connector
(pt 312 8)
(pt 312 0)
)
(connector
(pt 312 48)
(pt 184 48)
)
(connector
(pt 184 48)
(pt 184 -24)
)
(connector
(pt 168 -24)
(pt 184 -24)
)
(connector
(pt 312 64)
(pt 200 64)
)
(connector
(pt 200 64)
(pt 200 8)
)
(connector
(pt 168 8)
(pt 200 8)
)
(connector
(pt 376 -8)
(pt 408 -8)
)
(connector
(pt 408 -8)
(pt 408 -24)
)
(connector
(pt 408 -56)
(pt 168 -56)
)
(connector
(pt 408 -40)
(pt 408 -56)
)
(connector
(pt 376 56)
(pt 496 56)
)
(connector
(pt 472 -32)
(pt 496 -32)
)
(connector
(pt 496 -32)
(pt 496 8)
)
(connector
(pt 496 24)
(pt 496 56)
)
(connector
(pt 560 16)
(pt 584 16)
)
(connector
(pt 168 -24)
(pt 168 -56)
)
(connector
(pt 216 112)
(pt 296 112)
)
(connector
(pt 216 -24)
(pt 216 112)
)
(connector
(pt 232 128)
(pt 296 128)
)
(connector
(pt 232 8)
(pt 232 128)
)
(connector
(pt 184 -24)
(pt 216 -24)
)
(connector
(pt 216 -24)
(pt 312 -24)
)
(connector
(pt 200 8)
(pt 232 8)
)
(connector
(pt 232 8)
(pt 312 8)
)
(connector
(pt 168 152)
(pt 376 152)
)
(connector
(pt 360 120)
(pt 376 120)
)
(connector
(pt 376 120)
(pt 376 136)
)
(connector
(pt 168 -24)
(pt 168 8)
)
(connector
(pt 168 8)
(pt 168 152)
)
(connector
(pt 440 144)
(pt 456 144)
)
(junction (pt 184 -24))
(junction (pt 200 8))
(junction (pt 216 -24))
(junction (pt 232 8))
(junction (pt 168 -56))
(junction (pt 168 -24))
(junction (pt 168 8))

65
1ano/isd/quartus-projects/AdderDemo/AdderDemo.bsf Normal file
View File

@ -0,0 +1,65 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "symbol" (version "1.2"))
(symbol
(rect 16 16 112 112)
(text "AdderDemo" (rect 5 0 75 15)(font "Intel Clear" (font_size 8)))
(text "inst" (rect 8 79 28 92)(font "Intel Clear" ))
(port
(pt 0 32)
(input)
(text "Cin" (rect 0 0 20 15)(font "Intel Clear" (font_size 8)))
(text "Cin" (rect 21 27 41 42)(font "Intel Clear" (font_size 8)))
(line (pt 0 32)(pt 16 32))
)
(port
(pt 0 48)
(input)
(text "A" (rect 0 0 9 15)(font "Intel Clear" (font_size 8)))
(text "A" (rect 21 43 30 58)(font "Intel Clear" (font_size 8)))
(line (pt 0 48)(pt 16 48))
)
(port
(pt 0 64)
(input)
(text "B" (rect 0 0 9 15)(font "Intel Clear" (font_size 8)))
(text "B" (rect 21 59 30 74)(font "Intel Clear" (font_size 8)))
(line (pt 0 64)(pt 16 64))
)
(port
(pt 96 32)
(output)
(text "Cout" (rect 0 0 28 15)(font "Intel Clear" (font_size 8)))
(text "Cout" (rect 47 27 75 42)(font "Intel Clear" (font_size 8)))
(line (pt 96 32)(pt 80 32))
)
(port
(pt 96 48)
(output)
(text "S" (rect 0 0 9 15)(font "Intel Clear" (font_size 8)))
(text "S" (rect 66 43 75 58)(font "Intel Clear" (font_size 8)))
(line (pt 96 48)(pt 80 48))
)
(drawing
(rectangle (rect 16 16 80 80))
)
)

31
1ano/isd/quartus-projects/AdderDemo/AdderDemo.qpf Normal file
View File

@ -0,0 +1,31 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2020 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
# Date created = 12:03:39 November 25, 2022
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "20.1"
DATE = "12:03:39 November 25, 2022"
# Revisions
PROJECT_REVISION = "AdderDemo"

59
1ano/isd/quartus-projects/AdderDemo/AdderDemo.qsf Normal file
View File

@ -0,0 +1,59 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2020 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
# Date created = 12:03:39 November 25, 2022
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# AdderDemo_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE auto
set_global_assignment -name TOP_LEVEL_ENTITY Adder
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:03:39 NOVEMBER 25, 2022"
set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
set_global_assignment -name BDF_FILE AdderDemo.bdf
set_global_assignment -name BDF_FILE Adder.bdf
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

BIN
1ano/isd/quartus-projects/AdderDemo/AdderDemo.qws Normal file
View File

Binary file not shown.

BIN
1ano/isd/quartus-projects/AdderDemo/db/AdderDemo.(0).cnf.cdb Normal file
View File

Binary file not shown.

BIN
1ano/isd/quartus-projects/AdderDemo/db/AdderDemo.(0).cnf.hdb Normal file
View File

Binary file not shown.

BIN
1ano/isd/quartus-projects/AdderDemo/db/AdderDemo.(1).cnf.cdb Normal file
View File

Binary file not shown.

BIN
1ano/isd/quartus-projects/AdderDemo/db/AdderDemo.(1).cnf.hdb Normal file
View File

Binary file not shown.

5
1ano/isd/quartus-projects/AdderDemo/db/AdderDemo.cbx.xml Normal file
View File

@ -0,0 +1,5 @@
<?xml version="1.0" ?>
<LOG_ROOT>
<PROJECT NAME="AdderDemo">
</PROJECT>
</LOG_ROOT>

BIN
1ano/isd/quartus-projects/AdderDemo/db/AdderDemo.cmp.rdb Normal file
View File

Binary file not shown.

3
1ano/isd/quartus-projects/AdderDemo/db/AdderDemo.db_info Normal file
View File

@ -0,0 +1,3 @@
Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Version_Index = 520278016
Creation_Time = Thu Dec 1 16:34:59 2022

47
1ano/isd/quartus-projects/AdderDemo/db/AdderDemo.hier_info Normal file
View File

@ -0,0 +1,47 @@
|Adder
Cout <= AdderDemo:inst6.Cout
Cin => AdderDemo:inst.Cin
A[0] => AdderDemo:inst6.A
A[1] => AdderDemo:inst4.A
A[2] => AdderDemo:inst3.A
A[3] => AdderDemo:inst.A
B[0] => AdderDemo:inst6.B
B[1] => AdderDemo:inst4.B
B[2] => AdderDemo:inst3.B
B[3] => AdderDemo:inst.B
S <= S.DB_MAX_OUTPUT_PORT_TYPE
Overflow <= inst5.DB_MAX_OUTPUT_PORT_TYPE
|Adder|AdderDemo:inst6
Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
Cin => gdfx_temp0.IN0
A => gdfx_temp0.IN1
B => gdfx_temp0.IN2
S <= inst5.DB_MAX_OUTPUT_PORT_TYPE
|Adder|AdderDemo:inst4
Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
Cin => gdfx_temp0.IN0
A => gdfx_temp0.IN1
B => gdfx_temp0.IN2
S <= inst5.DB_MAX_OUTPUT_PORT_TYPE
|Adder|AdderDemo:inst3
Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
Cin => gdfx_temp0.IN0
A => gdfx_temp0.IN1
B => gdfx_temp0.IN2
S <= inst5.DB_MAX_OUTPUT_PORT_TYPE
|Adder|AdderDemo:inst
Cout <= inst3.DB_MAX_OUTPUT_PORT_TYPE
Cin => gdfx_temp0.IN0
A => gdfx_temp0.IN1
B => gdfx_temp0.IN2
S <= inst5.DB_MAX_OUTPUT_PORT_TYPE

BIN
1ano/isd/quartus-projects/AdderDemo/db/AdderDemo.hif Normal file
View File

Binary file not shown.

82
1ano/isd/quartus-projects/AdderDemo/db/AdderDemo.lpc.html Normal file
View File

@ -0,0 +1,82 @@
<TABLE>
<TR bgcolor="#C0C0C0">
<TH>Hierarchy</TH>
<TH>Input</TH>
<TH>Constant Input</TH>
<TH>Unused Input</TH>
<TH>Floating Input</TH>
<TH>Output</TH>
<TH>Constant Output</TH>
<TH>Unused Output</TH>
<TH>Floating Output</TH>
<TH>Bidir</TH>
<TH>Constant Bidir</TH>
<TH>Unused Bidir</TH>
<TH>Input only Bidir</TH>
<TH>Output only Bidir</TH>
</TR>
<TR >
<TD >inst</TD>
<TD >3</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >2</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst3</TD>
<TD >3</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >2</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst4</TD>
<TD >3</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >2</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst6</TD>
<TD >3</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >2</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
</TABLE>

BIN
1ano/isd/quartus-projects/AdderDemo/db/AdderDemo.lpc.rdb Normal file
View File

Binary file not shown.

10
1ano/isd/quartus-projects/AdderDemo/db/AdderDemo.lpc.txt Normal file
View File

@ -0,0 +1,10 @@
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Legal Partition Candidates ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; inst ; 3 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst3 ; 3 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst4 ; 3 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst6 ; 3 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

15
1ano/isd/quartus-projects/AdderDemo/db/AdderDemo.map.qmsg Normal file
View File

@ -0,0 +1,15 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1669913613849 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1669913613849 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Dec 1 16:53:33 2022 " "Processing started: Thu Dec 1 16:53:33 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1669913613849 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1669913613849 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off AdderDemo -c AdderDemo " "Command: quartus_map --read_settings_files=on --write_settings_files=off AdderDemo -c AdderDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1669913613849 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1669913613941 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1669913613941 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "AdderDemo.bdf 1 1 " "Found 1 design units, including 1 entities, in source file AdderDemo.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 AdderDemo " "Found entity 1: AdderDemo" { } { { "AdderDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/AdderDemo/AdderDemo.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1669913618851 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1669913618851 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Adder.bdf 1 1 " "Found 1 design units, including 1 entities, in source file Adder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Adder " "Found entity 1: Adder" { } { { "Adder.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/AdderDemo/Adder.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1669913618851 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1669913618851 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "Adder " "Elaborating entity \"Adder\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1669913618873 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "AdderDemo AdderDemo:inst6 " "Elaborating entity \"AdderDemo\" for hierarchy \"AdderDemo:inst6\"" { } { { "Adder.bdf" "inst6" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/AdderDemo/Adder.bdf" { { 264 608 704 360 "inst6" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1669913618874 ""}
{ "Error" "ESGN_MULTIPLE_SOURCE" "S S " "Net \"S\", which fans out to \"S\", cannot be assigned more than one value" { { "Error" "ESGN_SUB_MULTIPLE_SOURCE" "AdderDemo:inst\|S " "Net is fed by \"AdderDemo:inst\|S\"" { } { { "AdderDemo.bdf" "S" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/AdderDemo/AdderDemo.bdf" { { 136 456 632 152 "S" "" } } } } } 0 12015 "Net is fed by \"%1!s!\"" 0 0 "Design Software" 0 -1 1669913618894 ""} { "Error" "ESGN_SUB_MULTIPLE_SOURCE" "AdderDemo:inst3\|S " "Net is fed by \"AdderDemo:inst3\|S\"" { } { { "AdderDemo.bdf" "S" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/AdderDemo/AdderDemo.bdf" { { 136 456 632 152 "S" "" } } } } } 0 12015 "Net is fed by \"%1!s!\"" 0 0 "Design Software" 0 -1 1669913618894 ""} { "Error" "ESGN_SUB_MULTIPLE_SOURCE" "AdderDemo:inst4\|S " "Net is fed by \"AdderDemo:inst4\|S\"" { } { { "AdderDemo.bdf" "S" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/AdderDemo/AdderDemo.bdf" { { 136 456 632 152 "S" "" } } } } } 0 12015 "Net is fed by \"%1!s!\"" 0 0 "Design Software" 0 -1 1669913618894 ""} { "Error" "ESGN_SUB_MULTIPLE_SOURCE" "AdderDemo:inst6\|S " "Net is fed by \"AdderDemo:inst6\|S\"" { } { { "AdderDemo.bdf" "S" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/AdderDemo/AdderDemo.bdf" { { 136 456 632 152 "S" "" } } } } } 0 12015 "Net is fed by \"%1!s!\"" 0 0 "Design Software" 0 -1 1669913618894 ""} } { { "Adder.bdf" "S" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/AdderDemo/Adder.bdf" { { 368 728 904 384 "S" "" } } } } } 0 12014 "Net \"%1!s!\", which fans out to \"%2!s!\", cannot be assigned more than one value" 0 0 "Analysis & Synthesis" 0 -1 1669913618894 ""}
{ "Error" "ESGN_MULTIPLE_SOURCE" "AdderDemo:inst\|gdfx_temp0 AdderDemo:inst\|inst6 " "Net \"AdderDemo:inst\|gdfx_temp0\", which fans out to \"AdderDemo:inst\|inst6\", cannot be assigned more than one value" { { "Error" "ESGN_SUB_MULTIPLE_SOURCE" "AdderDemo:inst\|Cin " "Net is fed by \"AdderDemo:inst\|Cin\"" { } { { "AdderDemo.bdf" "Cin" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/AdderDemo/AdderDemo.bdf" { { -64 0 168 -48 "Cin" "" } } } } } 0 12015 "Net is fed by \"%1!s!\"" 0 0 "Design Software" 0 -1 1669913618894 ""} { "Error" "ESGN_SUB_MULTIPLE_SOURCE" "AdderDemo:inst\|A " "Net is fed by \"AdderDemo:inst\|A\"" { } { { "AdderDemo.bdf" "A" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/AdderDemo/AdderDemo.bdf" { { -32 0 168 -16 "A" "" } } } } } 0 12015 "Net is fed by \"%1!s!\"" 0 0 "Design Software" 0 -1 1669913618894 ""} { "Error" "ESGN_SUB_MULTIPLE_SOURCE" "AdderDemo:inst\|B " "Net is fed by \"AdderDemo:inst\|B\"" { } { { "AdderDemo.bdf" "B" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/AdderDemo/AdderDemo.bdf" { { 0 0 168 16 "B" "" } } } } } 0 12015 "Net is fed by \"%1!s!\"" 0 0 "Design Software" 0 -1 1669913618894 ""} } { { "AdderDemo.bdf" "inst6" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/AdderDemo/AdderDemo.bdf" { { 32 312 376 80 "inst6" "" } } } } } 0 12014 "Net \"%1!s!\", which fans out to \"%2!s!\", cannot be assigned more than one value" 0 0 "Analysis & Synthesis" 0 -1 1669913618894 ""}
{ "Error" "ESGN_MULTIPLE_SOURCE" "AdderDemo:inst3\|gdfx_temp0 AdderDemo:inst3\|inst6 " "Net \"AdderDemo:inst3\|gdfx_temp0\", which fans out to \"AdderDemo:inst3\|inst6\", cannot be assigned more than one value" { { "Error" "ESGN_SUB_MULTIPLE_SOURCE" "AdderDemo:inst3\|Cin " "Net is fed by \"AdderDemo:inst3\|Cin\"" { } { { "AdderDemo.bdf" "Cin" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/AdderDemo/AdderDemo.bdf" { { -64 0 168 -48 "Cin" "" } } } } } 0 12015 "Net is fed by \"%1!s!\"" 0 0 "Design Software" 0 -1 1669913618894 ""} { "Error" "ESGN_SUB_MULTIPLE_SOURCE" "AdderDemo:inst3\|A " "Net is fed by \"AdderDemo:inst3\|A\"" { } { { "AdderDemo.bdf" "A" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/AdderDemo/AdderDemo.bdf" { { -32 0 168 -16 "A" "" } } } } } 0 12015 "Net is fed by \"%1!s!\"" 0 0 "Design Software" 0 -1 1669913618894 ""} { "Error" "ESGN_SUB_MULTIPLE_SOURCE" "AdderDemo:inst3\|B " "Net is fed by \"AdderDemo:inst3\|B\"" { } { { "AdderDemo.bdf" "B" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/AdderDemo/AdderDemo.bdf" { { 0 0 168 16 "B" "" } } } } } 0 12015 "Net is fed by \"%1!s!\"" 0 0 "Design Software" 0 -1 1669913618894 ""} } { { "AdderDemo.bdf" "inst6" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/AdderDemo/AdderDemo.bdf" { { 32 312 376 80 "inst6" "" } } } } } 0 12014 "Net \"%1!s!\", which fans out to \"%2!s!\", cannot be assigned more than one value" 0 0 "Analysis & Synthesis" 0 -1 1669913618894 ""}
{ "Error" "ESGN_MULTIPLE_SOURCE" "AdderDemo:inst4\|gdfx_temp0 AdderDemo:inst4\|inst6 " "Net \"AdderDemo:inst4\|gdfx_temp0\", which fans out to \"AdderDemo:inst4\|inst6\", cannot be assigned more than one value" { { "Error" "ESGN_SUB_MULTIPLE_SOURCE" "AdderDemo:inst4\|Cin " "Net is fed by \"AdderDemo:inst4\|Cin\"" { } { { "AdderDemo.bdf" "Cin" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/AdderDemo/AdderDemo.bdf" { { -64 0 168 -48 "Cin" "" } } } } } 0 12015 "Net is fed by \"%1!s!\"" 0 0 "Design Software" 0 -1 1669913618894 ""} { "Error" "ESGN_SUB_MULTIPLE_SOURCE" "AdderDemo:inst4\|A " "Net is fed by \"AdderDemo:inst4\|A\"" { } { { "AdderDemo.bdf" "A" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/AdderDemo/AdderDemo.bdf" { { -32 0 168 -16 "A" "" } } } } } 0 12015 "Net is fed by \"%1!s!\"" 0 0 "Design Software" 0 -1 1669913618894 ""} { "Error" "ESGN_SUB_MULTIPLE_SOURCE" "AdderDemo:inst4\|B " "Net is fed by \"AdderDemo:inst4\|B\"" { } { { "AdderDemo.bdf" "B" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/AdderDemo/AdderDemo.bdf" { { 0 0 168 16 "B" "" } } } } } 0 12015 "Net is fed by \"%1!s!\"" 0 0 "Design Software" 0 -1 1669913618894 ""} } { { "AdderDemo.bdf" "inst6" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/AdderDemo/AdderDemo.bdf" { { 32 312 376 80 "inst6" "" } } } } } 0 12014 "Net \"%1!s!\", which fans out to \"%2!s!\", cannot be assigned more than one value" 0 0 "Analysis & Synthesis" 0 -1 1669913618894 ""}
{ "Error" "ESGN_MULTIPLE_SOURCE" "AdderDemo:inst6\|gdfx_temp0 AdderDemo:inst6\|inst6 " "Net \"AdderDemo:inst6\|gdfx_temp0\", which fans out to \"AdderDemo:inst6\|inst6\", cannot be assigned more than one value" { { "Error" "ESGN_SUB_MULTIPLE_SOURCE" "AdderDemo:inst6\|Cin " "Net is fed by \"AdderDemo:inst6\|Cin\"" { } { { "AdderDemo.bdf" "Cin" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/AdderDemo/AdderDemo.bdf" { { -64 0 168 -48 "Cin" "" } } } } } 0 12015 "Net is fed by \"%1!s!\"" 0 0 "Design Software" 0 -1 1669913618894 ""} { "Error" "ESGN_SUB_MULTIPLE_SOURCE" "AdderDemo:inst6\|A " "Net is fed by \"AdderDemo:inst6\|A\"" { } { { "AdderDemo.bdf" "A" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/AdderDemo/AdderDemo.bdf" { { -32 0 168 -16 "A" "" } } } } } 0 12015 "Net is fed by \"%1!s!\"" 0 0 "Design Software" 0 -1 1669913618894 ""} { "Error" "ESGN_SUB_MULTIPLE_SOURCE" "AdderDemo:inst6\|B " "Net is fed by \"AdderDemo:inst6\|B\"" { } { { "AdderDemo.bdf" "B" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/AdderDemo/AdderDemo.bdf" { { 0 0 168 16 "B" "" } } } } } 0 12015 "Net is fed by \"%1!s!\"" 0 0 "Design Software" 0 -1 1669913618894 ""} } { { "AdderDemo.bdf" "inst6" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/AdderDemo/AdderDemo.bdf" { { 32 312 376 80 "inst6" "" } } } } } 0 12014 "Net \"%1!s!\", which fans out to \"%2!s!\", cannot be assigned more than one value" 0 0 "Analysis & Synthesis" 0 -1 1669913618894 ""}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 21 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 21 errors, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "352 " "Peak virtual memory: 352 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1669913618917 ""} { "Error" "EQEXE_END_BANNER_TIME" "Thu Dec 1 16:53:38 2022 " "Processing ended: Thu Dec 1 16:53:38 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1669913618917 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1669913618917 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:14 " "Total CPU time (on all processors): 00:00:14" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1669913618917 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1669913618917 ""}

BIN
1ano/isd/quartus-projects/AdderDemo/db/AdderDemo.map.rdb Normal file
View File

Binary file not shown.

BIN
1ano/isd/quartus-projects/AdderDemo/db/AdderDemo.map_bb.hdb Normal file
View File

Binary file not shown.

BIN
1ano/isd/quartus-projects/AdderDemo/db/AdderDemo.pre_map.hdb Normal file
View File

Binary file not shown.

BIN
1ano/isd/quartus-projects/AdderDemo/db/AdderDemo.rtlv.hdb Normal file
View File

Binary file not shown.

BIN
1ano/isd/quartus-projects/AdderDemo/db/AdderDemo.rtlv_sg.cdb Normal file
View File

Binary file not shown.

BIN
1ano/isd/quartus-projects/AdderDemo/db/AdderDemo.rtlv_sg_swap.cdb Normal file
View File

Binary file not shown.

BIN
1ano/isd/quartus-projects/AdderDemo/db/AdderDemo.sld_design_entry.sci Normal file
View File

Binary file not shown.

1
1ano/isd/quartus-projects/AdderDemo/db/AdderDemo.smart_action.txt Normal file
View File

@ -0,0 +1 @@
SOURCE

BIN
1ano/isd/quartus-projects/AdderDemo/db/AdderDemo.tis_db_list.ddb Normal file
View File

Binary file not shown.

16
1ano/isd/quartus-projects/AdderDemo/db/prev_cmp_AdderDemo.qmsg Normal file
View File

@ -0,0 +1,16 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1669912604933 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1669912604934 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Dec 1 16:36:44 2022 " "Processing started: Thu Dec 1 16:36:44 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1669912604934 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1669912604934 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off AdderDemo -c AdderDemo " "Command: quartus_map --read_settings_files=on --write_settings_files=off AdderDemo -c AdderDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1669912604934 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1669912605025 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1669912605026 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "AdderDemo.bdf 1 1 " "Found 1 design units, including 1 entities, in source file AdderDemo.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 AdderDemo " "Found entity 1: AdderDemo" { } { { "AdderDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/AdderDemo/AdderDemo.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1669912609713 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1669912609713 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Adder.bdf 1 1 " "Found 1 design units, including 1 entities, in source file Adder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Adder " "Found entity 1: Adder" { } { { "Adder.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/AdderDemo/Adder.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1669912609713 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1669912609713 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "Adder " "Elaborating entity \"Adder\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1669912609742 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "AdderDemo AdderDemo:inst6 " "Elaborating entity \"AdderDemo\" for hierarchy \"AdderDemo:inst6\"" { } { { "Adder.bdf" "inst6" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/AdderDemo/Adder.bdf" { { 264 608 704 360 "inst6" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1669912609746 ""}
{ "Error" "ESGN_MULTIPLE_SOURCE" "S S " "Net \"S\", which fans out to \"S\", cannot be assigned more than one value" { { "Error" "ESGN_SUB_MULTIPLE_SOURCE" "AdderDemo:inst\|S " "Net is fed by \"AdderDemo:inst\|S\"" { } { { "AdderDemo.bdf" "S" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/AdderDemo/AdderDemo.bdf" { { 136 456 632 152 "S" "" } } } } } 0 12015 "Net is fed by \"%1!s!\"" 0 0 "Design Software" 0 -1 1669912609773 ""} { "Error" "ESGN_SUB_MULTIPLE_SOURCE" "AdderDemo:inst3\|S " "Net is fed by \"AdderDemo:inst3\|S\"" { } { { "AdderDemo.bdf" "S" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/AdderDemo/AdderDemo.bdf" { { 136 456 632 152 "S" "" } } } } } 0 12015 "Net is fed by \"%1!s!\"" 0 0 "Design Software" 0 -1 1669912609773 ""} { "Error" "ESGN_SUB_MULTIPLE_SOURCE" "AdderDemo:inst4\|S " "Net is fed by \"AdderDemo:inst4\|S\"" { } { { "AdderDemo.bdf" "S" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/AdderDemo/AdderDemo.bdf" { { 136 456 632 152 "S" "" } } } } } 0 12015 "Net is fed by \"%1!s!\"" 0 0 "Design Software" 0 -1 1669912609773 ""} { "Error" "ESGN_SUB_MULTIPLE_SOURCE" "AdderDemo:inst6\|S " "Net is fed by \"AdderDemo:inst6\|S\"" { } { { "AdderDemo.bdf" "S" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/AdderDemo/AdderDemo.bdf" { { 136 456 632 152 "S" "" } } } } } 0 12015 "Net is fed by \"%1!s!\"" 0 0 "Design Software" 0 -1 1669912609773 ""} } { { "Adder.bdf" "S" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/AdderDemo/Adder.bdf" { { 368 728 904 384 "S" "" } } } } } 0 12014 "Net \"%1!s!\", which fans out to \"%2!s!\", cannot be assigned more than one value" 0 0 "Analysis & Synthesis" 0 -1 1669912609773 ""}
{ "Error" "ESGN_MULTIPLE_SOURCE" "AdderDemo:inst\|gdfx_temp0 AdderDemo:inst\|inst6 " "Net \"AdderDemo:inst\|gdfx_temp0\", which fans out to \"AdderDemo:inst\|inst6\", cannot be assigned more than one value" { { "Error" "ESGN_SUB_MULTIPLE_SOURCE" "AdderDemo:inst\|Cin " "Net is fed by \"AdderDemo:inst\|Cin\"" { } { { "AdderDemo.bdf" "Cin" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/AdderDemo/AdderDemo.bdf" { { -64 0 168 -48 "Cin" "" } } } } } 0 12015 "Net is fed by \"%1!s!\"" 0 0 "Design Software" 0 -1 1669912609773 ""} { "Error" "ESGN_SUB_MULTIPLE_SOURCE" "AdderDemo:inst\|A " "Net is fed by \"AdderDemo:inst\|A\"" { } { { "AdderDemo.bdf" "A" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/AdderDemo/AdderDemo.bdf" { { -32 0 168 -16 "A" "" } } } } } 0 12015 "Net is fed by \"%1!s!\"" 0 0 "Design Software" 0 -1 1669912609773 ""} { "Error" "ESGN_SUB_MULTIPLE_SOURCE" "AdderDemo:inst\|B " "Net is fed by \"AdderDemo:inst\|B\"" { } { { "AdderDemo.bdf" "B" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/AdderDemo/AdderDemo.bdf" { { 0 0 168 16 "B" "" } } } } } 0 12015 "Net is fed by \"%1!s!\"" 0 0 "Design Software" 0 -1 1669912609773 ""} } { { "AdderDemo.bdf" "inst6" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/AdderDemo/AdderDemo.bdf" { { 32 312 376 80 "inst6" "" } } } } } 0 12014 "Net \"%1!s!\", which fans out to \"%2!s!\", cannot be assigned more than one value" 0 0 "Analysis & Synthesis" 0 -1 1669912609773 ""}
{ "Error" "ESGN_MULTIPLE_SOURCE" "AdderDemo:inst3\|gdfx_temp0 AdderDemo:inst3\|inst6 " "Net \"AdderDemo:inst3\|gdfx_temp0\", which fans out to \"AdderDemo:inst3\|inst6\", cannot be assigned more than one value" { { "Error" "ESGN_SUB_MULTIPLE_SOURCE" "AdderDemo:inst3\|Cin " "Net is fed by \"AdderDemo:inst3\|Cin\"" { } { { "AdderDemo.bdf" "Cin" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/AdderDemo/AdderDemo.bdf" { { -64 0 168 -48 "Cin" "" } } } } } 0 12015 "Net is fed by \"%1!s!\"" 0 0 "Design Software" 0 -1 1669912609773 ""} { "Error" "ESGN_SUB_MULTIPLE_SOURCE" "AdderDemo:inst3\|A " "Net is fed by \"AdderDemo:inst3\|A\"" { } { { "AdderDemo.bdf" "A" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/AdderDemo/AdderDemo.bdf" { { -32 0 168 -16 "A" "" } } } } } 0 12015 "Net is fed by \"%1!s!\"" 0 0 "Design Software" 0 -1 1669912609773 ""} { "Error" "ESGN_SUB_MULTIPLE_SOURCE" "AdderDemo:inst3\|B " "Net is fed by \"AdderDemo:inst3\|B\"" { } { { "AdderDemo.bdf" "B" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/AdderDemo/AdderDemo.bdf" { { 0 0 168 16 "B" "" } } } } } 0 12015 "Net is fed by \"%1!s!\"" 0 0 "Design Software" 0 -1 1669912609773 ""} } { { "AdderDemo.bdf" "inst6" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/AdderDemo/AdderDemo.bdf" { { 32 312 376 80 "inst6" "" } } } } } 0 12014 "Net \"%1!s!\", which fans out to \"%2!s!\", cannot be assigned more than one value" 0 0 "Analysis & Synthesis" 0 -1 1669912609773 ""}
{ "Error" "ESGN_MULTIPLE_SOURCE" "AdderDemo:inst4\|gdfx_temp0 AdderDemo:inst4\|inst6 " "Net \"AdderDemo:inst4\|gdfx_temp0\", which fans out to \"AdderDemo:inst4\|inst6\", cannot be assigned more than one value" { { "Error" "ESGN_SUB_MULTIPLE_SOURCE" "AdderDemo:inst4\|Cin " "Net is fed by \"AdderDemo:inst4\|Cin\"" { } { { "AdderDemo.bdf" "Cin" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/AdderDemo/AdderDemo.bdf" { { -64 0 168 -48 "Cin" "" } } } } } 0 12015 "Net is fed by \"%1!s!\"" 0 0 "Design Software" 0 -1 1669912609773 ""} { "Error" "ESGN_SUB_MULTIPLE_SOURCE" "AdderDemo:inst4\|A " "Net is fed by \"AdderDemo:inst4\|A\"" { } { { "AdderDemo.bdf" "A" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/AdderDemo/AdderDemo.bdf" { { -32 0 168 -16 "A" "" } } } } } 0 12015 "Net is fed by \"%1!s!\"" 0 0 "Design Software" 0 -1 1669912609773 ""} { "Error" "ESGN_SUB_MULTIPLE_SOURCE" "AdderDemo:inst4\|B " "Net is fed by \"AdderDemo:inst4\|B\"" { } { { "AdderDemo.bdf" "B" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/AdderDemo/AdderDemo.bdf" { { 0 0 168 16 "B" "" } } } } } 0 12015 "Net is fed by \"%1!s!\"" 0 0 "Design Software" 0 -1 1669912609773 ""} } { { "AdderDemo.bdf" "inst6" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/AdderDemo/AdderDemo.bdf" { { 32 312 376 80 "inst6" "" } } } } } 0 12014 "Net \"%1!s!\", which fans out to \"%2!s!\", cannot be assigned more than one value" 0 0 "Analysis & Synthesis" 0 -1 1669912609773 ""}
{ "Error" "ESGN_MULTIPLE_SOURCE" "AdderDemo:inst6\|gdfx_temp0 AdderDemo:inst6\|inst6 " "Net \"AdderDemo:inst6\|gdfx_temp0\", which fans out to \"AdderDemo:inst6\|inst6\", cannot be assigned more than one value" { { "Error" "ESGN_SUB_MULTIPLE_SOURCE" "AdderDemo:inst6\|Cin " "Net is fed by \"AdderDemo:inst6\|Cin\"" { } { { "AdderDemo.bdf" "Cin" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/AdderDemo/AdderDemo.bdf" { { -64 0 168 -48 "Cin" "" } } } } } 0 12015 "Net is fed by \"%1!s!\"" 0 0 "Design Software" 0 -1 1669912609773 ""} { "Error" "ESGN_SUB_MULTIPLE_SOURCE" "AdderDemo:inst6\|A " "Net is fed by \"AdderDemo:inst6\|A\"" { } { { "AdderDemo.bdf" "A" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/AdderDemo/AdderDemo.bdf" { { -32 0 168 -16 "A" "" } } } } } 0 12015 "Net is fed by \"%1!s!\"" 0 0 "Design Software" 0 -1 1669912609773 ""} { "Error" "ESGN_SUB_MULTIPLE_SOURCE" "AdderDemo:inst6\|B " "Net is fed by \"AdderDemo:inst6\|B\"" { } { { "AdderDemo.bdf" "B" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/AdderDemo/AdderDemo.bdf" { { 0 0 168 16 "B" "" } } } } } 0 12015 "Net is fed by \"%1!s!\"" 0 0 "Design Software" 0 -1 1669912609773 ""} } { { "AdderDemo.bdf" "inst6" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/AdderDemo/AdderDemo.bdf" { { 32 312 376 80 "inst6" "" } } } } } 0 12014 "Net \"%1!s!\", which fans out to \"%2!s!\", cannot be assigned more than one value" 0 0 "Analysis & Synthesis" 0 -1 1669912609773 ""}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 21 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 21 errors, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "353 " "Peak virtual memory: 353 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1669912609798 ""} { "Error" "EQEXE_END_BANNER_TIME" "Thu Dec 1 16:36:49 2022 " "Processing ended: Thu Dec 1 16:36:49 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1669912609798 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1669912609798 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:13 " "Total CPU time (on all processors): 00:00:13" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1669912609798 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1669912609798 ""}
{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 23 s 1 " "Quartus Prime Full Compilation was unsuccessful. 23 errors, 1 warning" { } { } 0 293001 "Quartus Prime %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1669912609904 ""}

11
1ano/isd/quartus-projects/AdderDemo/incremental_db/README Normal file
View File

@ -0,0 +1,11 @@
This folder contains data for incremental compilation.
The compiled_partitions sub-folder contains previous compilation results for each partition.
As long as this folder is preserved, incremental compilation results from earlier compiles
can be re-used. To perform a clean compilation from source files for all partitions, both
the db and incremental_db folder should be removed.
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
As long as this folder is preserved, imported partitions will be automatically re-imported
when the db or incremental_db/compiled_partitions folders are removed.

3
1ano/isd/quartus-projects/AdderDemo/incremental_db/compiled_partitions/AdderDemo.db_info Normal file
View File

@ -0,0 +1,3 @@
Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Version_Index = 520278016
Creation_Time = Fri Nov 25 12:57:17 2022

BIN
1ano/isd/quartus-projects/AdderDemo/incremental_db/compiled_partitions/AdderDemo.root_partition.map.dpi.tmp Normal file
View File

Binary file not shown.

118
1ano/isd/quartus-projects/AdderDemo/output_files/AdderDemo.flow.rpt Normal file
View File

@ -0,0 +1,118 @@
Flow report for AdderDemo
Thu Dec 1 16:53:38 2022
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Non-Default Global Settings
5. Flow Elapsed Time
6. Flow OS Summary
7. Flow Log
8. Flow Messages
9. Flow Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
+----------------------------------------------------------------------------------+
; Flow Summary ;
+------------------------------------+---------------------------------------------+
; Flow Status ; Flow Failed - Thu Dec 1 16:53:38 2022 ;
; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
; Revision Name ; AdderDemo ;
; Top-level Entity Name ; Adder ;
; Family ; Cyclone IV E ;
; Total logic elements ; N/A until Partition Merge ;
; Total combinational functions ; N/A until Partition Merge ;
; Dedicated logic registers ; N/A until Partition Merge ;
; Total registers ; N/A until Partition Merge ;
; Total pins ; N/A until Partition Merge ;
; Total virtual pins ; N/A until Partition Merge ;
; Total memory bits ; N/A until Partition Merge ;
; Embedded Multiplier 9-bit elements ; N/A until Partition Merge ;
; Total PLLs ; N/A until Partition Merge ;
+------------------------------------+---------------------------------------------+
+-----------------------------------------+
; Flow Settings ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 12/01/2022 16:53:33 ;
; Main task ; Compilation ;
; Revision Name ; AdderDemo ;
+-------------------+---------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; COMPILER_SIGNATURE_ID ; 198516037997543.166991361327869 ; -- ; -- ; -- ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_symbol ;
; EDA_OUTPUT_DATA_FORMAT ; Verilog Hdl ; -- ; -- ; eda_simulation ;
; EDA_SIMULATION_TOOL ; ModelSim-Altera (Verilog) ; <None> ; -- ; -- ;
; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; Adder ; Top ;
; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; Adder ; Top ;
; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; Adder ; Top ;
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
; TOP_LEVEL_ENTITY ; Adder ; AdderDemo ; -- ; -- ;
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
+--------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:05 ; 1.0 ; 352 MB ; 00:00:14 ;
; Total ; 00:00:05 ; -- ; -- ; 00:00:14 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
+----------------------------------------------------------------------------------------+
; Flow OS Summary ;
+----------------------+------------------+----------------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+----------------------+------------------+----------------+------------+----------------+
; Analysis & Synthesis ; rendlaptop ; Ubuntu 22.04.1 ; 22 ; x86_64 ;
+----------------------+------------------+----------------+------------+----------------+
------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off AdderDemo -c AdderDemo

201
1ano/isd/quartus-projects/AdderDemo/output_files/AdderDemo.map.rpt Normal file
View File

@ -0,0 +1,201 @@
Analysis & Synthesis report for AdderDemo
Thu Dec 1 16:53:38 2022
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Parallel Compilation
5. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
+----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+---------------------------------------------+
; Analysis & Synthesis Status ; Failed - Thu Dec 1 16:53:38 2022 ;
; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
; Revision Name ; AdderDemo ;
; Top-level Entity Name ; Adder ;
; Family ; Cyclone IV E ;
; Total logic elements ; N/A until Partition Merge ;
; Total combinational functions ; N/A until Partition Merge ;
; Dedicated logic registers ; N/A until Partition Merge ;
; Total registers ; N/A until Partition Merge ;
; Total pins ; N/A until Partition Merge ;
; Total virtual pins ; N/A until Partition Merge ;
; Total memory bits ; N/A until Partition Merge ;
; Embedded Multiplier 9-bit elements ; N/A until Partition Merge ;
; Total PLLs ; N/A until Partition Merge ;
+------------------------------------+---------------------------------------------+
+------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+------------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+------------------------------------------------------------------+--------------------+--------------------+
; Top-level entity name ; Adder ; AdderDemo ;
; Family name ; Cyclone IV E ; Cyclone V ;
; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Intel FPGA IP Evaluation Mode ; Enable ; Enable ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Infer RAMs from Raw Logic ; On ; On ;
; Parallel Synthesis ; On ; On ;
; DSP Block Balancing ; Auto ; Auto ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique ; Balanced ; Balanced ;
; Carry Chain Length ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto DSP Block Replacement ; On ; On ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Strict RAM Replacement ; Off ; Off ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto RAM Block Balancing ; On ; On ;
; Auto RAM to Logic Cell Conversion ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Timing-Driven Synthesis ; On ; On ;
; Report Parameter Settings ; On ; On ;
; Report Source Assignments ; On ; On ;
; Report Connectivity Checks ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Synchronization Register Chain Length ; 2 ; 2 ;
; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Auto Gated Clock Conversion ; Off ; Off ;
; Block Design Naming ; Auto ; Auto ;
; SDC constraint protection ; Off ; Off ;
; Synthesis Effort ; Auto ; Auto ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
; Analysis & Synthesis Message Level ; Medium ; Medium ;
; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
; Resource Aware Inference For Block RAM ; On ; On ;
+------------------------------------------------------------------+--------------------+--------------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 8 ;
; Maximum allowed ; 4 ;
; ; ;
; Average used ; 1.00 ;
; Maximum used ; 1 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
+----------------------------+-------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Info: Processing started: Thu Dec 1 16:53:33 2022
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off AdderDemo -c AdderDemo
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
Info (12021): Found 1 design units, including 1 entities, in source file AdderDemo.bdf
Info (12023): Found entity 1: AdderDemo
Info (12021): Found 1 design units, including 1 entities, in source file Adder.bdf
Info (12023): Found entity 1: Adder
Info (12127): Elaborating entity "Adder" for the top level hierarchy
Info (12128): Elaborating entity "AdderDemo" for hierarchy "AdderDemo:inst6"
Error (12014): Net "S", which fans out to "S", cannot be assigned more than one value
Error (12015): Net is fed by "AdderDemo:inst|S"
Error (12015): Net is fed by "AdderDemo:inst3|S"
Error (12015): Net is fed by "AdderDemo:inst4|S"
Error (12015): Net is fed by "AdderDemo:inst6|S"
Error (12014): Net "AdderDemo:inst|gdfx_temp0", which fans out to "AdderDemo:inst|inst6", cannot be assigned more than one value
Error (12015): Net is fed by "AdderDemo:inst|Cin"
Error (12015): Net is fed by "AdderDemo:inst|A"
Error (12015): Net is fed by "AdderDemo:inst|B"
Error (12014): Net "AdderDemo:inst3|gdfx_temp0", which fans out to "AdderDemo:inst3|inst6", cannot be assigned more than one value
Error (12015): Net is fed by "AdderDemo:inst3|Cin"
Error (12015): Net is fed by "AdderDemo:inst3|A"
Error (12015): Net is fed by "AdderDemo:inst3|B"
Error (12014): Net "AdderDemo:inst4|gdfx_temp0", which fans out to "AdderDemo:inst4|inst6", cannot be assigned more than one value
Error (12015): Net is fed by "AdderDemo:inst4|Cin"
Error (12015): Net is fed by "AdderDemo:inst4|A"
Error (12015): Net is fed by "AdderDemo:inst4|B"
Error (12014): Net "AdderDemo:inst6|gdfx_temp0", which fans out to "AdderDemo:inst6|inst6", cannot be assigned more than one value
Error (12015): Net is fed by "AdderDemo:inst6|Cin"
Error (12015): Net is fed by "AdderDemo:inst6|A"
Error (12015): Net is fed by "AdderDemo:inst6|B"
Error: Quartus Prime Analysis & Synthesis was unsuccessful. 21 errors, 1 warning
Error: Peak virtual memory: 352 megabytes
Error: Processing ended: Thu Dec 1 16:53:38 2022
Error: Elapsed time: 00:00:05
Error: Total CPU time (on all processors): 00:00:14

14
1ano/isd/quartus-projects/AdderDemo/output_files/AdderDemo.map.summary Normal file
View File

@ -0,0 +1,14 @@
Analysis & Synthesis Status : Failed - Thu Dec 1 16:53:38 2022
Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Revision Name : AdderDemo
Top-level Entity Name : Adder
Family : Cyclone IV E
Total logic elements : N/A until Partition Merge
Total combinational functions : N/A until Partition Merge
Dedicated logic registers : N/A until Partition Merge
Total registers : N/A until Partition Merge
Total pins : N/A until Partition Merge
Total virtual pins : N/A until Partition Merge
Total memory bits : N/A until Partition Merge
Embedded Multiplier 9-bit elements : N/A until Partition Merge
Total PLLs : N/A until Partition Merge

584
1ano/isd/quartus-projects/DecoderDemo/Dec2_4.bdf Normal file
View File

@ -0,0 +1,584 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "graphic" (version "1.4"))
(pin
(input)
(rect 16 -112 32 56)
(text "INPUT" (rect 6 125 16 154)(font "Arial" (font_size 6))(vertical))
(text "E0L" (rect 3 5 16 25)(font "Intel Clear" )(vertical))
(pt 8 168)
(drawing
(line (pt 4 84)(pt 4 109))
(line (pt 12 84)(pt 12 109))
(line (pt 8 113)(pt 8 168))
(line (pt 4 84)(pt 12 84))
(line (pt 12 109)(pt 8 113))
(line (pt 4 109)(pt 8 113))
)
(rotate270)
(text "VCC" (rect -1 128 9 149)(font "Arial" (font_size 6))(vertical))
)
(pin
(input)
(rect 40 -112 56 56)
(text "INPUT" (rect 6 125 16 154)(font "Arial" (font_size 6))(vertical))
(text "E1" (rect 3 5 16 17)(font "Intel Clear" )(vertical))
(pt 8 168)
(drawing
(line (pt 4 84)(pt 4 109))
(line (pt 12 84)(pt 12 109))
(line (pt 8 113)(pt 8 168))
(line (pt 4 84)(pt 12 84))
(line (pt 12 109)(pt 8 113))
(line (pt 4 109)(pt 8 113))
)
(rotate270)
(text "VCC" (rect -1 128 9 149)(font "Arial" (font_size 6))(vertical))
)
(pin
(input)
(rect 72 -112 88 56)
(text "INPUT" (rect 6 125 16 154)(font "Arial" (font_size 6))(vertical))
(text "X1" (rect 4 5 17 19)(font "Intel Clear" )(vertical))
(pt 8 168)
(drawing
(line (pt 4 84)(pt 4 109))
(line (pt 12 84)(pt 12 109))
(line (pt 8 113)(pt 8 168))
(line (pt 4 84)(pt 12 84))
(line (pt 12 109)(pt 8 113))
(line (pt 4 109)(pt 8 113))
)
(rotate270)
(text "VCC" (rect -1 128 9 149)(font "Arial" (font_size 6))(vertical))
)
(pin
(input)
(rect 120 -112 136 56)
(text "INPUT" (rect 6 125 16 154)(font "Arial" (font_size 6))(vertical))
(text "X0" (rect 3 5 16 20)(font "Intel Clear" )(vertical))
(pt 8 168)
(drawing
(line (pt 4 84)(pt 4 109))
(line (pt 12 84)(pt 12 109))
(line (pt 8 113)(pt 8 168))
(line (pt 4 84)(pt 12 84))
(line (pt 12 109)(pt 8 113))
(line (pt 4 109)(pt 8 113))
)
(rotate270)
(text "VCC" (rect -1 128 9 149)(font "Arial" (font_size 6))(vertical))
)
(pin
(output)
(rect 296 168 472 184)
(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
(text "Y3" (rect 90 0 105 11)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
(line (pt 52 4)(pt 78 4))
(line (pt 52 12)(pt 78 12))
(line (pt 52 12)(pt 52 4))
(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
)
(pin
(output)
(rect 296 256 472 272)
(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
(text "Y2" (rect 90 0 104 13)(font "Intel Clear" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
(line (pt 52 4)(pt 78 4))
(line (pt 52 12)(pt 78 12))
(line (pt 52 12)(pt 52 4))
(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
)
(pin
(output)
(rect 296 432 472 448)
(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
(text "Y1" (rect 90 0 104 13)(font "Intel Clear" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
(line (pt 52 4)(pt 78 4))
(line (pt 52 12)(pt 78 12))
(line (pt 52 12)(pt 52 4))
(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
)
(pin
(output)
(rect 296 344 472 360)
(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
(text "Y0" (rect 90 0 105 13)(font "Intel Clear" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
(line (pt 52 4)(pt 78 4))
(line (pt 52 12)(pt 78 12))
(line (pt 52 12)(pt 52 4))
(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
)
(symbol
(rect 232 136 296 216)
(text "AND4" (rect 1 0 29 10)(font "Arial" (font_size 6)))
(text "inst" (rect 3 69 21 80)(font "Arial" ))
(port
(pt 0 16)
(input)
(text "IN1" (rect 2 7 23 18)(font "Courier New" (bold))(invisible))
(text "IN1" (rect 2 7 23 18)(font "Courier New" (bold))(invisible))
(line (pt 0 16)(pt 18 16))
)
(port
(pt 0 32)
(input)
(text "IN2" (rect 2 23 23 34)(font "Courier New" (bold))(invisible))
(text "IN2" (rect 2 23 23 34)(font "Courier New" (bold))(invisible))
(line (pt 0 32)(pt 18 32))
)
(port
(pt 0 48)
(input)
(text "IN3" (rect 2 39 23 50)(font "Courier New" (bold))(invisible))
(text "IN3" (rect 2 39 23 50)(font "Courier New" (bold))(invisible))
(line (pt 0 48)(pt 18 48))
)
(port
(pt 0 64)
(input)
(text "IN4" (rect 2 55 23 66)(font "Courier New" (bold))(invisible))
(text "IN4" (rect 2 55 23 66)(font "Courier New" (bold))(invisible))
(line (pt 0 64)(pt 18 64))
)
(port
(pt 64 40)
(output)
(text "OUT" (rect 48 31 69 42)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 31 69 42)(font "Courier New" (bold))(invisible))
(line (pt 46 40)(pt 64 40))
)
(drawing
(line (pt 18 28)(pt 34 28))
(line (pt 18 52)(pt 18 28))
(line (pt 18 67)(pt 18 13))
(line (pt 34 53)(pt 18 53))
(arc (pt 34 52)(pt 34 28)(rect 22 28 47 53))
)
)
(symbol
(rect 232 224 296 304)
(text "AND4" (rect 1 0 29 10)(font "Arial" (font_size 6)))
(text "inst1" (rect 3 69 27 82)(font "Intel Clear" ))
(port
(pt 0 16)
(input)
(text "IN1" (rect 2 7 23 18)(font "Courier New" (bold))(invisible))
(text "IN1" (rect 2 7 23 18)(font "Courier New" (bold))(invisible))
(line (pt 0 16)(pt 18 16))
)
(port
(pt 0 32)
(input)
(text "IN2" (rect 2 23 23 34)(font "Courier New" (bold))(invisible))
(text "IN2" (rect 2 23 23 34)(font "Courier New" (bold))(invisible))
(line (pt 0 32)(pt 18 32))
)
(port
(pt 0 48)
(input)
(text "IN3" (rect 2 39 23 50)(font "Courier New" (bold))(invisible))
(text "IN3" (rect 2 39 23 50)(font "Courier New" (bold))(invisible))
(line (pt 0 48)(pt 18 48))
)
(port
(pt 0 64)
(input)
(text "IN4" (rect 2 55 23 66)(font "Courier New" (bold))(invisible))
(text "IN4" (rect 2 55 23 66)(font "Courier New" (bold))(invisible))
(line (pt 0 64)(pt 18 64))
)
(port
(pt 64 40)
(output)
(text "OUT" (rect 48 31 69 42)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 31 69 42)(font "Courier New" (bold))(invisible))
(line (pt 46 40)(pt 64 40))
)
(drawing
(line (pt 18 28)(pt 34 28))
(line (pt 18 52)(pt 18 28))
(line (pt 18 67)(pt 18 13))
(line (pt 34 53)(pt 18 53))
(arc (pt 34 52)(pt 34 28)(rect 22 28 47 53))
)
)
(symbol
(rect 232 312 296 392)
(text "AND4" (rect 1 0 29 10)(font "Arial" (font_size 6)))
(text "inst2" (rect 3 69 27 82)(font "Intel Clear" ))
(port
(pt 0 16)
(input)
(text "IN1" (rect 2 7 23 18)(font "Courier New" (bold))(invisible))
(text "IN1" (rect 2 7 23 18)(font "Courier New" (bold))(invisible))
(line (pt 0 16)(pt 18 16))
)
(port
(pt 0 32)
(input)
(text "IN2" (rect 2 23 23 34)(font "Courier New" (bold))(invisible))
(text "IN2" (rect 2 23 23 34)(font "Courier New" (bold))(invisible))
(line (pt 0 32)(pt 18 32))
)
(port
(pt 0 48)
(input)
(text "IN3" (rect 2 39 23 50)(font "Courier New" (bold))(invisible))
(text "IN3" (rect 2 39 23 50)(font "Courier New" (bold))(invisible))
(line (pt 0 48)(pt 18 48))
)
(port
(pt 0 64)
(input)
(text "IN4" (rect 2 55 23 66)(font "Courier New" (bold))(invisible))
(text "IN4" (rect 2 55 23 66)(font "Courier New" (bold))(invisible))
(line (pt 0 64)(pt 18 64))
)
(port
(pt 64 40)
(output)
(text "OUT" (rect 48 31 69 42)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 31 69 42)(font "Courier New" (bold))(invisible))
(line (pt 46 40)(pt 64 40))
)
(drawing
(line (pt 18 28)(pt 34 28))
(line (pt 18 52)(pt 18 28))
(line (pt 18 67)(pt 18 13))
(line (pt 34 53)(pt 18 53))
(arc (pt 34 52)(pt 34 28)(rect 22 28 47 53))
)
)
(symbol
(rect 232 400 296 480)
(text "AND4" (rect 1 0 29 10)(font "Arial" (font_size 6)))
(text "inst3" (rect 3 69 27 82)(font "Intel Clear" ))
(port
(pt 0 16)
(input)
(text "IN1" (rect 2 7 23 18)(font "Courier New" (bold))(invisible))
(text "IN1" (rect 2 7 23 18)(font "Courier New" (bold))(invisible))
(line (pt 0 16)(pt 18 16))
)
(port
(pt 0 32)
(input)
(text "IN2" (rect 2 23 23 34)(font "Courier New" (bold))(invisible))
(text "IN2" (rect 2 23 23 34)(font "Courier New" (bold))(invisible))
(line (pt 0 32)(pt 18 32))
)
(port
(pt 0 48)
(input)
(text "IN3" (rect 2 39 23 50)(font "Courier New" (bold))(invisible))
(text "IN3" (rect 2 39 23 50)(font "Courier New" (bold))(invisible))
(line (pt 0 48)(pt 18 48))
)
(port
(pt 0 64)
(input)
(text "IN4" (rect 2 55 23 66)(font "Courier New" (bold))(invisible))
(text "IN4" (rect 2 55 23 66)(font "Courier New" (bold))(invisible))
(line (pt 0 64)(pt 18 64))
)
(port
(pt 64 40)
(output)
(text "OUT" (rect 48 31 69 42)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 31 69 42)(font "Courier New" (bold))(invisible))
(line (pt 46 40)(pt 64 40))
)
(drawing
(line (pt 18 28)(pt 34 28))
(line (pt 18 52)(pt 18 28))
(line (pt 18 67)(pt 18 13))
(line (pt 34 53)(pt 18 53))
(arc (pt 34 52)(pt 34 28)(rect 22 28 47 53))
)
)
(symbol
(rect 136 64 168 112)
(text "NOT" (rect 22 1 32 22)(font "Arial" (font_size 6))(vertical))
(text "inst4" (rect -2 3 11 28)(font "Intel Clear" )(vertical))
(port
(pt 16 0)
(input)
(text "IN" (rect 2 7 16 18)(font "Courier New" (bold))(invisible))
(text "IN" (rect 14 2 25 16)(font "Courier New" (bold))(vertical)(invisible))
(line (pt 16 0)(pt 16 13))
)
(port
(pt 16 48)
(output)
(text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 14 32 25 53)(font "Courier New" (bold))(vertical)(invisible))
(line (pt 16 39)(pt 16 48))
)
(drawing
(line (pt 7 13)(pt 25 13))
(line (pt 25 13)(pt 16 31))
(line (pt 7 13)(pt 16 31))
(circle (rect 12 31 20 39))
)
(rotate270)
)
(symbol
(rect 88 64 120 112)
(text "NOT" (rect 22 1 32 22)(font "Arial" (font_size 6))(vertical))
(text "inst5" (rect -2 3 11 27)(font "Intel Clear" )(vertical))
(port
(pt 16 0)
(input)
(text "IN" (rect 2 7 16 18)(font "Courier New" (bold))(invisible))
(text "IN" (rect 14 2 25 16)(font "Courier New" (bold))(vertical)(invisible))
(line (pt 16 0)(pt 16 13))
)
(port
(pt 16 48)
(output)
(text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 14 32 25 53)(font "Courier New" (bold))(vertical)(invisible))
(line (pt 16 39)(pt 16 48))
)
(drawing
(line (pt 7 13)(pt 25 13))
(line (pt 25 13)(pt 16 31))
(line (pt 7 13)(pt 16 31))
(circle (rect 12 31 20 39))
)
(rotate270)
)
(symbol
(rect 8 64 40 112)
(text "NOT" (rect 22 1 32 22)(font "Arial" (font_size 6))(vertical))
(text "inst7" (rect -2 3 11 27)(font "Intel Clear" )(vertical))
(port
(pt 16 0)
(input)
(text "IN" (rect 2 7 16 18)(font "Courier New" (bold))(invisible))
(text "IN" (rect 14 2 25 16)(font "Courier New" (bold))(vertical)(invisible))
(line (pt 16 0)(pt 16 13))
)
(port
(pt 16 48)
(output)
(text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 14 32 25 53)(font "Courier New" (bold))(vertical)(invisible))
(line (pt 16 39)(pt 16 48))
)
(drawing
(line (pt 7 13)(pt 25 13))
(line (pt 25 13)(pt 16 31))
(line (pt 7 13)(pt 16 31))
(circle (rect 12 31 20 39))
)
(rotate270)
)
(connector
(pt 24 152)
(pt 232 152)
)
(connector
(pt 24 240)
(pt 232 240)
)
(connector
(pt 24 328)
(pt 232 328)
)
(connector
(pt 24 416)
(pt 232 416)
)
(connector
(pt 24 112)
(pt 24 152)
)
(connector
(pt 24 152)
(pt 24 240)
)
(connector
(pt 24 240)
(pt 24 328)
)
(connector
(pt 24 328)
(pt 24 416)
)
(connector
(pt 48 168)
(pt 232 168)
)
(connector
(pt 48 256)
(pt 232 256)
)
(connector
(pt 48 344)
(pt 232 344)
)
(connector
(pt 48 432)
(pt 232 432)
)
(connector
(pt 48 56)
(pt 48 168)
)
(connector
(pt 48 168)
(pt 48 256)
)
(connector
(pt 48 256)
(pt 48 344)
)
(connector
(pt 48 344)
(pt 48 432)
)
(connector
(pt 128 64)
(pt 152 64)
)
(connector
(pt 80 64)
(pt 104 64)
)
(connector
(pt 104 184)
(pt 232 184)
)
(connector
(pt 152 200)
(pt 232 200)
)
(connector
(pt 104 272)
(pt 232 272)
)
(connector
(pt 104 112)
(pt 104 184)
)
(connector
(pt 104 184)
(pt 104 272)
)
(connector
(pt 128 288)
(pt 232 288)
)
(connector
(pt 128 56)
(pt 128 64)
)
(connector
(pt 80 360)
(pt 232 360)
)
(connector
(pt 80 448)
(pt 232 448)
)
(connector
(pt 80 56)
(pt 80 64)
)
(connector
(pt 80 64)
(pt 80 360)
)
(connector
(pt 80 360)
(pt 80 448)
)
(connector
(pt 152 376)
(pt 232 376)
)
(connector
(pt 152 112)
(pt 152 200)
)
(connector
(pt 152 200)
(pt 152 376)
)
(connector
(pt 128 464)
(pt 232 464)
)
(connector
(pt 128 64)
(pt 128 288)
)
(connector
(pt 128 288)
(pt 128 464)
)
(connector
(pt 296 440)
(pt 304 440)
)
(connector
(pt 24 64)
(pt 24 56)
)
(junction (pt 24 152))
(junction (pt 24 240))
(junction (pt 24 328))
(junction (pt 48 168))
(junction (pt 48 256))
(junction (pt 48 344))
(junction (pt 104 184))
(junction (pt 128 64))
(junction (pt 80 64))
(junction (pt 80 360))
(junction (pt 152 200))
(junction (pt 128 288))

31
1ano/isd/quartus-projects/DecoderDemo/DecoderDemo.qpf Normal file
View File

@ -0,0 +1,31 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2020 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
# Date created = 11:42:26 November 04, 2022
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "20.1"
DATE = "11:42:26 November 04, 2022"
# Revisions
PROJECT_REVISION = "DecoderDemo"

61
1ano/isd/quartus-projects/DecoderDemo/DecoderDemo.qsf Normal file
View File

@ -0,0 +1,61 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2020 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
# Date created = 11:42:27 November 04, 2022
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# DecoderDemo_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE auto
set_global_assignment -name TOP_LEVEL_ENTITY Dec2_4
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:42:27 NOVEMBER 04, 2022"
set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
set_global_assignment -name BDF_FILE Dec2_4.bdf
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VECTOR_WAVEFORM_FILE WaveformDecoderNode.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform1.vwf
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

BIN
1ano/isd/quartus-projects/DecoderDemo/DecoderDemo.qws Normal file
View File

Binary file not shown.

22
1ano/isd/quartus-projects/DecoderDemo/EqCmpDemo.bdf Normal file
View File

@ -0,0 +1,22 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "graphic" (version "1.4"))

694
1ano/isd/quartus-projects/DecoderDemo/Waveform.vwf Normal file
View File

@ -0,0 +1,694 @@
/*<simulation_settings>
<ftestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off DecoderDemo -c DecoderDemo --vector_source="/home/tiagorg/repos/DecoderDemo/Waveform.vwf" --testbench_file="/home/tiagorg/repos/DecoderDemo/simulation/qsim/Waveform.vwf.vht"</ftestbench_cmd>
<ttestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off DecoderDemo -c DecoderDemo --vector_source="/home/tiagorg/repos/DecoderDemo/Waveform.vwf" --testbench_file="/home/tiagorg/repos/DecoderDemo/simulation/qsim/Waveform.vwf.vht"</ttestbench_cmd>
<fnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/DecoderDemo/simulation/qsim/" DecoderDemo -c DecoderDemo</fnetlist_cmd>
<tnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/DecoderDemo/simulation/qsim/" DecoderDemo -c DecoderDemo</tnetlist_cmd>
<modelsim_script>onerror {exit -code 1}
vlib work
vcom -work work DecoderDemo.vho
vcom -work work Waveform.vwf.vht
vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.Dec2_4_vhd_vec_tst
vcd file -direction DecoderDemo.msim.vcd
vcd add -internal Dec2_4_vhd_vec_tst/*
vcd add -internal Dec2_4_vhd_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script>
<modelsim_script_timing>onerror {exit -code 1}
vlib work
vcom -work work DecoderDemo.vho
vcom -work work Waveform.vwf.vht
vsim -novopt -c -t 1ps -sdfmax Dec2_4_vhd_vec_tst/i1=DecoderDemo_vhd.sdo -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.Dec2_4_vhd_vec_tst
vcd file -direction DecoderDemo.msim.vcd
vcd add -internal Dec2_4_vhd_vec_tst/*
vcd add -internal Dec2_4_vhd_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script_timing>
<hdl_lang>vhdl</hdl_lang>
</simulation_settings>*/
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
HEADER
{
VERSION = 1;
TIME_UNIT = ns;
DATA_OFFSET = 0.0;
DATA_DURATION = 1000.0;
SIMULATION_TIME = 0.0;
GRID_PHASE = 0.0;
GRID_PERIOD = 10.0;
GRID_DUTY_CYCLE = 50;
}
SIGNAL("E0L")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("E1")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("X0")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("X1")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("Y0")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("Y1")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("Y2")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("Y3")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
TRANSITION_LIST("E0L")
{
NODE
{
REPEAT = 1;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 65.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 20.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 15.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 30.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 15.0;
LEVEL 0 FOR 20.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 15.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 15.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 20.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 15.0;
LEVEL 0 FOR 30.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 35.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 20.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 30.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 20.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 15.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 45.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
}
}
TRANSITION_LIST("E1")
{
NODE
{
REPEAT = 1;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 15.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 20.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 15.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 20.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 15.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 15.0;
LEVEL 0 FOR 15.0;
LEVEL 1 FOR 30.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 15.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 30.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 25.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 15.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 15.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 20.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 15.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 15.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 15.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 20.0;
LEVEL 0 FOR 25.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 25.0;
LEVEL 0 FOR 15.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 25.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 15.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 15.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 20.0;
LEVEL 0 FOR 15.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 5.0;
}
}
TRANSITION_LIST("X0")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 15.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 15.0;
LEVEL 1 FOR 20.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 35.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 40.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 15.0;
LEVEL 1 FOR 15.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 15.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 15.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 15.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 20.0;
LEVEL 1 FOR 15.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 35.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 20.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 20.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 15.0;
LEVEL 1 FOR 15.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 20.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 15.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 15.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 40.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 35.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 30.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 5.0;
}
}
TRANSITION_LIST("X1")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 15.0;
LEVEL 0 FOR 25.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 15.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 20.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 20.0;
LEVEL 1 FOR 20.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 20.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 20.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 20.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 20.0;
LEVEL 1 FOR 15.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 20.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 25.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 25.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 15.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 15.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 20.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 15.0;
LEVEL 1 FOR 20.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 25.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 15.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 25.0;
LEVEL 0 FOR 15.0;
LEVEL 1 FOR 15.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 25.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 20.0;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 20.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 10.0;
}
}
TRANSITION_LIST("Y0")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("Y1")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("Y2")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("Y3")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
DISPLAY_LINE
{
CHANNEL = "E0L";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 0;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "E1";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 1;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "X0";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 2;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "X1";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 3;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "Y0";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 4;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "Y1";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 5;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "Y2";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 6;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "Y3";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 7;
TREE_LEVEL = 0;
}
TIME_BAR
{
TIME = 0;
MASTER = TRUE;
}
;

328
1ano/isd/quartus-projects/DecoderDemo/Waveform1.vwf Normal file
View File

@ -0,0 +1,328 @@
/*<simulation_settings>
<ftestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off DecoderDemo -c DecoderDemo --vector_source="/home/tiagorg/repos/DecoderDemo/Waveform1.vwf" --testbench_file="/home/tiagorg/repos/DecoderDemo/simulation/qsim/Waveform1.vwf.vht"</ftestbench_cmd>
<ttestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off DecoderDemo -c DecoderDemo --vector_source="/home/tiagorg/repos/DecoderDemo/Waveform1.vwf" --testbench_file="/home/tiagorg/repos/DecoderDemo/simulation/qsim/Waveform1.vwf.vht"</ttestbench_cmd>
<fnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/DecoderDemo/simulation/qsim/" DecoderDemo -c DecoderDemo</fnetlist_cmd>
<tnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/DecoderDemo/simulation/qsim/" DecoderDemo -c DecoderDemo</tnetlist_cmd>
<modelsim_script>onerror {exit -code 1}
vlib work
vcom -work work DecoderDemo.vho
vcom -work work Waveform1.vwf.vht
vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.Dec2_4_vhd_vec_tst
vcd file -direction DecoderDemo.msim.vcd
vcd add -internal Dec2_4_vhd_vec_tst/*
vcd add -internal Dec2_4_vhd_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script>
<modelsim_script_timing>onerror {exit -code 1}
vlib work
vcom -work work DecoderDemo.vho
vcom -work work Waveform1.vwf.vht
vsim -novopt -c -t 1ps -sdfmax Dec2_4_vhd_vec_tst/i1=DecoderDemo_vhd.sdo -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.Dec2_4_vhd_vec_tst
vcd file -direction DecoderDemo.msim.vcd
vcd add -internal Dec2_4_vhd_vec_tst/*
vcd add -internal Dec2_4_vhd_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script_timing>
<hdl_lang>vhdl</hdl_lang>
</simulation_settings>*/
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
HEADER
{
VERSION = 1;
TIME_UNIT = ns;
DATA_OFFSET = 0.0;
DATA_DURATION = 1000.0;
SIMULATION_TIME = 0.0;
GRID_PHASE = 0.0;
GRID_PERIOD = 10.0;
GRID_DUTY_CYCLE = 50;
}
SIGNAL("E0L")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("E1")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("X0")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("X1")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("Y0")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("Y1")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("Y2")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("Y3")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
TRANSITION_LIST("E0L")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 40;
LEVEL 0 FOR 12.5;
LEVEL 1 FOR 12.5;
}
}
}
TRANSITION_LIST("E1")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 20;
LEVEL 0 FOR 25.0;
LEVEL 1 FOR 25.0;
}
}
}
TRANSITION_LIST("X0")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 10;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
}
}
}
TRANSITION_LIST("X1")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 5;
LEVEL 0 FOR 100.0;
LEVEL 1 FOR 100.0;
}
}
}
TRANSITION_LIST("Y0")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("Y1")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("Y2")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("Y3")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
DISPLAY_LINE
{
CHANNEL = "E0L";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 0;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "E1";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 1;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "X0";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 2;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "X1";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 3;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "Y0";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 4;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "Y1";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 5;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "Y2";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 6;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "Y3";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 7;
TREE_LEVEL = 0;
}
TIME_BAR
{
TIME = 0;
MASTER = TRUE;
}
;

330
1ano/isd/quartus-projects/DecoderDemo/WaveformDecoderNode.vwf Normal file
View File

@ -0,0 +1,330 @@
/*<simulation_settings>
<ftestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off DecoderDemo -c DecoderDemo --vector_source="/home/rubeng/Documents/UAlinux/ISD/Quartus Prime/WaveformDecoderNode.vwf" --testbench_file="/home/rubeng/Documents/UAlinux/ISD/Quartus Prime/simulation/qsim/WaveformDecoderNode.vwf.vht"</ftestbench_cmd>
<ttestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off DecoderDemo -c DecoderDemo --vector_source="/home/rubeng/Documents/UAlinux/ISD/Quartus Prime/WaveformDecoderNode.vwf" --testbench_file="/home/rubeng/Documents/UAlinux/ISD/Quartus Prime/simulation/qsim/WaveformDecoderNode.vwf.vht"</ttestbench_cmd>
<fnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="/home/rubeng/Documents/UAlinux/ISD/Quartus Prime/simulation/qsim/" DecoderDemo -c DecoderDemo</fnetlist_cmd>
<tnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=vhdl --output_directory="/home/rubeng/Documents/UAlinux/ISD/Quartus Prime/simulation/qsim/" DecoderDemo -c DecoderDemo</tnetlist_cmd>
<modelsim_script>onerror {exit -code 1}
vlib work
vcom -work work DecoderDemo.vho
vcom -work work WaveformDecoderNode.vwf.vht
vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.Dec2_4_vhd_vec_tst
vcd file -direction DecoderDemo.msim.vcd
vcd add -internal Dec2_4_vhd_vec_tst/*
vcd add -internal Dec2_4_vhd_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script>
<modelsim_script_timing>onerror {exit -code 1}
vlib work
vcom -work work DecoderDemo.vho
vcom -work work WaveformDecoderNode.vwf.vht
vsim -c -t 1ps -sdfmax Dec2_4_vhd_vec_tst/i1=DecoderDemo_vhd.sdo -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.Dec2_4_vhd_vec_tst
vcd file -direction DecoderDemo.msim.vcd
vcd add -internal Dec2_4_vhd_vec_tst/*
vcd add -internal Dec2_4_vhd_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script_timing>
<hdl_lang>vhdl</hdl_lang>
</simulation_settings>*/
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
HEADER
{
VERSION = 1;
TIME_UNIT = ns;
DATA_OFFSET = 0.0;
DATA_DURATION = 1000.0;
SIMULATION_TIME = 0.0;
GRID_PHASE = 0.0;
GRID_PERIOD = 10.0;
GRID_DUTY_CYCLE = 50;
}
SIGNAL("E0L")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("E1")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("X0")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("Y0")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("Y1")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("Y2")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("Y3")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("X1")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
TRANSITION_LIST("E0L")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 5;
LEVEL 0 FOR 100.0;
LEVEL 1 FOR 100.0;
}
}
}
TRANSITION_LIST("E1")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 10;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
}
}
}
TRANSITION_LIST("X0")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 40;
LEVEL 0 FOR 12.5;
LEVEL 1 FOR 12.5;
}
}
}
TRANSITION_LIST("Y0")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("Y1")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("Y2")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("Y3")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("X1")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 20;
LEVEL 0 FOR 25.0;
LEVEL 1 FOR 25.0;
}
}
}
DISPLAY_LINE
{
CHANNEL = "E0L";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 0;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "E1";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 1;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "X1";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 2;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "X0";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 3;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "Y0";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 4;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "Y1";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 5;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "Y2";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 6;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "Y3";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 7;
TREE_LEVEL = 0;
}
TIME_BAR
{
TIME = 0;
MASTER = TRUE;
}
;

308
1ano/isd/quartus-projects/DecoderDemo/WaveformDecoderNoide.vwf Normal file
View File

@ -0,0 +1,308 @@
/*<simulation_settings>
<ftestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off DecoderDemo -c DecoderDemo --vector_source="/home/rubeng/Documents/UAlinux/ISD/Quartus Prime/Waveform.vwf" --testbench_file="/home/rubeng/Documents/UAlinux/ISD/Quartus Prime/simulation/qsim/Waveform.vwf.vt"</ftestbench_cmd>
<ttestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off DecoderDemo -c DecoderDemo --vector_source="/home/rubeng/Documents/UAlinux/ISD/Quartus Prime/Waveform.vwf" --testbench_file="/home/rubeng/Documents/UAlinux/ISD/Quartus Prime/simulation/qsim/Waveform.vwf.vt"</ttestbench_cmd>
<fnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="/home/rubeng/Documents/UAlinux/ISD/Quartus Prime/simulation/qsim/" DecoderDemo -c DecoderDemo</fnetlist_cmd>
<tnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=verilog --output_directory="/home/rubeng/Documents/UAlinux/ISD/Quartus Prime/simulation/qsim/" DecoderDemo -c DecoderDemo</tnetlist_cmd>
<modelsim_script>onerror {exit -code 1}
vlib work
vlog -work work DecoderDemo.vo
vlog -work work Waveform.vwf.vt
vsim -novopt -c -t 1ps -L cycloneive_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.Dec2_4_vlg_vec_tst
vcd file -direction DecoderDemo.msim.vcd
vcd add -internal Dec2_4_vlg_vec_tst/*
vcd add -internal Dec2_4_vlg_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script>
<modelsim_script_timing>onerror {exit -code 1}
vlib work
vlog -work work DecoderDemo.vo
vlog -work work Waveform.vwf.vt
vsim -novopt -c -t 1ps -L cycloneive_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.Dec2_4_vlg_vec_tst
vcd file -direction DecoderDemo.msim.vcd
vcd add -internal Dec2_4_vlg_vec_tst/*
vcd add -internal Dec2_4_vlg_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script_timing>
<hdl_lang>verilog</hdl_lang>
</simulation_settings>*/
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
HEADER
{
VERSION = 1;
TIME_UNIT = ns;
DATA_OFFSET = 0.0;
DATA_DURATION = 1000.0;
SIMULATION_TIME = 0.0;
GRID_PHASE = 0.0;
GRID_PERIOD = 10.0;
GRID_DUTY_CYCLE = 50;
}
SIGNAL("E0L")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("E1")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("X0")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("X1")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("Y0")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("Y1")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("Y2")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("Y3")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
TRANSITION_LIST("E0L")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 1000.0;
}
}
TRANSITION_LIST("E1")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 1000.0;
}
}
TRANSITION_LIST("X0")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 1000.0;
}
}
TRANSITION_LIST("X1")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 1000.0;
}
}
TRANSITION_LIST("Y0")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("Y1")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("Y2")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("Y3")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
DISPLAY_LINE
{
CHANNEL = "E0L";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 0;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "E1";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 1;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "X0";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 2;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "X1";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 3;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "Y0";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 4;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "Y1";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 5;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "Y2";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 6;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "Y3";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 7;
TREE_LEVEL = 0;
}
TIME_BAR
{
TIME = 0;
MASTER = TRUE;
}
;

BIN
1ano/isd/quartus-projects/DecoderDemo/db/.cmp.kpt Normal file
View File

Binary file not shown.

BIN
1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.(0).cnf.cdb Normal file
View File

Binary file not shown.

BIN
1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.(0).cnf.hdb Normal file
View File

Binary file not shown.

7
1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.asm.qmsg Normal file
View File

@ -0,0 +1,7 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1668463009510 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1668463009510 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 14 21:56:49 2022 " "Processing started: Mon Nov 14 21:56:49 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1668463009510 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1668463009510 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off DecoderDemo -c DecoderDemo " "Command: quartus_asm --read_settings_files=off --write_settings_files=off DecoderDemo -c DecoderDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1668463009510 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1668463009605 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1668463009774 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1668463009781 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "352 " "Peak virtual memory: 352 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1668463009828 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 14 21:56:49 2022 " "Processing ended: Mon Nov 14 21:56:49 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1668463009828 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1668463009828 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1668463009828 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1668463009828 ""}

BIN
1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.asm.rdb Normal file
View File

Binary file not shown.

BIN
1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.asm_labs.ddb Normal file
View File

Binary file not shown.

5
1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.cbx.xml Normal file
View File

@ -0,0 +1,5 @@
<?xml version="1.0" ?>
<LOG_ROOT>
<PROJECT NAME="DecoderDemo">
</PROJECT>
</LOG_ROOT>

BIN
1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.cmp.bpm Normal file
View File

Binary file not shown.

BIN
1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.cmp.cdb Normal file
View File

Binary file not shown.

BIN
1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.cmp.hdb Normal file
View File

Binary file not shown.

BIN
1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.cmp.idb Normal file
View File

Binary file not shown.

50
1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.cmp.logdb Normal file
View File

@ -0,0 +1,50 @@
v1
IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,,
IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,,
IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
IO_RULES,CHECK_UNAVAILABLE_LOC,INAPPLICABLE,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,No Location assignments found.,,I/O,,
IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,,
IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000001;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000047;IO_000046;IO_000045;IO_000027;IO_000026;IO_000024;IO_000023;IO_000022;IO_000021;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000033;IO_000034;IO_000042,
IO_RULES_MATRIX,Total Pass,0;0;0;0;0;8;0;0;0;0;0;0;0;4;0;0;0;4;4;0;4;0;0;4;0;8;8;8;0;0,
IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
IO_RULES_MATRIX,Total Inapplicable,8;8;8;8;8;0;8;8;8;8;8;8;8;4;8;8;8;4;4;8;4;8;8;4;8;0;0;0;8;8,
IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
IO_RULES_MATRIX,Y3,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,Y2,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,Y1,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,Y0,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,E1,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,X0,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,X1,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,E0L,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_SUMMARY,Total I/O Rules,30,
IO_RULES_SUMMARY,Number of I/O Rules Passed,9,
IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,21,

BIN
1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.cmp.rdb Normal file
View File

Binary file not shown.

BIN
1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.cmp_merge.kpt Normal file
View File

Binary file not shown.

BIN
1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd Normal file
View File

Binary file not shown.

BIN
1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.cycloneive_io_sim_cache.45um_tt_1200mv_0c_slow.hsd Normal file
View File

Binary file not shown.

BIN
1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.cycloneive_io_sim_cache.45um_tt_1200mv_85c_slow.hsd Normal file
View File

Binary file not shown.

3
1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.db_info Normal file
View File

@ -0,0 +1,3 @@
Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Version_Index = 520278016
Creation_Time = Fri Nov 18 12:22:15 2022

6
1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.eda.qmsg Normal file
View File

@ -0,0 +1,6 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1668463011444 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1668463011449 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 14 21:56:51 2022 " "Processing started: Mon Nov 14 21:56:51 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1668463011449 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1668463011449 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off DecoderDemo -c DecoderDemo " "Command: quartus_eda --read_settings_files=off --write_settings_files=off DecoderDemo -c DecoderDemo" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1668463011449 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1668463011567 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "DecoderDemo.vho /home/tiagorg/repos/DecoderDemo/simulation/modelsim/ simulation " "Generated file DecoderDemo.vho in folder \"/home/tiagorg/repos/DecoderDemo/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1668463011589 ""}
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "600 " "Peak virtual memory: 600 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1668463011596 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 14 21:56:51 2022 " "Processing ended: Mon Nov 14 21:56:51 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1668463011596 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1668463011596 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1668463011596 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1668463011596 ""}

49
1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.fit.qmsg Normal file
View File

@ -0,0 +1,49 @@
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1668463007155 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1668463007156 ""}
{ "Info" "IMPP_MPP_AUTO_ASSIGNED_DEVICE" "DecoderDemo EP4CE6E22C6 " "Automatically selected device EP4CE6E22C6 for design DecoderDemo" { } { } 0 119004 "Automatically selected device %2!s! for design %1!s!" 0 0 "Fitter" 0 -1 1668463007236 ""}
{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "High junction temperature 85 " "High junction temperature operating condition is not set. Assuming a default value of '85'." { } { } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Fitter" 0 -1 1668463007272 ""}
{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "Low junction temperature 0 " "Low junction temperature operating condition is not set. Assuming a default value of '0'." { } { } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Fitter" 0 -1 1668463007272 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1668463007338 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1668463007341 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE10E22C6 " "Device EP4CE10E22C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1668463007365 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15E22C6 " "Device EP4CE15E22C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1668463007365 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE22E22C6 " "Device EP4CE22E22C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1668463007365 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1668463007365 ""}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ 6 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location 6" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/DecoderDemo/" { { 0 { 0 ""} 0 27 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1668463007366 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ 8 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location 8" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/DecoderDemo/" { { 0 { 0 ""} 0 29 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1668463007366 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ 12 " "Pin ~ALTERA_DCLK~ is reserved at location 12" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/DecoderDemo/" { { 0 { 0 ""} 0 31 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1668463007366 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ 13 " "Pin ~ALTERA_DATA0~ is reserved at location 13" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/DecoderDemo/" { { 0 { 0 ""} 0 33 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1668463007366 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ 101 " "Pin ~ALTERA_nCEO~ is reserved at location 101" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/DecoderDemo/" { { 0 { 0 ""} 0 35 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1668463007366 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1668463007366 ""}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1668463007367 ""}
{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "8 8 " "No exact pin location assignment(s) for 8 pins of 8 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1668463007518 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "DecoderDemo.sdc " "Synopsys Design Constraints File file not found: 'DecoderDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1668463007574 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1668463007574 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1668463007574 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1668463007574 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1668463007575 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1668463007575 ""}
{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1668463007575 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1668463007576 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1668463007576 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1668463007576 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1668463007577 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1668463007577 ""}
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1668463007577 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1668463007577 ""}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1668463007577 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1668463007577 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1668463007577 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1668463007577 ""}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "8 unused 2.5V 4 4 0 " "Number of I/O pins in group: 8 (unused VREF, 2.5V VCCIO, 4 input, 4 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Design Software" 0 -1 1668463007578 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Design Software" 0 -1 1668463007578 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1668463007578 ""}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 4 7 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used -- 7 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1668463007578 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 8 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 8 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1668463007578 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 11 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 11 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1668463007578 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 14 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 14 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1668463007578 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 13 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 13 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1668463007578 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 1 9 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 9 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1668463007578 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 13 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 13 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1668463007578 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 12 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 12 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1668463007578 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Design Software" 0 -1 1668463007578 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1668463007578 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1668463007582 ""}
{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1668463007583 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1668463007832 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1668463007843 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1668463007849 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1668463007889 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1668463007889 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1668463007997 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y0 X10_Y11 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y11" { } { { "loc" "" { Generic "/home/tiagorg/repos/DecoderDemo/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y11"} { { 12 { 0 ""} 0 0 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1668463008214 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1668463008214 ""}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1668463008229 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1668463008229 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1668463008229 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1668463008230 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.01 " "Total time spent on timing analysis during the Fitter is 0.01 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1668463008293 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1668463008297 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1668463008381 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1668463008381 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1668463008573 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1668463008782 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/tiagorg/repos/DecoderDemo/output_files/DecoderDemo.fit.smsg " "Generated suppressed messages file /home/tiagorg/repos/DecoderDemo/output_files/DecoderDemo.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1668463008928 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "942 " "Peak virtual memory: 942 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1668463009025 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 14 21:56:49 2022 " "Processing ended: Mon Nov 14 21:56:49 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1668463009025 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1668463009025 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1668463009025 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1668463009025 ""}

18
1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.hier_info Normal file
View File

@ -0,0 +1,18 @@
|Dec2_4
Y3 <= inst.DB_MAX_OUTPUT_PORT_TYPE
E0L => inst7.IN0
E1 => inst.IN1
E1 => inst1.IN1
E1 => inst3.IN1
E1 => inst2.IN1
X1 => inst5.IN0
X1 => inst3.IN2
X1 => inst2.IN2
X0 => inst4.IN0
X0 => inst1.IN3
X0 => inst3.IN3
Y2 <= inst1.DB_MAX_OUTPUT_PORT_TYPE
Y1 <= inst3.DB_MAX_OUTPUT_PORT_TYPE
Y0 <= inst2.DB_MAX_OUTPUT_PORT_TYPE

BIN
1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.hif Normal file
View File

Binary file not shown.

18
1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.lpc.html Normal file
View File

@ -0,0 +1,18 @@
<TABLE>
<TR bgcolor="#C0C0C0">
<TH>Hierarchy</TH>
<TH>Input</TH>
<TH>Constant Input</TH>
<TH>Unused Input</TH>
<TH>Floating Input</TH>
<TH>Output</TH>
<TH>Constant Output</TH>
<TH>Unused Output</TH>
<TH>Floating Output</TH>
<TH>Bidir</TH>
<TH>Constant Bidir</TH>
<TH>Unused Bidir</TH>
<TH>Input only Bidir</TH>
<TH>Output only Bidir</TH>
</TR>
</TABLE>

BIN
1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.lpc.rdb Normal file
View File

Binary file not shown.

5
1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.lpc.txt Normal file
View File

@ -0,0 +1,5 @@
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Legal Partition Candidates ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

BIN
1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.map.ammdb Normal file
View File

Binary file not shown.

BIN
1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.map.bpm Normal file
View File

Binary file not shown.

BIN
1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.map.cdb Normal file
View File

Binary file not shown.

BIN
1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.map.hdb Normal file
View File

Binary file not shown.

BIN
1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.map.kpt Normal file
View File

Binary file not shown.

1
1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.map.logdb Normal file
View File

@ -0,0 +1 @@
v1

11
1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.map.qmsg Normal file
View File

@ -0,0 +1,11 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1668463001396 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1668463001396 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 14 21:56:41 2022 " "Processing started: Mon Nov 14 21:56:41 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1668463001396 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1668463001396 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off DecoderDemo -c DecoderDemo " "Command: quartus_map --read_settings_files=on --write_settings_files=off DecoderDemo -c DecoderDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1668463001396 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1668463001483 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1668463001483 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Dec2_4.bdf 1 1 " "Found 1 design units, including 1 entities, in source file Dec2_4.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Dec2_4 " "Found entity 1: Dec2_4" { } { { "Dec2_4.bdf" "" { Schematic "/home/tiagorg/repos/DecoderDemo/Dec2_4.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1668463006150 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1668463006150 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "Dec2_4 " "Elaborating entity \"Dec2_4\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1668463006177 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1668463006421 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1668463006616 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1668463006616 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "12 " "Implemented 12 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "4 " "Implemented 4 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1668463006630 ""} { "Info" "ICUT_CUT_TM_OPINS" "4 " "Implemented 4 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1668463006630 ""} { "Info" "ICUT_CUT_TM_LCELLS" "4 " "Implemented 4 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1668463006630 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1668463006630 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "402 " "Peak virtual memory: 402 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1668463006633 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 14 21:56:46 2022 " "Processing ended: Mon Nov 14 21:56:46 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1668463006633 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1668463006633 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:13 " "Total CPU time (on all processors): 00:00:13" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1668463006633 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1668463006633 ""}

BIN
1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.map.rdb Normal file
View File

Binary file not shown.

BIN
1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.map_bb.cdb Normal file
View File

Binary file not shown.

BIN
1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.map_bb.hdb Normal file
View File

Binary file not shown.

1
1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.map_bb.logdb Normal file
View File

@ -0,0 +1 @@
v1

BIN
1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.pre_map.hdb Normal file
View File

Binary file not shown.

BIN
1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.root_partition.map.reg_db.cdb Normal file
View File

Binary file not shown.

BIN
1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.routing.rdb Normal file
View File

Binary file not shown.

BIN
1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.rtlv.hdb Normal file
View File

Binary file not shown.

BIN
1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.rtlv_sg.cdb Normal file
View File

Binary file not shown.

BIN
1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.rtlv_sg_swap.cdb Normal file
View File

Binary file not shown.

BIN
1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.sld_design_entry.sci Normal file
View File

Binary file not shown.

BIN
1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.sld_design_entry_dsc.sci Normal file
View File

Binary file not shown.

1
1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.smart_action.txt Normal file
View File

@ -0,0 +1 @@
DONE

49
1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.sta.qmsg Normal file
View File

@ -0,0 +1,49 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1668463010289 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1668463010289 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 14 21:56:50 2022 " "Processing started: Mon Nov 14 21:56:50 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1668463010289 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1668463010289 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta DecoderDemo -c DecoderDemo " "Command: quartus_sta DecoderDemo -c DecoderDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1668463010289 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1668463010309 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1668463010348 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1668463010348 ""}
{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "High junction temperature 85 " "High junction temperature operating condition is not set. Assuming a default value of '85'." { } { } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Timing Analyzer" 0 -1 1668463010383 ""}
{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "Low junction temperature 0 " "Low junction temperature operating condition is not set. Assuming a default value of '0'." { } { } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Timing Analyzer" 0 -1 1668463010383 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "DecoderDemo.sdc " "Synopsys Design Constraints File file not found: 'DecoderDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1668463010479 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1668463010479 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1668463010479 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1668463010479 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1668463010479 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1668463010479 ""}
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1668463010480 ""}
{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1668463010481 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1668463010481 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668463010482 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668463010483 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668463010484 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668463010484 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668463010484 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668463010485 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1668463010486 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1668463010498 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1668463010702 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1668463010713 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1668463010713 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1668463010713 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1668463010713 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668463010713 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668463010714 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668463010714 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668463010715 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668463010715 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668463010715 ""}
{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1668463010716 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1668463010753 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1668463010753 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1668463010753 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1668463010753 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668463010754 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668463010754 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668463010754 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668463010755 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668463010755 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1668463010955 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1668463010955 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "465 " "Peak virtual memory: 465 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1668463010962 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 14 21:56:50 2022 " "Processing ended: Mon Nov 14 21:56:50 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1668463010962 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1668463010962 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1668463010962 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1668463010962 ""}

BIN
1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.sta.rdb Normal file
View File

Binary file not shown.

BIN
1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.sta_cmp.6_slow_1200mv_85c.tdb Normal file
View File

Binary file not shown.

BIN
1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.tis_db_list.ddb Normal file
View File

Binary file not shown.

BIN
1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.tiscmp.fast_1200mv_0c.ddb Normal file
View File

Binary file not shown.

BIN
1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.tiscmp.slow_1200mv_0c.ddb Normal file
View File

Binary file not shown.

BIN
1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.tiscmp.slow_1200mv_85c.ddb Normal file
View File

Binary file not shown.

BIN
1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.vpr.ammdb Normal file
View File

Binary file not shown.

41
1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo_partition_pins.json Normal file
View File

@ -0,0 +1,41 @@
{
"partitions" : [
{
"name" : "Top",
"pins" : [
{
"name" : "Y3",
"strict" : false
},
{
"name" : "Y2",
"strict" : false
},
{
"name" : "Y1",
"strict" : false
},
{
"name" : "Y0",
"strict" : false
},
{
"name" : "E1",
"strict" : false
},
{
"name" : "X0",
"strict" : false
},
{
"name" : "X1",
"strict" : false
},
{
"name" : "E0L",
"strict" : false
}
]
}
]
}

130
1ano/isd/quartus-projects/DecoderDemo/db/prev_cmp_DecoderDemo.qmsg Normal file
View File

@ -0,0 +1,130 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1668462005146 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1668462005146 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 14 21:40:05 2022 " "Processing started: Mon Nov 14 21:40:05 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1668462005146 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1668462005146 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off DecoderDemo -c DecoderDemo " "Command: quartus_map --read_settings_files=on --write_settings_files=off DecoderDemo -c DecoderDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1668462005146 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1668462005241 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1668462005241 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Dec2_4.bdf 1 1 " "Found 1 design units, including 1 entities, in source file Dec2_4.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Dec2_4 " "Found entity 1: Dec2_4" { } { { "Dec2_4.bdf" "" { Schematic "/home/tiagorg/repos/DecoderDemo/Dec2_4.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1668462009856 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1668462009856 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "Dec2_4 " "Elaborating entity \"Dec2_4\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1668462009881 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1668462010158 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1668462010370 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1668462010370 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "12 " "Implemented 12 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "4 " "Implemented 4 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1668462010407 ""} { "Info" "ICUT_CUT_TM_OPINS" "4 " "Implemented 4 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1668462010407 ""} { "Info" "ICUT_CUT_TM_LCELLS" "4 " "Implemented 4 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1668462010407 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1668462010407 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "398 " "Peak virtual memory: 398 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1668462010410 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 14 21:40:10 2022 " "Processing ended: Mon Nov 14 21:40:10 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1668462010410 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1668462010410 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:13 " "Total CPU time (on all processors): 00:00:13" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1668462010410 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1668462010410 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1668462010962 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1668462010962 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 14 21:40:10 2022 " "Processing started: Mon Nov 14 21:40:10 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1668462010962 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1668462010962 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off DecoderDemo -c DecoderDemo " "Command: quartus_fit --read_settings_files=off --write_settings_files=off DecoderDemo -c DecoderDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1668462010962 ""}
{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1668462011028 ""}
{ "Info" "0" "" "Project = DecoderDemo" { } { } 0 0 "Project = DecoderDemo" 0 0 "Fitter" 0 0 1668462011029 ""}
{ "Info" "0" "" "Revision = DecoderDemo" { } { } 0 0 "Revision = DecoderDemo" 0 0 "Fitter" 0 0 1668462011029 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1668462011053 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1668462011053 ""}
{ "Info" "IMPP_MPP_AUTO_ASSIGNED_DEVICE" "DecoderDemo EP4CE6E22C6 " "Automatically selected device EP4CE6E22C6 for design DecoderDemo" { } { } 0 119004 "Automatically selected device %2!s! for design %1!s!" 0 0 "Fitter" 0 -1 1668462011132 ""}
{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "High junction temperature 85 " "High junction temperature operating condition is not set. Assuming a default value of '85'." { } { } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Fitter" 0 -1 1668462011166 ""}
{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "Low junction temperature 0 " "Low junction temperature operating condition is not set. Assuming a default value of '0'." { } { } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Fitter" 0 -1 1668462011166 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1668462011241 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1668462011245 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE10E22C6 " "Device EP4CE10E22C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1668462011294 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15E22C6 " "Device EP4CE15E22C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1668462011294 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE22E22C6 " "Device EP4CE22E22C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1668462011294 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1668462011294 ""}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ 6 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location 6" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/DecoderDemo/" { { 0 { 0 ""} 0 27 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1668462011298 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ 8 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location 8" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/DecoderDemo/" { { 0 { 0 ""} 0 29 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1668462011298 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ 12 " "Pin ~ALTERA_DCLK~ is reserved at location 12" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/DecoderDemo/" { { 0 { 0 ""} 0 31 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1668462011298 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ 13 " "Pin ~ALTERA_DATA0~ is reserved at location 13" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/DecoderDemo/" { { 0 { 0 ""} 0 33 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1668462011298 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ 101 " "Pin ~ALTERA_nCEO~ is reserved at location 101" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/DecoderDemo/" { { 0 { 0 ""} 0 35 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1668462011298 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1668462011298 ""}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1668462011300 ""}
{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "8 8 " "No exact pin location assignment(s) for 8 pins of 8 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1668462011464 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "DecoderDemo.sdc " "Synopsys Design Constraints File file not found: 'DecoderDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1668462011528 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1668462011528 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1668462011528 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1668462011528 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1668462011529 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1668462011529 ""}
{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1668462011529 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1668462011532 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1668462011532 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1668462011532 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1668462011532 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1668462011532 ""}
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1668462011532 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1668462011532 ""}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1668462011532 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1668462011532 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1668462011532 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1668462011532 ""}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "8 unused 2.5V 4 4 0 " "Number of I/O pins in group: 8 (unused VREF, 2.5V VCCIO, 4 input, 4 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Design Software" 0 -1 1668462011534 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Design Software" 0 -1 1668462011534 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1668462011534 ""}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 4 7 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used -- 7 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1668462011535 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 8 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 8 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1668462011535 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 11 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 11 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1668462011535 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 14 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 14 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1668462011535 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 13 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 13 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1668462011535 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 1 9 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 9 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1668462011535 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 13 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 13 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1668462011535 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 12 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 12 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1668462011535 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Design Software" 0 -1 1668462011535 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1668462011535 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1668462011538 ""}
{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1668462011542 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1668462011795 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1668462011811 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1668462011819 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1668462011863 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1668462011863 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1668462011977 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y0 X10_Y11 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y11" { } { { "loc" "" { Generic "/home/tiagorg/repos/DecoderDemo/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y11"} { { 12 { 0 ""} 0 0 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1668462012210 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1668462012210 ""}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1668462012235 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1668462012235 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1668462012235 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1668462012236 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.01 " "Total time spent on timing analysis during the Fitter is 0.01 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1668462012307 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1668462012310 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1668462012397 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1668462012398 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1668462012591 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1668462012807 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/tiagorg/repos/DecoderDemo/output_files/DecoderDemo.fit.smsg " "Generated suppressed messages file /home/tiagorg/repos/DecoderDemo/output_files/DecoderDemo.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1668462012957 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "941 " "Peak virtual memory: 941 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1668462013056 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 14 21:40:13 2022 " "Processing ended: Mon Nov 14 21:40:13 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1668462013056 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1668462013056 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1668462013056 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1668462013056 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1668462013569 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1668462013569 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 14 21:40:13 2022 " "Processing started: Mon Nov 14 21:40:13 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1668462013569 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1668462013569 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off DecoderDemo -c DecoderDemo " "Command: quartus_asm --read_settings_files=off --write_settings_files=off DecoderDemo -c DecoderDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1668462013569 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1668462013663 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1668462013824 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1668462013832 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "352 " "Peak virtual memory: 352 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1668462013883 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 14 21:40:13 2022 " "Processing ended: Mon Nov 14 21:40:13 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1668462013883 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1668462013883 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1668462013883 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1668462013883 ""}
{ "Info" "IFLOW_DISABLED_MODULE" "Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1668462014024 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1668462014420 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1668462014420 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 14 21:40:14 2022 " "Processing started: Mon Nov 14 21:40:14 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1668462014420 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1668462014420 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta DecoderDemo -c DecoderDemo " "Command: quartus_sta DecoderDemo -c DecoderDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1668462014420 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1668462014441 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1668462014478 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1668462014478 ""}
{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "High junction temperature 85 " "High junction temperature operating condition is not set. Assuming a default value of '85'." { } { } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Timing Analyzer" 0 -1 1668462014516 ""}
{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "Low junction temperature 0 " "Low junction temperature operating condition is not set. Assuming a default value of '0'." { } { } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Timing Analyzer" 0 -1 1668462014516 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "DecoderDemo.sdc " "Synopsys Design Constraints File file not found: 'DecoderDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1668462014612 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1668462014612 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1668462014612 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1668462014613 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1668462014613 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1668462014613 ""}
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1668462014613 ""}
{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1668462014615 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1668462014615 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668462014616 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668462014618 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668462014619 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668462014619 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668462014619 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668462014620 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1668462014621 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1668462014633 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1668462014834 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1668462014845 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1668462014845 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1668462014845 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1668462014845 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668462014845 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668462014846 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668462014846 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668462014847 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668462014847 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668462014847 ""}
{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1668462014848 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1668462014882 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1668462014882 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1668462014882 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1668462014882 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668462014883 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668462014883 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668462014884 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668462014884 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668462014884 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1668462015083 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1668462015083 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "463 " "Peak virtual memory: 463 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1668462015091 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 14 21:40:15 2022 " "Processing ended: Mon Nov 14 21:40:15 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1668462015091 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1668462015091 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1668462015091 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1668462015091 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Timing Analyzer" 0 -1 1668462015560 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1668462015560 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 14 21:40:15 2022 " "Processing started: Mon Nov 14 21:40:15 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1668462015560 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1668462015560 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off DecoderDemo -c DecoderDemo " "Command: quartus_eda --read_settings_files=off --write_settings_files=off DecoderDemo -c DecoderDemo" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1668462015560 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1668462015678 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "DecoderDemo.vho /home/tiagorg/repos/DecoderDemo/simulation/modelsim/ simulation " "Generated file DecoderDemo.vho in folder \"/home/tiagorg/repos/DecoderDemo/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1668462015705 ""}
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "600 " "Peak virtual memory: 600 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1668462015714 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 14 21:40:15 2022 " "Processing ended: Mon Nov 14 21:40:15 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1668462015714 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1668462015714 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1668462015714 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1668462015714 ""}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 14 s " "Quartus Prime Full Compilation was successful. 0 errors, 14 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1668462015772 ""}

11
1ano/isd/quartus-projects/DecoderDemo/incremental_db/README Normal file
View File

@ -0,0 +1,11 @@
This folder contains data for incremental compilation.
The compiled_partitions sub-folder contains previous compilation results for each partition.
As long as this folder is preserved, incremental compilation results from earlier compiles
can be re-used. To perform a clean compilation from source files for all partitions, both
the db and incremental_db folder should be removed.
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
As long as this folder is preserved, imported partitions will be automatically re-imported
when the db or incremental_db/compiled_partitions folders are removed.

Some files were not shown because too many files have changed in this diff Show More