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[LSD] added generic version to ALUDemo (pratica05 - part5)

This commit is contained in:
TiagoRG 2023-04-05 14:34:11 +01:00
parent a0f476c3c0
commit 04d4de3354
Signed by untrusted user who does not match committer: TiagoRG
GPG Key ID: DFCD48E3F420DB42
4 changed files with 155 additions and 42 deletions
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90
1ano/2semestre/lsd/pratica03/ALUDemo/ALUDemo.bdf
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@ -20,28 +20,11 @@ refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "graphic" (version "1.4"))
(pin
(input)
(rect 272 144 440 160)
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
(text "SW[7..4]" (rect 5 0 47 11)(font "Arial" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
(annotation_block (location)(rect 208 160 272 176))
)
(pin
(input)
(rect 272 160 440 176)
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
(text "SW[3..0]" (rect 5 0 48 13)(font "Intel Clear" ))
(text "SW[5..0]" (rect 5 0 48 13)(font "Intel Clear" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
@ -54,11 +37,28 @@ https://fpgasoftware.intel.com/eula.
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
(annotation_block (location)(rect 208 176 272 192))
)
(pin
(input)
(rect 272 144 440 160)
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
(text "SW[11..6]" (rect 5 0 54 11)(font "Arial" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
(annotation_block (location)(rect 208 160 272 176))
)
(pin
(input)
(rect 272 176 440 192)
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
(text "SW[10..8]" (rect 5 0 54 11)(font "Arial" ))
(text "SW[14..12]" (rect 5 0 61 11)(font "Arial" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
@ -73,9 +73,9 @@ https://fpgasoftware.intel.com/eula.
)
(pin
(output)
(rect 616 144 792 160)
(rect 624 160 800 176)
(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
(text "LEDR[3..0]" (rect 90 0 144 11)(font "Arial" ))
(text "LEDR[11..6]" (rect 90 0 150 13)(font "Intel Clear" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
@ -86,13 +86,13 @@ https://fpgasoftware.intel.com/eula.
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
(annotation_block (location)(rect 792 160 856 176))
(annotation_block (location)(rect 800 176 856 192))
)
(pin
(output)
(rect 616 160 792 176)
(rect 624 144 800 160)
(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
(text "LEDR[7..4]" (rect 90 0 143 13)(font "Intel Clear" ))
(text "LEDR[5..0]" (rect 90 0 144 11)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
@ -103,24 +103,24 @@ https://fpgasoftware.intel.com/eula.
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
(annotation_block (location)(rect 792 176 848 192))
(annotation_block (location)(rect 800 160 864 176))
)
(symbol
(rect 448 120 608 232)
(text "ALU4" (rect 5 0 34 11)(font "Arial" ))
(rect 448 120 616 232)
(text "ALUN" (rect 5 0 34 11)(font "Arial" ))
(text "inst" (rect 8 96 26 107)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "a[3..0]" (rect 0 0 30 11)(font "Arial" ))
(text "a[3..0]" (rect 21 27 51 38)(font "Arial" ))
(text "a[n-1..0]" (rect 0 0 41 11)(font "Arial" ))
(text "a[n-1..0]" (rect 21 27 62 38)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 3))
)
(port
(pt 0 48)
(input)
(text "b[3..0]" (rect 0 0 30 11)(font "Arial" ))
(text "b[3..0]" (rect 21 43 51 54)(font "Arial" ))
(text "b[n-1..0]" (rect 0 0 41 11)(font "Arial" ))
(text "b[n-1..0]" (rect 21 43 62 54)(font "Arial" ))
(line (pt 0 48)(pt 16 48)(line_width 3))
)
(port
@ -131,22 +131,28 @@ https://fpgasoftware.intel.com/eula.
(line (pt 0 64)(pt 16 64)(line_width 3))
)
(port
(pt 160 32)
(pt 168 32)
(output)
(text "r[3..0]" (rect 0 0 28 11)(font "Arial" ))
(text "r[3..0]" (rect 116 27 144 38)(font "Arial" ))
(line (pt 160 32)(pt 144 32)(line_width 3))
(text "r[n-1..0]" (rect 0 0 38 11)(font "Arial" ))
(text "r[n-1..0]" (rect 115 27 153 38)(font "Arial" ))
(line (pt 168 32)(pt 152 32)(line_width 3))
)
(port
(pt 160 48)
(pt 168 48)
(output)
(text "m[3..0]" (rect 0 0 34 11)(font "Arial" ))
(text "m[3..0]" (rect 111 43 145 54)(font "Arial" ))
(line (pt 160 48)(pt 144 48)(line_width 3))
(text "m[n-1..0]" (rect 0 0 43 11)(font "Arial" ))
(text "m[n-1..0]" (rect 111 43 154 54)(font "Arial" ))
(line (pt 168 48)(pt 152 48)(line_width 3))
)
(parameter
"N"
"6"
""
(type "PARAMETER_SIGNED_DEC") )
(drawing
(rectangle (rect 16 16 144 96))
(rectangle (rect 16 16 152 96))
)
(annotation_block (parameter)(rect 616 88 787 118))
)
(connector
(pt 448 152)
@ -164,12 +170,12 @@ https://fpgasoftware.intel.com/eula.
(bus)
)
(connector
(pt 608 152)
(pt 616 152)
(pt 624 152)
(bus)
)
(connector
(pt 608 168)
(pt 616 168)
(pt 624 168)
(bus)
)

71
1ano/2semestre/lsd/pratica03/ALUDemo/ALUN.bsf Normal file
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@ -0,0 +1,71 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 184 128)
(text "ALUN" (rect 5 0 33 12)(font "Arial" ))
(text "inst" (rect 8 96 20 108)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "a[n-1..0]" (rect 0 0 30 12)(font "Arial" ))
(text "a[n-1..0]" (rect 21 27 51 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 3))
)
(port
(pt 0 48)
(input)
(text "b[n-1..0]" (rect 0 0 30 12)(font "Arial" ))
(text "b[n-1..0]" (rect 21 43 51 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48)(line_width 3))
)
(port
(pt 0 64)
(input)
(text "op[2..0]" (rect 0 0 29 12)(font "Arial" ))
(text "op[2..0]" (rect 21 59 50 71)(font "Arial" ))
(line (pt 0 64)(pt 16 64)(line_width 3))
)
(port
(pt 168 32)
(output)
(text "r[n-1..0]" (rect 0 0 29 12)(font "Arial" ))
(text "r[n-1..0]" (rect 118 27 147 39)(font "Arial" ))
(line (pt 168 32)(pt 152 32)(line_width 3))
)
(port
(pt 168 48)
(output)
(text "m[n-1..0]" (rect 0 0 34 12)(font "Arial" ))
(text "m[n-1..0]" (rect 113 43 147 55)(font "Arial" ))
(line (pt 168 48)(pt 152 48)(line_width 3))
)
(parameter
"N"
"8"
""
(type "PARAMETER_SIGNED_DEC") )
(drawing
(rectangle (rect 16 16 152 96)(line_width 1))
)
(annotation_block (parameter)(rect 184 -64 284 16))
)

36
1ano/2semestre/lsd/pratica03/ALUDemo/ALUN.vhd Normal file
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@ -0,0 +1,36 @@
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity ALUN is
generic (N : positive := 8);
port
(
a,b : in std_logic_vector((N-1) downto 0);
op : in std_logic_vector(2 downto 0);
r, m : out std_logic_vector((N-1) downto 0)
);
end ALUN;
architecture Behavioral of ALUN is
signal s_a, s_b, s_r : unsigned((N-1) downto 0);
signal s_m : unsigned(((N*2)-1) downto 0);
begin
s_a <= unsigned(a);
s_b <= unsigned(b);
s_m <= s_a * s_b;
with op select
s_r <= s_a + s_b when "000",
s_a - s_b when "001",
s_m((N-1) downto 0) when "010",
s_a / s_b when "011",
s_a rem s_b when "100",
s_a and s_b when "101",
s_a or s_b when "110",
s_a xor s_b when "111";
r <= std_logic_vector(s_r);
m <= std_logic_vector(s_m(((N*2)-1) downto N)) when (op = "010") else (others => '0');
end Behavioral;

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1ano/2semestre/lsd/pratica03/ALUDemo/output_files/ALUDemo.sof
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