111 lines
2.9 KiB
Plaintext
111 lines
2.9 KiB
Plaintext
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-- Copyright (C) 2020 Intel Corporation. All rights reserved.
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-- Your use of Intel Corporation's design tools, logic functions
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-- and other software and tools, and any partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Intel Program License
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-- Subscription Agreement, the Intel Quartus Prime License Agreement,
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-- the Intel FPGA IP License Agreement, or other applicable license
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-- agreement, including, without limitation, that your use is for
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-- the sole purpose of programming logic devices manufactured by
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-- Intel and sold by Intel or its authorized distributors. Please
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-- refer to the applicable agreement for further details, at
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-- https://fpgasoftware.intel.com/eula.
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-- *****************************************************************************
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-- This file contains a Vhdl test bench with test vectors .The test vectors
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-- are exported from a vector file in the Quartus Waveform Editor and apply to
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-- the top level entity of the current Quartus project .The user can use this
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-- testbench to simulate his design using a third-party simulation tool .
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-- *****************************************************************************
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-- Generated on "12/02/2022 13:03:34"
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-- Vhdl Test Bench(with test vectors) for design : Teste3
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--
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-- Simulation tool : 3rd Party
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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ENTITY Teste3_vhd_vec_tst IS
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END Teste3_vhd_vec_tst;
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ARCHITECTURE Teste3_arch OF Teste3_vhd_vec_tst IS
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-- constants
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-- signals
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SIGNAL A : STD_LOGIC;
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SIGNAL B : STD_LOGIC;
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SIGNAL C : STD_LOGIC;
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SIGNAL D : STD_LOGIC;
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SIGNAL F : STD_LOGIC;
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COMPONENT Teste3
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PORT (
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A : IN STD_LOGIC;
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B : IN STD_LOGIC;
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C : IN STD_LOGIC;
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D : IN STD_LOGIC;
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F : OUT STD_LOGIC
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);
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END COMPONENT;
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BEGIN
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i1 : Teste3
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PORT MAP (
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-- list connections between master ports and signals
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A => A,
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B => B,
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C => C,
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D => D,
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F => F
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);
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-- A
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t_prcs_A: PROCESS
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BEGIN
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LOOP
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A <= '0';
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WAIT FOR 50000 ps;
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A <= '1';
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WAIT FOR 50000 ps;
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IF (NOW >= 1000000 ps) THEN WAIT; END IF;
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END LOOP;
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END PROCESS t_prcs_A;
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-- B
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t_prcs_B: PROCESS
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BEGIN
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LOOP
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B <= '0';
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WAIT FOR 100000 ps;
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B <= '1';
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WAIT FOR 100000 ps;
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IF (NOW >= 1000000 ps) THEN WAIT; END IF;
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END LOOP;
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END PROCESS t_prcs_B;
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-- C
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t_prcs_C: PROCESS
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BEGIN
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FOR i IN 1 TO 2
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LOOP
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C <= '0';
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WAIT FOR 200000 ps;
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C <= '1';
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WAIT FOR 200000 ps;
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END LOOP;
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C <= '0';
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WAIT;
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END PROCESS t_prcs_C;
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-- D
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t_prcs_D: PROCESS
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BEGIN
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D <= '0';
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WAIT FOR 400000 ps;
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D <= '1';
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WAIT FOR 400000 ps;
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D <= '0';
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WAIT;
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END PROCESS t_prcs_D;
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END Teste3_arch;
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