438 lines
38 KiB
Plaintext
438 lines
38 KiB
Plaintext
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Timing Analyzer report for Teste1
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Fri Dec 2 13:02:27 2022
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Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
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---------------------
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; Table of Contents ;
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---------------------
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1. Legal Notice
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2. Timing Analyzer Summary
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3. Parallel Compilation
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4. Clocks
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5. Slow 1200mV 85C Model Fmax Summary
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6. Timing Closure Recommendations
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7. Slow 1200mV 85C Model Setup Summary
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8. Slow 1200mV 85C Model Hold Summary
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9. Slow 1200mV 85C Model Recovery Summary
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10. Slow 1200mV 85C Model Removal Summary
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11. Slow 1200mV 85C Model Minimum Pulse Width Summary
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12. Slow 1200mV 85C Model Metastability Summary
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13. Slow 1200mV 0C Model Fmax Summary
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14. Slow 1200mV 0C Model Setup Summary
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15. Slow 1200mV 0C Model Hold Summary
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16. Slow 1200mV 0C Model Recovery Summary
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17. Slow 1200mV 0C Model Removal Summary
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18. Slow 1200mV 0C Model Minimum Pulse Width Summary
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19. Slow 1200mV 0C Model Metastability Summary
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20. Fast 1200mV 0C Model Setup Summary
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21. Fast 1200mV 0C Model Hold Summary
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22. Fast 1200mV 0C Model Recovery Summary
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23. Fast 1200mV 0C Model Removal Summary
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24. Fast 1200mV 0C Model Minimum Pulse Width Summary
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25. Fast 1200mV 0C Model Metastability Summary
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26. Multicorner Timing Analysis Summary
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27. Board Trace Model Assignments
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28. Input Transition Times
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29. Signal Integrity Metrics (Slow 1200mv 0c Model)
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30. Signal Integrity Metrics (Slow 1200mv 85c Model)
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31. Signal Integrity Metrics (Fast 1200mv 0c Model)
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32. Clock Transfers
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33. Report TCCS
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34. Report RSKM
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35. Unconstrained Paths Summary
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36. Unconstrained Input Ports
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37. Unconstrained Output Ports
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38. Unconstrained Input Ports
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39. Unconstrained Output Ports
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40. Timing Analyzer Messages
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----------------
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; Legal Notice ;
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----------------
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Copyright (C) 2020 Intel Corporation. All rights reserved.
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Your use of Intel Corporation's design tools, logic functions
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and other software and tools, and any partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Intel Program License
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Subscription Agreement, the Intel Quartus Prime License Agreement,
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the Intel FPGA IP License Agreement, or other applicable license
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agreement, including, without limitation, that your use is for
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the sole purpose of programming logic devices manufactured by
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Intel and sold by Intel or its authorized distributors. Please
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refer to the applicable agreement for further details, at
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https://fpgasoftware.intel.com/eula.
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+-----------------------------------------------------------------------------+
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; Timing Analyzer Summary ;
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+-----------------------+-----------------------------------------------------+
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; Quartus Prime Version ; Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
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; Timing Analyzer ; Legacy Timing Analyzer ;
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; Revision Name ; Teste1 ;
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; Device Family ; Cyclone IV E ;
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; Device Name ; EP4CE6E22C6 ;
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; Timing Models ; Final ;
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; Delay Model ; Combined ;
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; Rise/Fall Delays ; Enabled ;
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+-----------------------+-----------------------------------------------------+
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+------------------------------------------+
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; Parallel Compilation ;
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+----------------------------+-------------+
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; Processors ; Number ;
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+----------------------------+-------------+
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; Number detected on machine ; 8 ;
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; Maximum allowed ; 4 ;
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; ; ;
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; Average used ; 1.01 ;
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; Maximum used ; 4 ;
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; ; ;
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; Usage by Processor ; % Time Used ;
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; Processor 1 ; 100.0% ;
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; Processors 2-4 ; 0.2% ;
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+----------------------------+-------------+
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----------
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; Clocks ;
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----------
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No clocks to report.
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--------------------------------------
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; Slow 1200mV 85C Model Fmax Summary ;
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--------------------------------------
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No paths to report.
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----------------------------------
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; Timing Closure Recommendations ;
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----------------------------------
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HTML report is unavailable in plain text report export.
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---------------------------------------
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; Slow 1200mV 85C Model Setup Summary ;
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---------------------------------------
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No paths to report.
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--------------------------------------
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; Slow 1200mV 85C Model Hold Summary ;
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--------------------------------------
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No paths to report.
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------------------------------------------
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; Slow 1200mV 85C Model Recovery Summary ;
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------------------------------------------
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No paths to report.
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-----------------------------------------
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; Slow 1200mV 85C Model Removal Summary ;
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-----------------------------------------
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No paths to report.
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-----------------------------------------------------
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; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
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-----------------------------------------------------
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No paths to report.
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-----------------------------------------------
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; Slow 1200mV 85C Model Metastability Summary ;
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-----------------------------------------------
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No synchronizer chains to report.
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-------------------------------------
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; Slow 1200mV 0C Model Fmax Summary ;
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-------------------------------------
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No paths to report.
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--------------------------------------
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; Slow 1200mV 0C Model Setup Summary ;
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--------------------------------------
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No paths to report.
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-------------------------------------
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; Slow 1200mV 0C Model Hold Summary ;
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-------------------------------------
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No paths to report.
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-----------------------------------------
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; Slow 1200mV 0C Model Recovery Summary ;
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-----------------------------------------
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No paths to report.
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----------------------------------------
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; Slow 1200mV 0C Model Removal Summary ;
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----------------------------------------
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No paths to report.
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----------------------------------------------------
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; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
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----------------------------------------------------
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No paths to report.
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----------------------------------------------
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; Slow 1200mV 0C Model Metastability Summary ;
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----------------------------------------------
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No synchronizer chains to report.
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--------------------------------------
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; Fast 1200mV 0C Model Setup Summary ;
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--------------------------------------
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No paths to report.
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-------------------------------------
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; Fast 1200mV 0C Model Hold Summary ;
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-------------------------------------
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No paths to report.
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-----------------------------------------
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; Fast 1200mV 0C Model Recovery Summary ;
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-----------------------------------------
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No paths to report.
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----------------------------------------
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; Fast 1200mV 0C Model Removal Summary ;
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----------------------------------------
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No paths to report.
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----------------------------------------------------
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; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
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----------------------------------------------------
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No paths to report.
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----------------------------------------------
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; Fast 1200mV 0C Model Metastability Summary ;
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----------------------------------------------
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No synchronizer chains to report.
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+----------------------------------------------------------------------------+
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; Multicorner Timing Analysis Summary ;
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+------------------+-------+------+----------+---------+---------------------+
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; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
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+------------------+-------+------+----------+---------+---------------------+
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; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; N/A ;
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; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ;
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+------------------+-------+------+----------+---------+---------------------+
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+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Board Trace Model Assignments ;
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+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
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; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
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+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
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; F ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
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; ~ALTERA_DCLK~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
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; ~ALTERA_nCEO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
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+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
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+----------------------------------------------------------------------------+
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; Input Transition Times ;
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+-------------------------+--------------+-----------------+-----------------+
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; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
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+-------------------------+--------------+-----------------+-----------------+
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; C ; 2.5 V ; 2000 ps ; 2000 ps ;
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; B ; 2.5 V ; 2000 ps ; 2000 ps ;
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; D ; 2.5 V ; 2000 ps ; 2000 ps ;
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; A ; 2.5 V ; 2000 ps ; 2000 ps ;
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; ~ALTERA_ASDO_DATA1~ ; 2.5 V ; 2000 ps ; 2000 ps ;
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; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V ; 2000 ps ; 2000 ps ;
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; ~ALTERA_DATA0~ ; 2.5 V ; 2000 ps ; 2000 ps ;
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+-------------------------+--------------+-----------------+-----------------+
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+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Signal Integrity Metrics (Slow 1200mv 0c Model) ;
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+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
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; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
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+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
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; F ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.39 V ; -0.0265 V ; 0.2 V ; 0.033 V ; 2.94e-10 s ; 3.12e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.39 V ; -0.0265 V ; 0.2 V ; 0.033 V ; 2.94e-10 s ; 3.12e-10 s ; Yes ; Yes ;
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; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.45e-09 V ; 2.38 V ; -0.0609 V ; 0.148 V ; 0.095 V ; 2.82e-10 s ; 2.59e-10 s ; Yes ; Yes ; 2.32 V ; 3.45e-09 V ; 2.38 V ; -0.0609 V ; 0.148 V ; 0.095 V ; 2.82e-10 s ; 2.59e-10 s ; Yes ; Yes ;
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; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.61e-09 V ; 2.38 V ; -0.00274 V ; 0.141 V ; 0.006 V ; 4.7e-10 s ; 6.02e-10 s ; Yes ; Yes ; 2.32 V ; 5.61e-09 V ; 2.38 V ; -0.00274 V ; 0.141 V ; 0.006 V ; 4.7e-10 s ; 6.02e-10 s ; Yes ; Yes ;
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+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
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+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Signal Integrity Metrics (Slow 1200mv 85c Model) ;
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+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
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; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
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+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
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; F ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.36 V ; -0.00476 V ; 0.096 V ; 0.013 V ; 4.39e-10 s ; 4.15e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.36 V ; -0.00476 V ; 0.096 V ; 0.013 V ; 4.39e-10 s ; 4.15e-10 s ; Yes ; Yes ;
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; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.74e-07 V ; 2.36 V ; -0.0201 V ; 0.072 V ; 0.033 V ; 4.04e-10 s ; 3.29e-10 s ; Yes ; Yes ; 2.32 V ; 5.74e-07 V ; 2.36 V ; -0.0201 V ; 0.072 V ; 0.033 V ; 4.04e-10 s ; 3.29e-10 s ; Yes ; Yes ;
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; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.45e-07 V ; 2.35 V ; -0.00643 V ; 0.081 V ; 0.031 V ; 5.31e-10 s ; 7.59e-10 s ; Yes ; Yes ; 2.32 V ; 9.45e-07 V ; 2.35 V ; -0.00643 V ; 0.081 V ; 0.031 V ; 5.31e-10 s ; 7.59e-10 s ; Yes ; Yes ;
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+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
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+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Signal Integrity Metrics (Fast 1200mv 0c Model) ;
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+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
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; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
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+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
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; F ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ;
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; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ;
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|
; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ;
|
||
|
|
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
||
|
|
|
||
|
|
|
||
|
|
-------------------
|
||
|
|
; Clock Transfers ;
|
||
|
|
-------------------
|
||
|
|
Nothing to report.
|
||
|
|
|
||
|
|
|
||
|
|
---------------
|
||
|
|
; Report TCCS ;
|
||
|
|
---------------
|
||
|
|
No dedicated SERDES Transmitter circuitry present in device or used in design
|
||
|
|
|
||
|
|
|
||
|
|
---------------
|
||
|
|
; Report RSKM ;
|
||
|
|
---------------
|
||
|
|
No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
|
||
|
|
|
||
|
|
|
||
|
|
+------------------------------------------------+
|
||
|
|
; Unconstrained Paths Summary ;
|
||
|
|
+---------------------------------+-------+------+
|
||
|
|
; Property ; Setup ; Hold ;
|
||
|
|
+---------------------------------+-------+------+
|
||
|
|
; Illegal Clocks ; 0 ; 0 ;
|
||
|
|
; Unconstrained Clocks ; 0 ; 0 ;
|
||
|
|
; Unconstrained Input Ports ; 4 ; 4 ;
|
||
|
|
; Unconstrained Input Port Paths ; 4 ; 4 ;
|
||
|
|
; Unconstrained Output Ports ; 1 ; 1 ;
|
||
|
|
; Unconstrained Output Port Paths ; 4 ; 4 ;
|
||
|
|
+---------------------------------+-------+------+
|
||
|
|
|
||
|
|
|
||
|
|
+---------------------------------------------------------------------------------------------------+
|
||
|
|
; Unconstrained Input Ports ;
|
||
|
|
+------------+--------------------------------------------------------------------------------------+
|
||
|
|
; Input Port ; Comment ;
|
||
|
|
+------------+--------------------------------------------------------------------------------------+
|
||
|
|
; A ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||
|
|
; B ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||
|
|
; C ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||
|
|
; D ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||
|
|
+------------+--------------------------------------------------------------------------------------+
|
||
|
|
|
||
|
|
|
||
|
|
+-----------------------------------------------------------------------------------------------------+
|
||
|
|
; Unconstrained Output Ports ;
|
||
|
|
+-------------+---------------------------------------------------------------------------------------+
|
||
|
|
; Output Port ; Comment ;
|
||
|
|
+-------------+---------------------------------------------------------------------------------------+
|
||
|
|
; F ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||
|
|
+-------------+---------------------------------------------------------------------------------------+
|
||
|
|
|
||
|
|
|
||
|
|
+---------------------------------------------------------------------------------------------------+
|
||
|
|
; Unconstrained Input Ports ;
|
||
|
|
+------------+--------------------------------------------------------------------------------------+
|
||
|
|
; Input Port ; Comment ;
|
||
|
|
+------------+--------------------------------------------------------------------------------------+
|
||
|
|
; A ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||
|
|
; B ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||
|
|
; C ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||
|
|
; D ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||
|
|
+------------+--------------------------------------------------------------------------------------+
|
||
|
|
|
||
|
|
|
||
|
|
+-----------------------------------------------------------------------------------------------------+
|
||
|
|
; Unconstrained Output Ports ;
|
||
|
|
+-------------+---------------------------------------------------------------------------------------+
|
||
|
|
; Output Port ; Comment ;
|
||
|
|
+-------------+---------------------------------------------------------------------------------------+
|
||
|
|
; F ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||
|
|
+-------------+---------------------------------------------------------------------------------------+
|
||
|
|
|
||
|
|
|
||
|
|
+--------------------------+
|
||
|
|
; Timing Analyzer Messages ;
|
||
|
|
+--------------------------+
|
||
|
|
Info: *******************************************************************
|
||
|
|
Info: Running Quartus Prime Timing Analyzer
|
||
|
|
Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
||
|
|
Info: Processing started: Fri Dec 2 13:02:26 2022
|
||
|
|
Info: Command: quartus_sta Teste1 -c Teste1
|
||
|
|
Info: qsta_default_script.tcl version: #1
|
||
|
|
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
||
|
|
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
|
||
|
|
Info (21076): High junction temperature operating condition is not set. Assuming a default value of '85'.
|
||
|
|
Info (21076): Low junction temperature operating condition is not set. Assuming a default value of '0'.
|
||
|
|
Critical Warning (332012): Synopsys Design Constraints File file not found: 'Teste1.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
|
||
|
|
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
|
||
|
|
Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
|
||
|
|
Warning (332068): No clocks defined in design.
|
||
|
|
Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
|
||
|
|
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
|
||
|
|
Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
|
||
|
|
Info (332159): No clocks to report
|
||
|
|
Info: Analyzing Slow 1200mV 85C Model
|
||
|
|
Info (332140): No fmax paths to report
|
||
|
|
Info (332140): No Setup paths to report
|
||
|
|
Info (332140): No Hold paths to report
|
||
|
|
Info (332140): No Recovery paths to report
|
||
|
|
Info (332140): No Removal paths to report
|
||
|
|
Info (332140): No Minimum Pulse Width paths to report
|
||
|
|
Info: Analyzing Slow 1200mV 0C Model
|
||
|
|
Info (334003): Started post-fitting delay annotation
|
||
|
|
Info (334004): Delay annotation completed successfully
|
||
|
|
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
|
||
|
|
Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
|
||
|
|
Warning (332068): No clocks defined in design.
|
||
|
|
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
|
||
|
|
Info (332140): No fmax paths to report
|
||
|
|
Info (332140): No Setup paths to report
|
||
|
|
Info (332140): No Hold paths to report
|
||
|
|
Info (332140): No Recovery paths to report
|
||
|
|
Info (332140): No Removal paths to report
|
||
|
|
Info (332140): No Minimum Pulse Width paths to report
|
||
|
|
Info: Analyzing Fast 1200mV 0C Model
|
||
|
|
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
|
||
|
|
Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed.
|
||
|
|
Warning (332068): No clocks defined in design.
|
||
|
|
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
|
||
|
|
Info (332140): No Setup paths to report
|
||
|
|
Info (332140): No Hold paths to report
|
||
|
|
Info (332140): No Recovery paths to report
|
||
|
|
Info (332140): No Removal paths to report
|
||
|
|
Info (332140): No Minimum Pulse Width paths to report
|
||
|
|
Info (332102): Design is not fully constrained for setup requirements
|
||
|
|
Info (332102): Design is not fully constrained for hold requirements
|
||
|
|
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings
|
||
|
|
Info: Peak virtual memory: 465 megabytes
|
||
|
|
Info: Processing ended: Fri Dec 2 13:02:27 2022
|
||
|
|
Info: Elapsed time: 00:00:01
|
||
|
|
Info: Total CPU time (on all processors): 00:00:01
|
||
|
|
|
||
|
|
|