329 lines
8.3 KiB
Plaintext
329 lines
8.3 KiB
Plaintext
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-- Copyright (C) 2020 Intel Corporation. All rights reserved.
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-- Your use of Intel Corporation's design tools, logic functions
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-- and other software and tools, and any partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Intel Program License
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-- Subscription Agreement, the Intel Quartus Prime License Agreement,
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-- the Intel FPGA IP License Agreement, or other applicable license
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-- agreement, including, without limitation, that your use is for
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-- the sole purpose of programming logic devices manufactured by
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-- Intel and sold by Intel or its authorized distributors. Please
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-- refer to the applicable agreement for further details, at
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-- https://fpgasoftware.intel.com/eula.
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-- VENDOR "Altera"
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-- PROGRAM "Quartus Prime"
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-- VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
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-- DATE "11/14/2022 21:56:51"
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--
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-- Device: Altera EP4CE6E22C6 Package TQFP144
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--
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--
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-- This VHDL file should be used for ModelSim-Altera (VHDL) only
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--
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LIBRARY CYCLONEIVE;
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LIBRARY IEEE;
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USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
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USE IEEE.STD_LOGIC_1164.ALL;
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ENTITY hard_block IS
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PORT (
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devoe : IN std_logic;
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devclrn : IN std_logic;
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devpor : IN std_logic
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);
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END hard_block;
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-- Design Ports Information
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-- ~ALTERA_ASDO_DATA1~ => Location: PIN_6, I/O Standard: 2.5 V, Current Strength: Default
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-- ~ALTERA_FLASH_nCE_nCSO~ => Location: PIN_8, I/O Standard: 2.5 V, Current Strength: Default
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-- ~ALTERA_DCLK~ => Location: PIN_12, I/O Standard: 2.5 V, Current Strength: Default
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-- ~ALTERA_DATA0~ => Location: PIN_13, I/O Standard: 2.5 V, Current Strength: Default
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-- ~ALTERA_nCEO~ => Location: PIN_101, I/O Standard: 2.5 V, Current Strength: 8mA
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ARCHITECTURE structure OF hard_block IS
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SIGNAL gnd : std_logic := '0';
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SIGNAL vcc : std_logic := '1';
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SIGNAL unknown : std_logic := 'X';
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SIGNAL ww_devoe : std_logic;
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SIGNAL ww_devclrn : std_logic;
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SIGNAL ww_devpor : std_logic;
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SIGNAL \~ALTERA_ASDO_DATA1~~padout\ : std_logic;
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SIGNAL \~ALTERA_FLASH_nCE_nCSO~~padout\ : std_logic;
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SIGNAL \~ALTERA_DATA0~~padout\ : std_logic;
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SIGNAL \~ALTERA_ASDO_DATA1~~ibuf_o\ : std_logic;
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SIGNAL \~ALTERA_FLASH_nCE_nCSO~~ibuf_o\ : std_logic;
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SIGNAL \~ALTERA_DATA0~~ibuf_o\ : std_logic;
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BEGIN
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ww_devoe <= devoe;
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ww_devclrn <= devclrn;
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ww_devpor <= devpor;
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END structure;
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LIBRARY CYCLONEIVE;
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LIBRARY IEEE;
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USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
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USE IEEE.STD_LOGIC_1164.ALL;
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ENTITY Dec2_4 IS
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PORT (
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Y3 : OUT std_logic;
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E0L : IN std_logic;
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E1 : IN std_logic;
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X1 : IN std_logic;
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X0 : IN std_logic;
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Y2 : OUT std_logic;
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Y1 : OUT std_logic;
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Y0 : OUT std_logic
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);
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END Dec2_4;
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-- Design Ports Information
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-- Y3 => Location: PIN_33, I/O Standard: 2.5 V, Current Strength: Default
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-- Y2 => Location: PIN_32, I/O Standard: 2.5 V, Current Strength: Default
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-- Y1 => Location: PIN_28, I/O Standard: 2.5 V, Current Strength: Default
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-- Y0 => Location: PIN_34, I/O Standard: 2.5 V, Current Strength: Default
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-- E1 => Location: PIN_24, I/O Standard: 2.5 V, Current Strength: Default
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-- X0 => Location: PIN_25, I/O Standard: 2.5 V, Current Strength: Default
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-- X1 => Location: PIN_31, I/O Standard: 2.5 V, Current Strength: Default
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-- E0L => Location: PIN_30, I/O Standard: 2.5 V, Current Strength: Default
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ARCHITECTURE structure OF Dec2_4 IS
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SIGNAL gnd : std_logic := '0';
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SIGNAL vcc : std_logic := '1';
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SIGNAL unknown : std_logic := 'X';
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SIGNAL devoe : std_logic := '1';
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SIGNAL devclrn : std_logic := '1';
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SIGNAL devpor : std_logic := '1';
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SIGNAL ww_devoe : std_logic;
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SIGNAL ww_devclrn : std_logic;
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SIGNAL ww_devpor : std_logic;
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SIGNAL ww_Y3 : std_logic;
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SIGNAL ww_E0L : std_logic;
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SIGNAL ww_E1 : std_logic;
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SIGNAL ww_X1 : std_logic;
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SIGNAL ww_X0 : std_logic;
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SIGNAL ww_Y2 : std_logic;
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SIGNAL ww_Y1 : std_logic;
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SIGNAL ww_Y0 : std_logic;
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SIGNAL \Y3~output_o\ : std_logic;
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SIGNAL \Y2~output_o\ : std_logic;
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SIGNAL \Y1~output_o\ : std_logic;
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SIGNAL \Y0~output_o\ : std_logic;
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SIGNAL \E1~input_o\ : std_logic;
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SIGNAL \X1~input_o\ : std_logic;
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SIGNAL \X0~input_o\ : std_logic;
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SIGNAL \E0L~input_o\ : std_logic;
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SIGNAL \inst~combout\ : std_logic;
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SIGNAL \inst1~combout\ : std_logic;
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SIGNAL \inst3~combout\ : std_logic;
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SIGNAL \inst2~combout\ : std_logic;
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COMPONENT hard_block
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PORT (
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devoe : IN std_logic;
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devclrn : IN std_logic;
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devpor : IN std_logic);
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END COMPONENT;
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BEGIN
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Y3 <= ww_Y3;
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ww_E0L <= E0L;
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ww_E1 <= E1;
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ww_X1 <= X1;
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ww_X0 <= X0;
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Y2 <= ww_Y2;
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Y1 <= ww_Y1;
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Y0 <= ww_Y0;
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ww_devoe <= devoe;
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ww_devclrn <= devclrn;
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ww_devpor <= devpor;
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auto_generated_inst : hard_block
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PORT MAP (
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devoe => ww_devoe,
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devclrn => ww_devclrn,
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devpor => ww_devpor);
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-- Location: IOOBUF_X0_Y6_N23
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\Y3~output\ : cycloneive_io_obuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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open_drain_output => "false")
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-- pragma translate_on
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PORT MAP (
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i => \inst~combout\,
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devoe => ww_devoe,
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o => \Y3~output_o\);
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-- Location: IOOBUF_X0_Y6_N16
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\Y2~output\ : cycloneive_io_obuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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open_drain_output => "false")
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-- pragma translate_on
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PORT MAP (
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i => \inst1~combout\,
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devoe => ww_devoe,
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o => \Y2~output_o\);
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-- Location: IOOBUF_X0_Y9_N9
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\Y1~output\ : cycloneive_io_obuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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open_drain_output => "false")
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-- pragma translate_on
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PORT MAP (
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i => \inst3~combout\,
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devoe => ww_devoe,
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o => \Y1~output_o\);
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-- Location: IOOBUF_X0_Y5_N16
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\Y0~output\ : cycloneive_io_obuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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open_drain_output => "false")
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-- pragma translate_on
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PORT MAP (
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i => \inst2~combout\,
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devoe => ww_devoe,
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o => \Y0~output_o\);
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-- Location: IOIBUF_X0_Y11_N15
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\E1~input\ : cycloneive_io_ibuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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simulate_z_as => "z")
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-- pragma translate_on
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PORT MAP (
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i => ww_E1,
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o => \E1~input_o\);
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-- Location: IOIBUF_X0_Y7_N1
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\X1~input\ : cycloneive_io_ibuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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simulate_z_as => "z")
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-- pragma translate_on
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PORT MAP (
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i => ww_X1,
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o => \X1~input_o\);
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-- Location: IOIBUF_X0_Y11_N22
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\X0~input\ : cycloneive_io_ibuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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simulate_z_as => "z")
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-- pragma translate_on
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PORT MAP (
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i => ww_X0,
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o => \X0~input_o\);
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-- Location: IOIBUF_X0_Y8_N15
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\E0L~input\ : cycloneive_io_ibuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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simulate_z_as => "z")
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-- pragma translate_on
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PORT MAP (
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i => ww_E0L,
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o => \E0L~input_o\);
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-- Location: LCCOMB_X6_Y9_N8
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inst : cycloneive_lcell_comb
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-- Equation(s):
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-- \inst~combout\ = (\E1~input_o\ & (!\X1~input_o\ & (!\X0~input_o\ & !\E0L~input_o\)))
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-- pragma translate_off
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GENERIC MAP (
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lut_mask => "0000000000000010",
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sum_lutc_input => "datac")
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-- pragma translate_on
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PORT MAP (
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dataa => \E1~input_o\,
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datab => \X1~input_o\,
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datac => \X0~input_o\,
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datad => \E0L~input_o\,
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combout => \inst~combout\);
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-- Location: LCCOMB_X6_Y9_N2
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inst1 : cycloneive_lcell_comb
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-- Equation(s):
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-- \inst1~combout\ = (\E1~input_o\ & (!\X1~input_o\ & (\X0~input_o\ & !\E0L~input_o\)))
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-- pragma translate_off
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GENERIC MAP (
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lut_mask => "0000000000100000",
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sum_lutc_input => "datac")
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-- pragma translate_on
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PORT MAP (
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dataa => \E1~input_o\,
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datab => \X1~input_o\,
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datac => \X0~input_o\,
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datad => \E0L~input_o\,
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combout => \inst1~combout\);
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-- Location: LCCOMB_X6_Y9_N28
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inst3 : cycloneive_lcell_comb
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-- Equation(s):
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-- \inst3~combout\ = (\E1~input_o\ & (\X1~input_o\ & (\X0~input_o\ & !\E0L~input_o\)))
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-- pragma translate_off
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GENERIC MAP (
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lut_mask => "0000000010000000",
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sum_lutc_input => "datac")
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-- pragma translate_on
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PORT MAP (
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dataa => \E1~input_o\,
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datab => \X1~input_o\,
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datac => \X0~input_o\,
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datad => \E0L~input_o\,
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combout => \inst3~combout\);
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-- Location: LCCOMB_X6_Y9_N30
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inst2 : cycloneive_lcell_comb
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-- Equation(s):
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-- \inst2~combout\ = (\E1~input_o\ & (\X1~input_o\ & (!\X0~input_o\ & !\E0L~input_o\)))
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-- pragma translate_off
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GENERIC MAP (
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lut_mask => "0000000000001000",
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sum_lutc_input => "datac")
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-- pragma translate_on
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PORT MAP (
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dataa => \E1~input_o\,
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datab => \X1~input_o\,
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datac => \X0~input_o\,
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datad => \E0L~input_o\,
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combout => \inst2~combout\);
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ww_Y3 <= \Y3~output_o\;
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ww_Y2 <= \Y2~output_o\;
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ww_Y1 <= \Y1~output_o\;
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ww_Y0 <= \Y0~output_o\;
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END structure;
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