uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/modelsim/CounterDemo_modelsim.xrf

vendor_name = ModelSim
source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/CounterUpDown4.vhd
source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDown4.vhd
source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDown4.vwf
source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDemo.bdf
source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/Bin7SegDecoder.vhd
source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/FreqDivider.vhd
source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_b.vhd
source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_p.vhd
source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_b.vhd
source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_p.vhd
source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.cbx.xml
design_name = hard_block
design_name = CounterDemo
instance = comp, \HEX0[6]~output\, HEX0[6]~output, CounterDemo, 1
instance = comp, \HEX0[5]~output\, HEX0[5]~output, CounterDemo, 1
instance = comp, \HEX0[4]~output\, HEX0[4]~output, CounterDemo, 1
instance = comp, \HEX0[3]~output\, HEX0[3]~output, CounterDemo, 1
instance = comp, \HEX0[2]~output\, HEX0[2]~output, CounterDemo, 1
instance = comp, \HEX0[1]~output\, HEX0[1]~output, CounterDemo, 1
instance = comp, \HEX0[0]~output\, HEX0[0]~output, CounterDemo, 1
instance = comp, \CLOCK_50~input\, CLOCK_50~input, CounterDemo, 1
instance = comp, \CLOCK_50~inputclkctrl\, CLOCK_50~inputclkctrl, CounterDemo, 1
instance = comp, \inst1|Add2~0\, inst1|Add2~0, CounterDemo, 1
instance = comp, \inst1|s_counter[0]\, inst1|s_counter[0], CounterDemo, 1
instance = comp, \inst1|Add2~2\, inst1|Add2~2, CounterDemo, 1
instance = comp, \inst1|s_counter[1]\, inst1|s_counter[1], CounterDemo, 1
instance = comp, \inst1|Add2~4\, inst1|Add2~4, CounterDemo, 1
instance = comp, \inst1|s_counter[2]\, inst1|s_counter[2], CounterDemo, 1
instance = comp, \inst1|Add2~6\, inst1|Add2~6, CounterDemo, 1
instance = comp, \inst1|s_counter[3]\, inst1|s_counter[3], CounterDemo, 1
instance = comp, \inst1|Add2~8\, inst1|Add2~8, CounterDemo, 1
instance = comp, \inst1|s_counter[4]\, inst1|s_counter[4], CounterDemo, 1
instance = comp, \inst1|Add2~10\, inst1|Add2~10, CounterDemo, 1
instance = comp, \inst1|s_counter[5]\, inst1|s_counter[5], CounterDemo, 1
instance = comp, \inst1|Equal0~6\, inst1|Equal0~6, CounterDemo, 1
instance = comp, \inst1|Add2~46\, inst1|Add2~46, CounterDemo, 1
instance = comp, \inst1|Add2~48\, inst1|Add2~48, CounterDemo, 1
instance = comp, \inst1|s_counter~0\, inst1|s_counter~0, CounterDemo, 1
instance = comp, \inst1|s_counter[24]\, inst1|s_counter[24], CounterDemo, 1
instance = comp, \inst1|Add2~12\, inst1|Add2~12, CounterDemo, 1
instance = comp, \inst1|s_counter~11\, inst1|s_counter~11, CounterDemo, 1
instance = comp, \inst1|s_counter[6]\, inst1|s_counter[6], CounterDemo, 1
instance = comp, \inst1|Add2~14\, inst1|Add2~14, CounterDemo, 1
instance = comp, \inst1|s_counter[7]\, inst1|s_counter[7], CounterDemo, 1
instance = comp, \inst1|Add2~16\, inst1|Add2~16, CounterDemo, 1
instance = comp, \inst1|s_counter[8]\, inst1|s_counter[8], CounterDemo, 1
instance = comp, \inst1|Add2~18\, inst1|Add2~18, CounterDemo, 1
instance = comp, \inst1|s_counter[9]\, inst1|s_counter[9], CounterDemo, 1
instance = comp, \inst1|Add2~20\, inst1|Add2~20, CounterDemo, 1
instance = comp, \inst1|s_counter[10]\, inst1|s_counter[10], CounterDemo, 1
instance = comp, \inst1|Add2~22\, inst1|Add2~22, CounterDemo, 1
instance = comp, \inst1|s_counter~10\, inst1|s_counter~10, CounterDemo, 1
instance = comp, \inst1|s_counter[11]\, inst1|s_counter[11], CounterDemo, 1
instance = comp, \inst1|Add2~24\, inst1|Add2~24, CounterDemo, 1
instance = comp, \inst1|s_counter~9\, inst1|s_counter~9, CounterDemo, 1
instance = comp, \inst1|s_counter[12]\, inst1|s_counter[12], CounterDemo, 1
instance = comp, \inst1|Add2~26\, inst1|Add2~26, CounterDemo, 1
instance = comp, \inst1|s_counter~8\, inst1|s_counter~8, CounterDemo, 1
instance = comp, \inst1|s_counter[13]\, inst1|s_counter[13], CounterDemo, 1
instance = comp, \inst1|Add2~28\, inst1|Add2~28, CounterDemo, 1
instance = comp, \inst1|s_counter~3\, inst1|s_counter~3, CounterDemo, 1
instance = comp, \inst1|s_counter[14]\, inst1|s_counter[14], CounterDemo, 1
instance = comp, \inst1|Add2~30\, inst1|Add2~30, CounterDemo, 1
instance = comp, \inst1|s_counter[15]\, inst1|s_counter[15], CounterDemo, 1
instance = comp, \inst1|Add2~32\, inst1|Add2~32, CounterDemo, 1
instance = comp, \inst1|s_counter~2\, inst1|s_counter~2, CounterDemo, 1
instance = comp, \inst1|s_counter[16]\, inst1|s_counter[16], CounterDemo, 1
instance = comp, \inst1|Add2~34\, inst1|Add2~34, CounterDemo, 1
instance = comp, \inst1|s_counter[17]\, inst1|s_counter[17], CounterDemo, 1
instance = comp, \inst1|Equal0~8\, inst1|Equal0~8, CounterDemo, 1
instance = comp, \inst1|Equal0~9\, inst1|Equal0~9, CounterDemo, 1
instance = comp, \inst1|Equal0~10\, inst1|Equal0~10, CounterDemo, 1
instance = comp, \inst1|Equal0~5\, inst1|Equal0~5, CounterDemo, 1
instance = comp, \inst1|Equal0~3\, inst1|Equal0~3, CounterDemo, 1
instance = comp, \inst1|Add2~36\, inst1|Add2~36, CounterDemo, 1
instance = comp, \inst1|s_counter~7\, inst1|s_counter~7, CounterDemo, 1
instance = comp, \inst1|s_counter[18]\, inst1|s_counter[18], CounterDemo, 1
instance = comp, \inst1|Add2~38\, inst1|Add2~38, CounterDemo, 1
instance = comp, \inst1|s_counter~6\, inst1|s_counter~6, CounterDemo, 1
instance = comp, \inst1|s_counter[19]\, inst1|s_counter[19], CounterDemo, 1
instance = comp, \inst1|Add2~40\, inst1|Add2~40, CounterDemo, 1
instance = comp, \inst1|s_counter~5\, inst1|s_counter~5, CounterDemo, 1
instance = comp, \inst1|s_counter[20]\, inst1|s_counter[20], CounterDemo, 1
instance = comp, \inst1|Equal0~2\, inst1|Equal0~2, CounterDemo, 1
instance = comp, \inst1|Add2~42\, inst1|Add2~42, CounterDemo, 1
instance = comp, \inst1|s_counter~4\, inst1|s_counter~4, CounterDemo, 1
instance = comp, \inst1|s_counter[21]\, inst1|s_counter[21], CounterDemo, 1
instance = comp, \inst1|Add2~50\, inst1|Add2~50, CounterDemo, 1
instance = comp, \inst1|s_counter[25]\, inst1|s_counter[25], CounterDemo, 1
instance = comp, \inst1|Add2~52\, inst1|Add2~52, CounterDemo, 1
instance = comp, \inst1|s_counter[26]\, inst1|s_counter[26], CounterDemo, 1
instance = comp, \inst1|Add2~54\, inst1|Add2~54, CounterDemo, 1
instance = comp, \inst1|s_counter[27]\, inst1|s_counter[27], CounterDemo, 1
instance = comp, \inst1|Equal0~1\, inst1|Equal0~1, CounterDemo, 1
instance = comp, \inst1|Add2~56\, inst1|Add2~56, CounterDemo, 1
instance = comp, \inst1|s_counter[28]\, inst1|s_counter[28], CounterDemo, 1
instance = comp, \inst1|Add2~58\, inst1|Add2~58, CounterDemo, 1
instance = comp, \inst1|s_counter[29]\, inst1|s_counter[29], CounterDemo, 1
instance = comp, \inst1|Add2~60\, inst1|Add2~60, CounterDemo, 1
instance = comp, \inst1|s_counter[30]\, inst1|s_counter[30], CounterDemo, 1
instance = comp, \inst1|Add2~62\, inst1|Add2~62, CounterDemo, 1
instance = comp, \inst1|s_counter[31]\, inst1|s_counter[31], CounterDemo, 1
instance = comp, \inst1|Equal0~0\, inst1|Equal0~0, CounterDemo, 1
instance = comp, \inst1|Equal0~4\, inst1|Equal0~4, CounterDemo, 1
instance = comp, \inst1|Equal0~11\, inst1|Equal0~11, CounterDemo, 1
instance = comp, \inst1|Add2~44\, inst1|Add2~44, CounterDemo, 1
instance = comp, \inst1|s_counter~1\, inst1|s_counter~1, CounterDemo, 1
instance = comp, \inst1|s_counter[22]\, inst1|s_counter[22], CounterDemo, 1
instance = comp, \inst1|s_counter[23]\, inst1|s_counter[23], CounterDemo, 1
instance = comp, \inst1|clkOut~0\, inst1|clkOut~0, CounterDemo, 1
instance = comp, \inst1|clkOut~1\, inst1|clkOut~1, CounterDemo, 1
instance = comp, \inst1|clkOut~2\, inst1|clkOut~2, CounterDemo, 1
instance = comp, \inst1|Equal0~7\, inst1|Equal0~7, CounterDemo, 1
instance = comp, \inst1|clkOut~3\, inst1|clkOut~3, CounterDemo, 1
instance = comp, \inst1|clkOut~feeder\, inst1|clkOut~feeder, CounterDemo, 1
instance = comp, \inst1|clkOut\, inst1|clkOut, CounterDemo, 1
instance = comp, \inst1|clkOut~clkctrl\, inst1|clkOut~clkctrl, CounterDemo, 1
instance = comp, \SW[0]~input\, SW[0]~input, CounterDemo, 1
instance = comp, \inst|s_count[0]~11\, inst|s_count[0]~11, CounterDemo, 1
instance = comp, \KEY[1]~input\, KEY[1]~input, CounterDemo, 1
instance = comp, \inst|s_count[0]\, inst|s_count[0], CounterDemo, 1
instance = comp, \inst|s_count[1]~4\, inst|s_count[1]~4, CounterDemo, 1
instance = comp, \inst|s_count[1]~5\, inst|s_count[1]~5, CounterDemo, 1
instance = comp, \inst|s_count[1]\, inst|s_count[1], CounterDemo, 1
instance = comp, \inst|s_count[2]~7\, inst|s_count[2]~7, CounterDemo, 1
instance = comp, \inst|s_count[2]\, inst|s_count[2], CounterDemo, 1
instance = comp, \inst|s_count[3]~9\, inst|s_count[3]~9, CounterDemo, 1
instance = comp, \inst|s_count[3]\, inst|s_count[3], CounterDemo, 1
instance = comp, \hex|decOut_n[6]~0\, hex|decOut_n[6]~0, CounterDemo, 1
instance = comp, \hex|decOut_n[5]~1\, hex|decOut_n[5]~1, CounterDemo, 1
instance = comp, \hex|decOut_n[4]~2\, hex|decOut_n[4]~2, CounterDemo, 1
instance = comp, \hex|decOut_n[3]~3\, hex|decOut_n[3]~3, CounterDemo, 1
instance = comp, \hex|decOut_n[2]~4\, hex|decOut_n[2]~4, CounterDemo, 1
instance = comp, \hex|decOut_n[1]~5\, hex|decOut_n[1]~5, CounterDemo, 1
instance = comp, \hex|decOut_n[0]~6\, hex|decOut_n[0]~6, CounterDemo, 1