14 lines
267 B
Plaintext
14 lines
267 B
Plaintext
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|GateDemo
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SW[0] => and2gate:system_core.inPort0
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SW[1] => and2gate:system_core.inPort1
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LEDR[0] <= and2gate:system_core.outPort
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LEDR[1] <= <GND>
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|GateDemo|AND2Gate:system_core
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inPort0 => outPort.IN0
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inPort1 => outPort.IN1
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outPort <= outPort.DB_MAX_OUTPUT_PORT_TYPE
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