20 lines
375 B
VHDL
20 lines
375 B
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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entity Dec2_4EnDemo is
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port
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(
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SW : in std_logic_vector(2 downto 0);
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LEDR : out std_logic_vector(3 downto 0)
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);
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end Dec2_4EnDemo;
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architecture Shell of Dec2_4EnDemo is
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begin
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system_core : entity work.Dec2_4En(BehavProc)
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port map(
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enable => SW(2),
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inputs => SW(1 downto 0),
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outputs => LEDR(3 downto 0)
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);
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end Shell;
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