65 lines
1.5 KiB
VHDL
65 lines
1.5 KiB
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.NUMERIC_STD.all;
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entity DebounceUnit is
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generic(kHzClkFreq : positive := 50000;
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mSecMinInWidth : positive := 100;
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inPolarity : std_logic := '1';
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outPolarity : std_logic := '1');
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port(refClk : in std_logic;
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dirtyIn : in std_logic;
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pulsedOut : out std_logic);
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end DebounceUnit;
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architecture Behavioral of DebounceUnit is
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constant MIN_IN_WIDTH_CYCLES : positive := mSecMinInWidth * kHzClkFreq;
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subtype TCounter is natural range 0 to MIN_IN_WIDTH_CYCLES;
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signal s_debounceCnt : TCounter := 0;
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signal s_dirtyIn, s_previousIn, s_pulsedOut : std_logic;
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begin
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in_sync_proc : process(refClk)
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begin
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if (rising_edge(refClk)) then
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if (inPolarity = '1') then
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s_dirtyIn <= dirtyIn;
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else
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s_dirtyIn <= not dirtyIn;
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end if;
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s_previousIn <= s_dirtyIn;
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end if;
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end process;
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count_proc : process(refClk)
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begin
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if (rising_edge(refClk)) then
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if ((s_dirtyIn = '0') or
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(s_debounceCnt > MIN_IN_WIDTH_CYCLES)) then
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s_debounceCnt <= 0;
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s_pulsedOut <= '0';
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elsif (s_dirtyIn = '1') then
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if (s_previousIn = '0') then
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s_debounceCnt <= MIN_IN_WIDTH_CYCLES;
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s_pulsedOut <= '0';
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else
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if (s_debounceCnt >= 1) then
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s_debounceCnt <= s_debounceCnt - 1;
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end if;
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if (s_debounceCnt = 1) then
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s_pulsedOut <= '1';
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else
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s_pulsedOut <= '0';
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end if;
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end if;
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end if;
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end if;
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end process;
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pulsedOut <= s_pulsedOut when (outPolarity = '1') else
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not s_pulsedOut;
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end Behavioral;
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