17 lines
359 B
VHDL
17 lines
359 B
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_UNSIGNED.all;
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entity AdderN is
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generic ( N : positive )
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port
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(
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operand1, operand2 : in std_logic_vector((N-1) downto 0 );
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result : out std_logic_vector( N downto 0 )
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);
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end AdderN;
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architecture Behavioral of AdderN is
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begin
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result <= operand1 + operand2;
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end Behavioral;
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