34 lines
700 B
VHDL
34 lines
700 B
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.NUMERIC_STD.all;
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entity FreqDivider is
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generic(divFactor : positive := 10);
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port
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(
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clkIn : in std_logic;
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clkOut : out std_logic
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);
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end FreqDivider;
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architecture Behavioral of FreqDivider is
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subtype TCounter is natural range 0 to divFactor - 1;
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signal s_divCounter : TCounter := 0;
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begin
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assert(divFactor >= 2);
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process(clkIn)
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begin
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if (rising_edge(clkIn)) then
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if (s_divCounter >= (divFactor - 1)) then
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clkOut <= '0';
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s_divCounter <= 0;
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else
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if (s_divCounter = (divFactor / 2 - 1)) then
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clkOut <= '1';
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end if;
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s_divCounter <= s_divCounter + 1;
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end if;
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end if;
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end process;
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end Behavioral;
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