36 lines
1011 B
VHDL
36 lines
1011 B
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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entity Bin7SegDecoder is
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port(enable : in std_logic;
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binInput : in std_logic_vector(3 downto 0);
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decOut_n : out std_logic_vector(6 downto 0));
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end Bin7SegDecoder;
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architecture RTL of Bin7SegDecoder is
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signal s_decOut_n : std_logic_vector(6 downto 0);
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begin
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with binInput select
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s_decOut_n <= "1111001" when "0001", --1
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"0100100" when "0010", --2
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"0110000" when "0011", --3
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"0011001" when "0100", --4
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"0010010" when "0101", --5
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"0000010" when "0110", --6
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"1111000" when "0111", --7
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"0000000" when "1000", --8
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"0010000" when "1001", --9
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"0001000" when "1010", --A
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"0000011" when "1011", --b
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"1000110" when "1100", --C
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"0100001" when "1101", --d
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"0000110" when "1110", --E
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"0001110" when "1111", --F
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"1000000" when others; --0
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decOut_n <= s_decOut_n when (enable = '1') else
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"0111111";
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end RTL;
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