28 lines
603 B
VHDL
28 lines
603 B
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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entity DisplayDemoVHDL is
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port
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(
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SW : in std_logic_vector(3 downto 0);
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KEY : in std_logic_vector(1 downto 0);
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LEDG : out std_logic_vector(3 downto 0);
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LEDR : out std_logic_vector(6 downto 0);
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HEX0 : out std_logic_vector(6 downto 0)
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);
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end DisplayDemoVHDL;
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architecture Shell of DisplayDemoVHDL is
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signal s_decOut : std_logic_vector(6 downto 0);
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begin
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system_core : entity work.Bin7SegDecoder(Behavioral)
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port map
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(
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binInput => SW,
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enable => KEY(0),
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decOut_n => s_decOut
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);
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HEX0 <= s_decOut;
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LEDR <= s_decOut;
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LEDG <= SW;
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end Shell;
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