26 lines
532 B
VHDL
26 lines
532 B
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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entity LogicUnit is
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port
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(
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input0 : in std_logic;
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input1 : in std_logic;
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invOut : out std_logic;
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andOut : out std_logic;
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orOut : out std_logic;
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xorOut : out std_logic;
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nandOut : out std_logic;
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norOut : out std_logic
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);
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end LogicUnit;
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architecture Behavioral of LogicUnit is
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begin
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invOut <= not input0;
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andOut <= input0 and input1;
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orOut <= input0 or input1;
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xorOut <= input0 xor input1;
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nandOut <= input0 nand input1;
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norOut <= input0 nor input1;
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end Behavioral;
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