21 lines
11 KiB
Plaintext
21 lines
11 KiB
Plaintext
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1679318115039 ""}
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{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1679318115039 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 20 13:15:14 2023 " "Processing started: Mon Mar 20 13:15:14 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1679318115039 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679318115039 ""}
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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off CounterDemo -c CounterDemo " "Command: quartus_map --read_settings_files=on --write_settings_files=off CounterDemo -c CounterDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679318115039 ""}
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{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1679318115167 ""}
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{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1679318115167 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CounterUpDown4.vhd 2 1 " "Found 2 design units, including 1 entities, in source file CounterUpDown4.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 CounterUpDown4-Behavioral " "Found design unit 1: CounterUpDown4-Behavioral" { } { { "CounterUpDown4.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/CounterUpDown4.vhd" 15 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679318119662 ""} { "Info" "ISGN_ENTITY_NAME" "1 CounterUpDown4 " "Found entity 1: CounterUpDown4" { } { { "CounterUpDown4.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/CounterUpDown4.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679318119662 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679318119662 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CounterDown4.vhd 2 1 " "Found 2 design units, including 1 entities, in source file CounterDown4.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 CounterDown4-Behavioral " "Found design unit 1: CounterDown4-Behavioral" { } { { "CounterDown4.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDown4.vhd" 13 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679318119662 ""} { "Info" "ISGN_ENTITY_NAME" "1 CounterDown4 " "Found entity 1: CounterDown4" { } { { "CounterDown4.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDown4.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679318119662 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679318119662 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CounterDemo.bdf 1 1 " "Found 1 design units, including 1 entities, in source file CounterDemo.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 CounterDemo " "Found entity 1: CounterDemo" { } { { "CounterDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDemo.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679318119663 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679318119663 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Bin7SegDecoder.vhd 2 1 " "Found 2 design units, including 1 entities, in source file Bin7SegDecoder.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Bin7SegDecoder-Behavioral " "Found design unit 1: Bin7SegDecoder-Behavioral" { } { { "Bin7SegDecoder.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/Bin7SegDecoder.vhd" 12 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679318119663 ""} { "Info" "ISGN_ENTITY_NAME" "1 Bin7SegDecoder " "Found entity 1: Bin7SegDecoder" { } { { "Bin7SegDecoder.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/Bin7SegDecoder.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679318119663 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679318119663 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "FreqDivider.vhd 2 1 " "Found 2 design units, including 1 entities, in source file FreqDivider.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 FreqDivider-Behavioral " "Found design unit 1: FreqDivider-Behavioral" { } { { "FreqDivider.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/FreqDivider.vhd" 11 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679318119663 ""} { "Info" "ISGN_ENTITY_NAME" "1 FreqDivider " "Found entity 1: FreqDivider" { } { { "FreqDivider.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/FreqDivider.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679318119663 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679318119663 ""}
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{ "Info" "ISGN_START_ELABORATION_TOP" "CounterDemo " "Elaborating entity \"CounterDemo\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1679318119688 ""}
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{ "Warning" "WGDFX_SYMBOLS_OVERLAP_WARNING" "NOT inst3 " "Block or symbol \"NOT\" of instance \"inst3\" overlaps another block or symbol" { } { { "CounterDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDemo.bdf" { { 224 432 480 256 "inst3" "" } } } } } 0 275011 "Block or symbol \"%1!s!\" of instance \"%2!s!\" overlaps another block or symbol" 0 0 "Analysis & Synthesis" 0 -1 1679318119688 ""}
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{ "Warning" "WGDFX_SYMBOLS_OVERLAP_WARNING" "Bin7SegDecoder hex " "Block or symbol \"Bin7SegDecoder\" of instance \"hex\" overlaps another block or symbol" { } { { "CounterDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDemo.bdf" { { 192 672 880 272 "hex" "" } } } } } 0 275011 "Block or symbol \"%1!s!\" of instance \"%2!s!\" overlaps another block or symbol" 0 0 "Analysis & Synthesis" 0 -1 1679318119688 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Bin7SegDecoder Bin7SegDecoder:hex " "Elaborating entity \"Bin7SegDecoder\" for hierarchy \"Bin7SegDecoder:hex\"" { } { { "CounterDemo.bdf" "hex" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDemo.bdf" { { 192 672 880 272 "hex" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1679318119690 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CounterUpDown4 CounterUpDown4:inst " "Elaborating entity \"CounterUpDown4\" for hierarchy \"CounterUpDown4:inst\"" { } { { "CounterDemo.bdf" "inst" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDemo.bdf" { { 192 488 664 304 "inst" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1679318119691 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FreqDivider FreqDivider:inst1 " "Elaborating entity \"FreqDivider\" for hierarchy \"FreqDivider:inst1\"" { } { { "CounterDemo.bdf" "inst1" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDemo.bdf" { { 152 328 472 232 "inst1" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1679318119691 ""}
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{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1679318120030 ""}
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{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1679318120333 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1679318120333 ""}
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{ "Info" "ICUT_CUT_TM_SUMMARY" "82 " "Implemented 82 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Implemented 3 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1679318120349 ""} { "Info" "ICUT_CUT_TM_OPINS" "7 " "Implemented 7 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1679318120349 ""} { "Info" "ICUT_CUT_TM_LCELLS" "72 " "Implemented 72 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1679318120349 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1679318120349 ""}
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{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "446 " "Peak virtual memory: 446 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679318120352 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 20 13:15:20 2023 " "Processing ended: Mon Mar 20 13:15:20 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679318120352 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679318120352 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:13 " "Total CPU time (on all processors): 00:00:13" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679318120352 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1679318120352 ""}
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