427 lines
12 KiB
Plaintext
427 lines
12 KiB
Plaintext
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-- Copyright (C) 2020 Intel Corporation. All rights reserved.
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-- Your use of Intel Corporation's design tools, logic functions
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-- and other software and tools, and any partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Intel Program License
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-- Subscription Agreement, the Intel Quartus Prime License Agreement,
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-- the Intel FPGA IP License Agreement, or other applicable license
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-- agreement, including, without limitation, that your use is for
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-- the sole purpose of programming logic devices manufactured by
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-- Intel and sold by Intel or its authorized distributors. Please
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-- refer to the applicable agreement for further details, at
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-- https://fpgasoftware.intel.com/eula.
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-- VENDOR "Altera"
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-- PROGRAM "Quartus Prime"
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-- VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
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-- DATE "03/08/2023 11:38:17"
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--
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-- Device: Altera EP4CE115F29C7 Package FBGA780
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--
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--
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-- This VHDL file should be used for ModelSim-Altera (VHDL) only
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--
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LIBRARY CYCLONEIVE;
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LIBRARY IEEE;
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USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
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USE IEEE.STD_LOGIC_1164.ALL;
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ENTITY hard_block IS
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PORT (
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devoe : IN std_logic;
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devclrn : IN std_logic;
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devpor : IN std_logic
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);
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END hard_block;
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-- Design Ports Information
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-- ~ALTERA_ASDO_DATA1~ => Location: PIN_F4, I/O Standard: 2.5 V, Current Strength: Default
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-- ~ALTERA_FLASH_nCE_nCSO~ => Location: PIN_E2, I/O Standard: 2.5 V, Current Strength: Default
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-- ~ALTERA_DCLK~ => Location: PIN_P3, I/O Standard: 2.5 V, Current Strength: Default
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-- ~ALTERA_DATA0~ => Location: PIN_N7, I/O Standard: 2.5 V, Current Strength: Default
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-- ~ALTERA_nCEO~ => Location: PIN_P28, I/O Standard: 2.5 V, Current Strength: 8mA
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ARCHITECTURE structure OF hard_block IS
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SIGNAL gnd : std_logic := '0';
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SIGNAL vcc : std_logic := '1';
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SIGNAL unknown : std_logic := 'X';
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SIGNAL ww_devoe : std_logic;
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SIGNAL ww_devclrn : std_logic;
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SIGNAL ww_devpor : std_logic;
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SIGNAL \~ALTERA_ASDO_DATA1~~padout\ : std_logic;
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SIGNAL \~ALTERA_FLASH_nCE_nCSO~~padout\ : std_logic;
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SIGNAL \~ALTERA_DATA0~~padout\ : std_logic;
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SIGNAL \~ALTERA_ASDO_DATA1~~ibuf_o\ : std_logic;
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SIGNAL \~ALTERA_FLASH_nCE_nCSO~~ibuf_o\ : std_logic;
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SIGNAL \~ALTERA_DATA0~~ibuf_o\ : std_logic;
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BEGIN
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ww_devoe <= devoe;
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ww_devclrn <= devclrn;
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ww_devpor <= devpor;
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END structure;
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LIBRARY CYCLONEIVE;
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LIBRARY IEEE;
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USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
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USE IEEE.STD_LOGIC_1164.ALL;
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ENTITY AdderDemo IS
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PORT (
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LEDR : OUT std_logic_vector(4 DOWNTO 0);
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SW : IN std_logic_vector(7 DOWNTO 0)
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);
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END AdderDemo;
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-- Design Ports Information
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-- LEDR[4] => Location: PIN_F18, I/O Standard: 2.5 V, Current Strength: Default
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-- LEDR[3] => Location: PIN_F21, I/O Standard: 2.5 V, Current Strength: Default
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-- LEDR[2] => Location: PIN_E19, I/O Standard: 2.5 V, Current Strength: Default
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-- LEDR[1] => Location: PIN_F19, I/O Standard: 2.5 V, Current Strength: Default
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-- LEDR[0] => Location: PIN_G19, I/O Standard: 2.5 V, Current Strength: Default
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-- SW[7] => Location: PIN_AB26, I/O Standard: 2.5 V, Current Strength: Default
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-- SW[3] => Location: PIN_AD27, I/O Standard: 2.5 V, Current Strength: Default
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-- SW[6] => Location: PIN_AD26, I/O Standard: 2.5 V, Current Strength: Default
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-- SW[2] => Location: PIN_AC27, I/O Standard: 2.5 V, Current Strength: Default
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-- SW[0] => Location: PIN_AB28, I/O Standard: 2.5 V, Current Strength: Default
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-- SW[4] => Location: PIN_AB27, I/O Standard: 2.5 V, Current Strength: Default
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-- SW[1] => Location: PIN_AC28, I/O Standard: 2.5 V, Current Strength: Default
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-- SW[5] => Location: PIN_AC26, I/O Standard: 2.5 V, Current Strength: Default
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ARCHITECTURE structure OF AdderDemo IS
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SIGNAL gnd : std_logic := '0';
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SIGNAL vcc : std_logic := '1';
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SIGNAL unknown : std_logic := 'X';
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SIGNAL devoe : std_logic := '1';
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SIGNAL devclrn : std_logic := '1';
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SIGNAL devpor : std_logic := '1';
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SIGNAL ww_devoe : std_logic;
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SIGNAL ww_devclrn : std_logic;
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SIGNAL ww_devpor : std_logic;
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SIGNAL ww_LEDR : std_logic_vector(4 DOWNTO 0);
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SIGNAL ww_SW : std_logic_vector(7 DOWNTO 0);
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SIGNAL \LEDR[4]~output_o\ : std_logic;
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SIGNAL \LEDR[3]~output_o\ : std_logic;
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SIGNAL \LEDR[2]~output_o\ : std_logic;
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SIGNAL \LEDR[1]~output_o\ : std_logic;
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SIGNAL \LEDR[0]~output_o\ : std_logic;
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SIGNAL \SW[0]~input_o\ : std_logic;
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SIGNAL \SW[1]~input_o\ : std_logic;
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SIGNAL \SW[5]~input_o\ : std_logic;
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SIGNAL \SW[4]~input_o\ : std_logic;
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SIGNAL \Adder4Demo|bit1|cout~0_combout\ : std_logic;
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SIGNAL \SW[6]~input_o\ : std_logic;
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SIGNAL \SW[2]~input_o\ : std_logic;
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SIGNAL \Adder4Demo|bit2|cout~0_combout\ : std_logic;
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SIGNAL \SW[3]~input_o\ : std_logic;
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SIGNAL \SW[7]~input_o\ : std_logic;
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SIGNAL \Adder4Demo|bit3|cout~0_combout\ : std_logic;
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SIGNAL \Adder4Demo|bit3|s~combout\ : std_logic;
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SIGNAL \Adder4Demo|bit2|s~0_combout\ : std_logic;
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SIGNAL \Adder4Demo|bit1|s~0_combout\ : std_logic;
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SIGNAL \Adder4Demo|bit0|s~0_combout\ : std_logic;
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COMPONENT hard_block
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PORT (
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devoe : IN std_logic;
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devclrn : IN std_logic;
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devpor : IN std_logic);
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END COMPONENT;
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BEGIN
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LEDR <= ww_LEDR;
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ww_SW <= SW;
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ww_devoe <= devoe;
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ww_devclrn <= devclrn;
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ww_devpor <= devpor;
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auto_generated_inst : hard_block
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PORT MAP (
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devoe => ww_devoe,
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devclrn => ww_devclrn,
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devpor => ww_devpor);
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-- Location: IOOBUF_X87_Y73_N16
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\LEDR[4]~output\ : cycloneive_io_obuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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open_drain_output => "false")
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-- pragma translate_on
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PORT MAP (
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i => \Adder4Demo|bit3|cout~0_combout\,
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devoe => ww_devoe,
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o => \LEDR[4]~output_o\);
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-- Location: IOOBUF_X107_Y73_N16
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\LEDR[3]~output\ : cycloneive_io_obuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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open_drain_output => "false")
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-- pragma translate_on
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PORT MAP (
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i => \Adder4Demo|bit3|s~combout\,
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devoe => ww_devoe,
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o => \LEDR[3]~output_o\);
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-- Location: IOOBUF_X94_Y73_N9
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\LEDR[2]~output\ : cycloneive_io_obuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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open_drain_output => "false")
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-- pragma translate_on
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PORT MAP (
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i => \Adder4Demo|bit2|s~0_combout\,
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devoe => ww_devoe,
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o => \LEDR[2]~output_o\);
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-- Location: IOOBUF_X94_Y73_N2
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\LEDR[1]~output\ : cycloneive_io_obuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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open_drain_output => "false")
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-- pragma translate_on
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PORT MAP (
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i => \Adder4Demo|bit1|s~0_combout\,
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devoe => ww_devoe,
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o => \LEDR[1]~output_o\);
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-- Location: IOOBUF_X69_Y73_N16
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\LEDR[0]~output\ : cycloneive_io_obuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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open_drain_output => "false")
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-- pragma translate_on
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PORT MAP (
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i => \Adder4Demo|bit0|s~0_combout\,
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devoe => ww_devoe,
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o => \LEDR[0]~output_o\);
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-- Location: IOIBUF_X115_Y17_N1
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\SW[0]~input\ : cycloneive_io_ibuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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simulate_z_as => "z")
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-- pragma translate_on
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PORT MAP (
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i => ww_SW(0),
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o => \SW[0]~input_o\);
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-- Location: IOIBUF_X115_Y14_N1
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\SW[1]~input\ : cycloneive_io_ibuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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simulate_z_as => "z")
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-- pragma translate_on
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PORT MAP (
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i => ww_SW(1),
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o => \SW[1]~input_o\);
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-- Location: IOIBUF_X115_Y11_N8
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\SW[5]~input\ : cycloneive_io_ibuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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simulate_z_as => "z")
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-- pragma translate_on
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PORT MAP (
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i => ww_SW(5),
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o => \SW[5]~input_o\);
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-- Location: IOIBUF_X115_Y18_N8
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\SW[4]~input\ : cycloneive_io_ibuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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simulate_z_as => "z")
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-- pragma translate_on
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PORT MAP (
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i => ww_SW(4),
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o => \SW[4]~input_o\);
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-- Location: LCCOMB_X114_Y18_N24
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\Adder4Demo|bit1|cout~0\ : cycloneive_lcell_comb
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-- Equation(s):
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-- \Adder4Demo|bit1|cout~0_combout\ = (\SW[1]~input_o\ & ((\SW[5]~input_o\) # ((\SW[0]~input_o\ & \SW[4]~input_o\)))) # (!\SW[1]~input_o\ & (\SW[0]~input_o\ & (\SW[5]~input_o\ & \SW[4]~input_o\)))
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-- pragma translate_off
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GENERIC MAP (
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lut_mask => "1110100011000000",
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sum_lutc_input => "datac")
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-- pragma translate_on
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PORT MAP (
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dataa => \SW[0]~input_o\,
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datab => \SW[1]~input_o\,
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datac => \SW[5]~input_o\,
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datad => \SW[4]~input_o\,
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combout => \Adder4Demo|bit1|cout~0_combout\);
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-- Location: IOIBUF_X115_Y10_N1
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\SW[6]~input\ : cycloneive_io_ibuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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simulate_z_as => "z")
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-- pragma translate_on
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PORT MAP (
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i => ww_SW(6),
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o => \SW[6]~input_o\);
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-- Location: IOIBUF_X115_Y15_N8
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\SW[2]~input\ : cycloneive_io_ibuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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simulate_z_as => "z")
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-- pragma translate_on
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PORT MAP (
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i => ww_SW(2),
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o => \SW[2]~input_o\);
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-- Location: LCCOMB_X114_Y18_N10
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\Adder4Demo|bit2|cout~0\ : cycloneive_lcell_comb
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-- Equation(s):
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-- \Adder4Demo|bit2|cout~0_combout\ = (\Adder4Demo|bit1|cout~0_combout\ & ((\SW[6]~input_o\) # (\SW[2]~input_o\))) # (!\Adder4Demo|bit1|cout~0_combout\ & (\SW[6]~input_o\ & \SW[2]~input_o\))
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-- pragma translate_off
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GENERIC MAP (
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lut_mask => "1111110011000000",
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sum_lutc_input => "datac")
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-- pragma translate_on
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PORT MAP (
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datab => \Adder4Demo|bit1|cout~0_combout\,
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datac => \SW[6]~input_o\,
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datad => \SW[2]~input_o\,
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combout => \Adder4Demo|bit2|cout~0_combout\);
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-- Location: IOIBUF_X115_Y13_N8
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\SW[3]~input\ : cycloneive_io_ibuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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simulate_z_as => "z")
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-- pragma translate_on
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PORT MAP (
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i => ww_SW(3),
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o => \SW[3]~input_o\);
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-- Location: IOIBUF_X115_Y15_N1
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\SW[7]~input\ : cycloneive_io_ibuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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simulate_z_as => "z")
|
||
|
|
-- pragma translate_on
|
||
|
|
PORT MAP (
|
||
|
|
i => ww_SW(7),
|
||
|
|
o => \SW[7]~input_o\);
|
||
|
|
|
||
|
|
-- Location: LCCOMB_X114_Y18_N28
|
||
|
|
\Adder4Demo|bit3|cout~0\ : cycloneive_lcell_comb
|
||
|
|
-- Equation(s):
|
||
|
|
-- \Adder4Demo|bit3|cout~0_combout\ = (\Adder4Demo|bit2|cout~0_combout\ & ((\SW[3]~input_o\) # (\SW[7]~input_o\))) # (!\Adder4Demo|bit2|cout~0_combout\ & (\SW[3]~input_o\ & \SW[7]~input_o\))
|
||
|
|
|
||
|
|
-- pragma translate_off
|
||
|
|
GENERIC MAP (
|
||
|
|
lut_mask => "1111101010100000",
|
||
|
|
sum_lutc_input => "datac")
|
||
|
|
-- pragma translate_on
|
||
|
|
PORT MAP (
|
||
|
|
dataa => \Adder4Demo|bit2|cout~0_combout\,
|
||
|
|
datac => \SW[3]~input_o\,
|
||
|
|
datad => \SW[7]~input_o\,
|
||
|
|
combout => \Adder4Demo|bit3|cout~0_combout\);
|
||
|
|
|
||
|
|
-- Location: LCCOMB_X114_Y18_N22
|
||
|
|
\Adder4Demo|bit3|s\ : cycloneive_lcell_comb
|
||
|
|
-- Equation(s):
|
||
|
|
-- \Adder4Demo|bit3|s~combout\ = \Adder4Demo|bit2|cout~0_combout\ $ (\SW[3]~input_o\ $ (\SW[7]~input_o\))
|
||
|
|
|
||
|
|
-- pragma translate_off
|
||
|
|
GENERIC MAP (
|
||
|
|
lut_mask => "1010010101011010",
|
||
|
|
sum_lutc_input => "datac")
|
||
|
|
-- pragma translate_on
|
||
|
|
PORT MAP (
|
||
|
|
dataa => \Adder4Demo|bit2|cout~0_combout\,
|
||
|
|
datac => \SW[3]~input_o\,
|
||
|
|
datad => \SW[7]~input_o\,
|
||
|
|
combout => \Adder4Demo|bit3|s~combout\);
|
||
|
|
|
||
|
|
-- Location: LCCOMB_X114_Y18_N0
|
||
|
|
\Adder4Demo|bit2|s~0\ : cycloneive_lcell_comb
|
||
|
|
-- Equation(s):
|
||
|
|
-- \Adder4Demo|bit2|s~0_combout\ = \Adder4Demo|bit1|cout~0_combout\ $ (\SW[6]~input_o\ $ (\SW[2]~input_o\))
|
||
|
|
|
||
|
|
-- pragma translate_off
|
||
|
|
GENERIC MAP (
|
||
|
|
lut_mask => "1100001100111100",
|
||
|
|
sum_lutc_input => "datac")
|
||
|
|
-- pragma translate_on
|
||
|
|
PORT MAP (
|
||
|
|
datab => \Adder4Demo|bit1|cout~0_combout\,
|
||
|
|
datac => \SW[6]~input_o\,
|
||
|
|
datad => \SW[2]~input_o\,
|
||
|
|
combout => \Adder4Demo|bit2|s~0_combout\);
|
||
|
|
|
||
|
|
-- Location: LCCOMB_X114_Y18_N26
|
||
|
|
\Adder4Demo|bit1|s~0\ : cycloneive_lcell_comb
|
||
|
|
-- Equation(s):
|
||
|
|
-- \Adder4Demo|bit1|s~0_combout\ = \SW[1]~input_o\ $ (\SW[5]~input_o\ $ (((\SW[0]~input_o\ & \SW[4]~input_o\))))
|
||
|
|
|
||
|
|
-- pragma translate_off
|
||
|
|
GENERIC MAP (
|
||
|
|
lut_mask => "1001011000111100",
|
||
|
|
sum_lutc_input => "datac")
|
||
|
|
-- pragma translate_on
|
||
|
|
PORT MAP (
|
||
|
|
dataa => \SW[0]~input_o\,
|
||
|
|
datab => \SW[1]~input_o\,
|
||
|
|
datac => \SW[5]~input_o\,
|
||
|
|
datad => \SW[4]~input_o\,
|
||
|
|
combout => \Adder4Demo|bit1|s~0_combout\);
|
||
|
|
|
||
|
|
-- Location: LCCOMB_X114_Y18_N4
|
||
|
|
\Adder4Demo|bit0|s~0\ : cycloneive_lcell_comb
|
||
|
|
-- Equation(s):
|
||
|
|
-- \Adder4Demo|bit0|s~0_combout\ = \SW[0]~input_o\ $ (\SW[4]~input_o\)
|
||
|
|
|
||
|
|
-- pragma translate_off
|
||
|
|
GENERIC MAP (
|
||
|
|
lut_mask => "0000111111110000",
|
||
|
|
sum_lutc_input => "datac")
|
||
|
|
-- pragma translate_on
|
||
|
|
PORT MAP (
|
||
|
|
datac => \SW[0]~input_o\,
|
||
|
|
datad => \SW[4]~input_o\,
|
||
|
|
combout => \Adder4Demo|bit0|s~0_combout\);
|
||
|
|
|
||
|
|
ww_LEDR(4) <= \LEDR[4]~output_o\;
|
||
|
|
|
||
|
|
ww_LEDR(3) <= \LEDR[3]~output_o\;
|
||
|
|
|
||
|
|
ww_LEDR(2) <= \LEDR[2]~output_o\;
|
||
|
|
|
||
|
|
ww_LEDR(1) <= \LEDR[1]~output_o\;
|
||
|
|
|
||
|
|
ww_LEDR(0) <= \LEDR[0]~output_o\;
|
||
|
|
END structure;
|
||
|
|
|
||
|
|
|