18 lines
560 B
VHDL
18 lines
560 B
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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entity Dec2_4En is
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port (
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enable : in std_logic;
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inputs : in std_logic_vector(1 downto 0);
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outputs : out std_logic_vector(3 downto 0)
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);
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end Dec2_4En;
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architecture BehavEquations of Dec2_4En is
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begin
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outputs(0) <= enable and (not inputs(1)) and (not inputs(1));
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outputs(1) <= enable and (not inputs(1)) and ( inputs(1));
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outputs(2) <= enable and ( inputs(1)) and (not inputs(1));
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outputs(3) <= enable and ( inputs(1)) and ( inputs(1));
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end BehavEquations;
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