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uaveiro-leci/1ano/2semestre/lsd/aula01/part2/db/AND2Gate.hier_info

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LSD aula01 initial commit, base VHDL files, to be finished along the hardware
2023-02-20 22:37:32 +00:00
|GateDemo
LSD: aula01 part2 finished
2023-03-01 12:17:08 +00:00
SW[0] => nand2gate:system_core.inPort0
SW[1] => nand2gate:system_core.inPort1
LEDR[0] <= nand2gate:system_core.outPort
LSD aula01 initial commit, base VHDL files, to be finished along the hardware
2023-02-20 22:37:32 +00:00
LEDR[1] <= <GND>
LSD: aula01 part2 finished
2023-03-01 12:17:08 +00:00
|GateDemo|NAND2Gate:system_core
inPort0 => and2gate:and_gate.inPort0
inPort1 => and2gate:and_gate.inPort1
outPort <= notgate:not_gate.outPort
|GateDemo|NAND2Gate:system_core|AND2Gate:and_gate
LSD aula01 initial commit, base VHDL files, to be finished along the hardware
2023-02-20 22:37:32 +00:00
inPort0 => outPort.IN0
inPort1 => outPort.IN1
outPort <= outPort.DB_MAX_OUTPUT_PORT_TYPE
LSD: aula01 part2 finished
2023-03-01 12:17:08 +00:00
|GateDemo|NAND2Gate:system_core|NOTGate:not_gate
inPort => outPort.DATAIN
outPort <= inPort.DB_MAX_OUTPUT_PORT_TYPE