85 lines
2.0 KiB
VHDL
85 lines
2.0 KiB
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.NUMERIC_STD.all;
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entity BreadMachine is
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port
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(
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CLOCK_50 : in std_logic;
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KEY : in std_logic_vector(3 downto 0);
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SW : in std_logic_vector(17 downto 0);
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LEDR : out std_logic_vector(0 downto 0);
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LEDG : out std_logic_vector(2 downto 0);
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HEX2 : out std_logic_vector(6 downto 0);
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HEX3 : out std_logic_vector(6 downto 0);
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HEX4 : out std_logic_vector(6 downto 0);
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HEX6 : out std_logic_vector(6 downto 0);
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HEX7 : out std_logic_vector(6 downto 0)
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);
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end BreadMachine;
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architecture Demo of BreadMachine is
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-- global main signals
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signal s_reset : std_logic := '0';
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-- processed signals
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signal s_program, s_timeAdj, s_startStop, s_finished : std_logic;
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signal current_delay, current_time : std_logic_vector(6 downto 0);
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signal s_extra_time : std_logic_vector(3 downto 0);
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signal s_display7, s_display6, s_display1, s_display0 : std_logic_vector(3 downto 0);
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signal s_phase : std_logic_vector(1 downto 0);
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begin
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-- Debounces all the keys
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keys_debouncer : entity work.Debouncers(Debounce)
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port map
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(
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clock => CLOCK_50,
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reset_btn => KEY(3),
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start_stop_btn => KEY(1),
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time_adjust_btn => KEY(0),
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reset_out => s_reset,
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start_stop_out => s_startStop,
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time_adjust_out => s_timeAdj
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);
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fsm : entity work.BreadMachineFSM(Behavioral)
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port map
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(
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clock => CLOCK_50,
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reset => s_reset,
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delayer_sw => SW(17 downto 11),
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program_sw => SW(0),
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time_adj_but => s_timeAdj,
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start_stop_but => s_startStop,
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in_progress => LEDR(0),
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leds_phase => LEDG,
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current_delay => current_delay,
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current_time => current_time,
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extra_time => s_extra_time
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);
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displays : entity work.DisplaysManager(Behavioral)
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port map
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(
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bin_delay => current_delay,
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bin_total => current_time,
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bin_extra => s_extra_time,
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D_HEX2 => HEX2,
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D_HEX3 => HEX3,
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D_HEX4 => HEX4,
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D_HEX6 => HEX6,
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D_HEX7 => HEX7
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);
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end Demo;
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