44 lines
940 B
VHDL
44 lines
940 B
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.NUMERIC_STD.all;
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entity Counter4Bits is
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port(MAX : natural := 9;
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reset : in std_logic;
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clk : in std_logic;
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enable1 : in std_logic;
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enable2 : in std_logic;
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valOut : out std_logic_vector(3 downto 0);
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termCnt : out std_logic);
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end Counter4Bits;
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architecture RTL of Counter4Bits is
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signal s_value : unsigned(3 downto 0);
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begin
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process(reset, clk)
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begin
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if (rising_edge(clk)) then
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if (reset = '1') then
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s_value <= (others => '0');
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termCnt <= '0';
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elsif ((enable1 = '1') and (enable2 = '1')) then
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if (to_integer(s_value) = MAX) then
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s_value <= (others => '0');
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termCnt <= '0';
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else
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s_value <= s_value + 1;
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if (to_integer(s_value) = MAX - 1) then
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termCnt <= '1';
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else
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termCnt <= '0';
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end if;
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end if;
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end if;
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end if;
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end process;
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valOut <= std_logic_vector(s_value);
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end RTL;
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