49 lines
3.6 KiB
Plaintext
49 lines
3.6 KiB
Plaintext
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vendor_name = ModelSim
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source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/Bin7SegDecoder.vhd
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source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/DisplayDemoVHDL.vhd
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source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_b.vhd
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source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_p.vhd
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source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_b.vhd
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source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_p.vhd
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source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/db/DisplayDemoVHDL.cbx.xml
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design_name = hard_block
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design_name = DisplayDemoVHDL
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instance = comp, \LEDG[0]~output\, LEDG[0]~output, DisplayDemoVHDL, 1
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instance = comp, \LEDG[1]~output\, LEDG[1]~output, DisplayDemoVHDL, 1
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instance = comp, \LEDG[2]~output\, LEDG[2]~output, DisplayDemoVHDL, 1
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instance = comp, \LEDG[3]~output\, LEDG[3]~output, DisplayDemoVHDL, 1
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instance = comp, \LEDR[0]~output\, LEDR[0]~output, DisplayDemoVHDL, 1
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instance = comp, \LEDR[1]~output\, LEDR[1]~output, DisplayDemoVHDL, 1
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instance = comp, \LEDR[2]~output\, LEDR[2]~output, DisplayDemoVHDL, 1
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instance = comp, \LEDR[3]~output\, LEDR[3]~output, DisplayDemoVHDL, 1
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instance = comp, \LEDR[4]~output\, LEDR[4]~output, DisplayDemoVHDL, 1
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instance = comp, \LEDR[5]~output\, LEDR[5]~output, DisplayDemoVHDL, 1
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instance = comp, \LEDR[6]~output\, LEDR[6]~output, DisplayDemoVHDL, 1
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instance = comp, \HEX0[0]~output\, HEX0[0]~output, DisplayDemoVHDL, 1
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instance = comp, \HEX0[1]~output\, HEX0[1]~output, DisplayDemoVHDL, 1
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instance = comp, \HEX0[2]~output\, HEX0[2]~output, DisplayDemoVHDL, 1
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instance = comp, \HEX0[3]~output\, HEX0[3]~output, DisplayDemoVHDL, 1
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instance = comp, \HEX0[4]~output\, HEX0[4]~output, DisplayDemoVHDL, 1
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instance = comp, \HEX0[5]~output\, HEX0[5]~output, DisplayDemoVHDL, 1
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instance = comp, \HEX0[6]~output\, HEX0[6]~output, DisplayDemoVHDL, 1
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instance = comp, \SW[0]~input\, SW[0]~input, DisplayDemoVHDL, 1
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instance = comp, \SW[1]~input\, SW[1]~input, DisplayDemoVHDL, 1
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instance = comp, \SW[2]~input\, SW[2]~input, DisplayDemoVHDL, 1
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instance = comp, \SW[3]~input\, SW[3]~input, DisplayDemoVHDL, 1
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instance = comp, \KEY[0]~input\, KEY[0]~input, DisplayDemoVHDL, 1
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instance = comp, \system_core|decOut_n~6\, system_core|decOut_n~6, DisplayDemoVHDL, 1
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instance = comp, \system_core|decOut_n~7\, system_core|decOut_n~7, DisplayDemoVHDL, 1
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instance = comp, \system_core|decOut_n~8\, system_core|decOut_n~8, DisplayDemoVHDL, 1
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instance = comp, \system_core|decOut_n~9\, system_core|decOut_n~9, DisplayDemoVHDL, 1
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instance = comp, \system_core|decOut_n~10\, system_core|decOut_n~10, DisplayDemoVHDL, 1
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instance = comp, \system_core|decOut_n~11\, system_core|decOut_n~11, DisplayDemoVHDL, 1
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instance = comp, \system_core|decOut_n[3]~2\, system_core|decOut_n[3]~2, DisplayDemoVHDL, 1
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instance = comp, \system_core|decOut_n[3]~16\, system_core|decOut_n[3]~16, DisplayDemoVHDL, 1
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instance = comp, \system_core|decOut_n~12\, system_core|decOut_n~12, DisplayDemoVHDL, 1
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instance = comp, \system_core|decOut_n~13\, system_core|decOut_n~13, DisplayDemoVHDL, 1
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instance = comp, \system_core|decOut_n~14\, system_core|decOut_n~14, DisplayDemoVHDL, 1
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instance = comp, \system_core|decOut_n~15\, system_core|decOut_n~15, DisplayDemoVHDL, 1
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instance = comp, \system_core|decOut_n[6]~5\, system_core|decOut_n[6]~5, DisplayDemoVHDL, 1
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instance = comp, \system_core|decOut_n[6]~17\, system_core|decOut_n[6]~17, DisplayDemoVHDL, 1
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instance = comp, \KEY[1]~input\, KEY[1]~input, DisplayDemoVHDL, 1
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