13 lines
849 B
Plaintext
13 lines
849 B
Plaintext
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vendor_name = ModelSim
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source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/AND2Gate.vhd
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source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_b.vhd
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source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_p.vhd
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source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_b.vhd
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source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_p.vhd
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source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula01/part2/db/AND2Gate.cbx.xml
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design_name = AND2Gate
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instance = comp, \outPort~output\, outPort~output, AND2Gate, 1
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instance = comp, \inPort0~input\, inPort0~input, AND2Gate, 1
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instance = comp, \inPort1~input\, inPort1~input, AND2Gate, 1
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instance = comp, \outPort~0\, outPort~0, AND2Gate, 1
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