84 lines
1.6 KiB
VHDL
84 lines
1.6 KiB
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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entity MiniProj_Demo is
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port
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(
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CLOCK_50 : in std_logic;
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KEY : in std_logic_vector(1 downto 0);
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LEDR : out std_logic_vector(14 downto 0);
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HEX0 : out std_logic_vector(6 downto 0);
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HEX1 : out std_logic_vector(6 downto 0)
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);
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end MiniProj_Demo;
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architecture Shell of MiniProj_Demo is
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signal s_clk_def, s_clk_div : std_logic;
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signal s_speed : positive := 4;
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signal s_reset : std_logic;
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signal s_count : std_logic_vector(3 downto 0);
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signal s_display0, s_display1 : std_logic_vector(3 downto 0);
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begin
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s_clk_def <= CLOCK_50;
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s_reset <= not KEY(0);
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speed_select : entity work.SpeedSelect(Behavioral)
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port map
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(
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toggle => not KEY(1),
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reset => s_reset,
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speed => s_speed
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);
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freq_divider : entity work.FreqDivider(Behavioral)
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generic map (divFactor => 50_000_000)
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port map
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(
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clkIn => s_clk_def,
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multi => s_speed,
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clkOut => s_clk_div
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);
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counter : entity work.Counter(Behavioral)
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port map
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(
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clk => s_clk_div,
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reset => s_reset,
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count => s_count
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);
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led_display : entity work.LedDisplayer(Behavioral)
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port map
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(
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count => s_count,
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ledOut => LEDR
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);
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hex_to_dec : entity work.HexToDec4Bit(Behavioral)
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port map
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(
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hexIn => s_count,
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cin => '0',
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decOut0 => s_display0,
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decOut1 => s_display1
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);
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display0 : entity work.Bin7SegDecoder(Behavioral)
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port map
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(
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enable => '1',
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binInput => s_display0,
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decOut_n => HEX0
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);
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display1 : entity work.Bin7SegDecoder(Behavioral)
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port map
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(
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enable => '1',
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binInput => s_display1,
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decOut_n => HEX1
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);
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end Shell;
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