34 lines
771 B
VHDL
34 lines
771 B
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.NUMERIC_STD.all;
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entity CombShiftUnit_Demo is
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port
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(
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CLOCK_50 : in std_logic;
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SW : in std_logic_vector(17 downto 0);
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KEY : in std_logic_vector(2 downto 0);
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LEDR : out std_logic_vector(7 downto 0)
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);
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end CombShiftUnit_Demo;
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architecture Shell of CombShiftUnit_Demo is
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signal clk : std_logic;
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begin
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freq : entity work.FreqDivider(Behavioral)
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generic map (divFactor => 12_500_000)
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port map (clkIn => CLOCK_50, clkOut => clk);
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core : entity work.CombShiftUnit(Behavioral)
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port map
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(
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clk => clk,
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dataIn => SW(7 downto 0),
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loadEn => SW(8),
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rotate => KEY(0),
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dirLeft => KEY(1),
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shArith => KEY(2),
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shAmount => SW(17 downto 15),
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dataOut => LEDR
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);
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end Shell;
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