27 lines
565 B
VHDL
27 lines
565 B
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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entity NAND2Gate is
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port (
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inPort0 : in std_logic;
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inPort1 : in std_logic;
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outPort : out std_logic
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);
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end NAND2Gate;
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architecture Structural of NAND2Gate is
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signal s_andOut : std_logic;
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begin
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and_gate : entity work.AND2Gate(Behavioral)
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port map(
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inPort0 => inPort0,
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inPort1 => inPort1,
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outPort => s_andOut
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);
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not_gate : entity work.NOTGate(Behavioral)
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port map(
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inPort => s_andOut,
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outPort => outPort
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);
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end Structural;
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