52 lines
1.8 KiB
Plaintext
52 lines
1.8 KiB
Plaintext
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/*
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WARNING: Do NOT edit the input and output ports in this file in a text
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editor if you plan to continue editing the block that represents it in
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the Block Editor! File corruption is VERY likely to occur.
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*/
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/*
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Copyright (C) 2020 Intel Corporation. All rights reserved.
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Your use of Intel Corporation's design tools, logic functions
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and other software and tools, and any partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Intel Program License
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Subscription Agreement, the Intel Quartus Prime License Agreement,
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the Intel FPGA IP License Agreement, or other applicable license
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agreement, including, without limitation, that your use is for
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the sole purpose of programming logic devices manufactured by
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Intel and sold by Intel or its authorized distributors. Please
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refer to the applicable agreement for further details, at
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https://fpgasoftware.intel.com/eula.
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*/
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(header "symbol" (version "1.1"))
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(symbol
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(rect 16 16 176 96)
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(text "AND2Gate" (rect 5 0 51 12)(font "Arial" ))
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(text "inst" (rect 8 64 20 76)(font "Arial" ))
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(port
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(pt 0 32)
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(input)
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(text "inPort0" (rect 0 0 27 12)(font "Arial" ))
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(text "inPort0" (rect 21 27 48 39)(font "Arial" ))
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(line (pt 0 32)(pt 16 32)(line_width 1))
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)
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(port
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(pt 0 48)
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(input)
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(text "inPort1" (rect 0 0 25 12)(font "Arial" ))
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(text "inPort1" (rect 21 43 46 55)(font "Arial" ))
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(line (pt 0 48)(pt 16 48)(line_width 1))
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)
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(port
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(pt 160 32)
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(output)
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(text "outPort" (rect 0 0 28 12)(font "Arial" ))
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(text "outPort" (rect 111 27 139 39)(font "Arial" ))
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(line (pt 160 32)(pt 144 32)(line_width 1))
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)
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(drawing
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(rectangle (rect 16 16 144 64)(line_width 1))
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)
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)
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