478 lines
18 KiB
Plaintext
478 lines
18 KiB
Plaintext
|
-- Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||
|
|
-- Your use of Intel Corporation's design tools, logic functions
|
||
|
|
-- and other software and tools, and any partner logic
|
||
|
|
-- functions, and any output files from any of the foregoing
|
||
|
|
-- (including device programming or simulation files), and any
|
||
|
|
-- associated documentation or information are expressly subject
|
||
|
|
-- to the terms and conditions of the Intel Program License
|
||
|
|
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||
|
|
-- the Intel FPGA IP License Agreement, or other applicable license
|
||
|
|
-- agreement, including, without limitation, that your use is for
|
||
|
|
-- the sole purpose of programming logic devices manufactured by
|
||
|
|
-- Intel and sold by Intel or its authorized distributors. Please
|
||
|
|
-- refer to the applicable agreement for further details, at
|
||
|
|
-- https://fpgasoftware.intel.com/eula.
|
||
|
|
|
||
|
|
-- VENDOR "Altera"
|
||
|
|
-- PROGRAM "Quartus Prime"
|
||
|
|
-- VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
|
||
|
|
|
||
|
|
-- DATE "03/07/2023 18:06:08"
|
||
|
|
|
||
|
|
--
|
||
|
|
-- Device: Altera EP4CE115F29C7 Package FBGA780
|
||
|
|
--
|
||
|
|
|
||
|
|
--
|
||
|
|
-- This VHDL file should be used for ModelSim-Altera (VHDL) only
|
||
|
|
--
|
||
|
|
|
||
|
|
LIBRARY CYCLONEIVE;
|
||
|
|
LIBRARY IEEE;
|
||
|
|
USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
|
||
|
|
USE IEEE.STD_LOGIC_1164.ALL;
|
||
|
|
|
||
|
|
ENTITY hard_block IS
|
||
|
|
PORT (
|
||
|
|
devoe : IN std_logic;
|
||
|
|
devclrn : IN std_logic;
|
||
|
|
devpor : IN std_logic
|
||
|
|
);
|
||
|
|
END hard_block;
|
||
|
|
|
||
|
|
-- Design Ports Information
|
||
|
|
-- AUD_ADCDAT => Location: PIN_D2, I/O Standard: 3.3-V LVTTL, Current Strength: Default
|
||
|
|
-- CLOCK2_50 => Location: PIN_AG14, I/O Standard: 3.3-V LVTTL, Current Strength: Default
|
||
|
|
-- CLOCK3_50 => Location: PIN_AG15, I/O Standard: 3.3-V LVTTL, Current Strength: Default
|
||
|
|
-- CLOCK_50 => Location: PIN_Y2, I/O Standard: 2.5 V, Current Strength: Default
|
||
|
|
-- ENET0_INT_N => Location: PIN_A21, I/O Standard: 2.5 V, Current Strength: Default
|
||
|
|
-- ENET0_LINK100 => Location: PIN_C14, I/O Standard: 3.3-V LVTTL, Current Strength: Default
|
||
|
|
-- ENET0_MDIO => Location: PIN_B21, I/O Standard: 2.5 V, Current Strength: Default
|
||
|
|
-- ENET0_RX_CLK => Location: PIN_A15, I/O Standard: 2.5 V, Current Strength: Default
|
||
|
|
-- ENET0_RX_COL => Location: PIN_E15, I/O Standard: 2.5 V, Current Strength: Default
|
||
|
|
-- ENET0_RX_CRS => Location: PIN_D15, I/O Standard: 2.5 V, Current Strength: Default
|
||
|
|
-- ENET0_RX_DATA[0] => Location: PIN_C16, I/O Standard: 2.5 V, Current Strength: Default
|
||
|
|
-- ENET0_RX_DATA[1] => Location: PIN_D16, I/O Standard: 2.5 V, Current Strength: Default
|
||
|
|
-- ENET0_RX_DATA[2] => Location: PIN_D17, I/O Standard: 2.5 V, Current Strength: Default
|
||
|
|
-- ENET0_RX_DATA[3] => Location: PIN_C15, I/O Standard: 2.5 V, Current Strength: Default
|
||
|
|
-- ENET0_RX_DV => Location: PIN_C17, I/O Standard: 2.5 V, Current Strength: Default
|
||
|
|
-- ENET0_RX_ER => Location: PIN_D18, I/O Standard: 2.5 V, Current Strength: Default
|
||
|
|
-- ENET0_TX_CLK => Location: PIN_B17, I/O Standard: 2.5 V, Current Strength: Default
|
||
|
|
-- ENET1_INT_N => Location: PIN_D24, I/O Standard: 2.5 V, Current Strength: Default
|
||
|
|
-- ENET1_LINK100 => Location: PIN_D13, I/O Standard: 3.3-V LVTTL, Current Strength: Default
|
||
|
|
-- ENET1_MDIO => Location: PIN_D25, I/O Standard: 2.5 V, Current Strength: Default
|
||
|
|
-- ENET1_RX_CLK => Location: PIN_B15, I/O Standard: 2.5 V, Current Strength: Default
|
||
|
|
-- ENET1_RX_COL => Location: PIN_B22, I/O Standard: 2.5 V, Current Strength: Default
|
||
|
|
-- ENET1_RX_CRS => Location: PIN_D20, I/O Standard: 2.5 V, Current Strength: Default
|
||
|
|
-- ENET1_RX_DATA[0] => Location: PIN_B23, I/O Standard: 2.5 V, Current Strength: Default
|
||
|
|
-- ENET1_RX_DATA[1] => Location: PIN_C21, I/O Standard: 2.5 V, Current Strength: Default
|
||
|
|
-- ENET1_RX_DATA[2] => Location: PIN_A23, I/O Standard: 2.5 V, Current Strength: Default
|
||
|
|
-- ENET1_RX_DATA[3] => Location: PIN_D21, I/O Standard: 2.5 V, Current Strength: Default
|
||
|
|
-- ENET1_RX_DV => Location: PIN_A22, I/O Standard: 2.5 V, Current Strength: Default
|
||
|
|
-- ENET1_RX_ER => Location: PIN_C24, I/O Standard: 2.5 V, Current Strength: Default
|
||
|
|
-- ENET1_TX_CLK => Location: PIN_C22, I/O Standard: 2.5 V, Current Strength: Default
|
||
|
|
-- ENETCLK_25 => Location: PIN_A14, I/O Standard: 3.3-V LVTTL, Current Strength: Default
|
||
|
|
-- FL_RY => Location: PIN_Y1, I/O Standard: 3.3-V LVTTL, Current Strength: Default
|
||
|
|
-- HSMC_CLKIN0 => Location: PIN_AH15, I/O Standard: 3.3-V LVTTL, Current Strength: Default
|
||
|
|
-- IRDA_RXD => Location: PIN_Y15, I/O Standard: 3.3-V LVTTL, Current Strength: Default
|
||
|
|
-- KEY[0] => Location: PIN_M23, I/O Standard: 2.5 V, Current Strength: Default
|
||
|
|
-- KEY[1] => Location: PIN_M21, I/O Standard: 2.5 V, Current Strength: Default
|
||
|
|
-- KEY[2] => Location: PIN_N21, I/O Standard: 2.5 V, Current Strength: Default
|
||
|
|
-- KEY[3] => Location: PIN_R24, I/O Standard: 2.5 V, Current Strength: Default
|
||
|
|
-- OTG_INT => Location: PIN_D5, I/O Standard: 3.3-V LVTTL, Current Strength: Default
|
||
|
|
-- SD_WP_N => Location: PIN_AF14, I/O Standard: 3.3-V LVTTL, Current Strength: Default
|
||
|
|
-- SMA_CLKIN => Location: PIN_AH14, I/O Standard: 3.3-V LVTTL, Current Strength: Default
|
||
|
|
-- SW[10] => Location: PIN_AC24, I/O Standard: 2.5 V, Current Strength: Default
|
||
|
|
-- SW[11] => Location: PIN_AB24, I/O Standard: 2.5 V, Current Strength: Default
|
||
|
|
-- SW[12] => Location: PIN_AB23, I/O Standard: 2.5 V, Current Strength: Default
|
||
|
|
-- SW[13] => Location: PIN_AA24, I/O Standard: 2.5 V, Current Strength: Default
|
||
|
|
-- SW[14] => Location: PIN_AA23, I/O Standard: 2.5 V, Current Strength: Default
|
||
|
|
-- SW[15] => Location: PIN_AA22, I/O Standard: 2.5 V, Current Strength: Default
|
||
|
|
-- SW[16] => Location: PIN_Y24, I/O Standard: 2.5 V, Current Strength: Default
|
||
|
|
-- SW[17] => Location: PIN_Y23, I/O Standard: 2.5 V, Current Strength: Default
|
||
|
|
-- SW[8] => Location: PIN_AC25, I/O Standard: 2.5 V, Current Strength: Default
|
||
|
|
-- SW[9] => Location: PIN_AB25, I/O Standard: 2.5 V, Current Strength: Default
|
||
|
|
-- TD_CLK27 => Location: PIN_B14, I/O Standard: 3.3-V LVTTL, Current Strength: Default
|
||
|
|
-- TD_DATA[0] => Location: PIN_E8, I/O Standard: 3.3-V LVTTL, Current Strength: Default
|
||
|
|
-- TD_DATA[1] => Location: PIN_A7, I/O Standard: 3.3-V LVTTL, Current Strength: Default
|
||
|
|
-- TD_DATA[2] => Location: PIN_D8, I/O Standard: 3.3-V LVTTL, Current Strength: Default
|
||
|
|
-- TD_DATA[3] => Location: PIN_C7, I/O Standard: 3.3-V LVTTL, Current Strength: Default
|
||
|
|
-- TD_DATA[4] => Location: PIN_D7, I/O Standard: 3.3-V LVTTL, Current Strength: Default
|
||
|
|
-- TD_DATA[5] => Location: PIN_D6, I/O Standard: 3.3-V LVTTL, Current Strength: Default
|
||
|
|
-- TD_DATA[6] => Location: PIN_E7, I/O Standard: 3.3-V LVTTL, Current Strength: Default
|
||
|
|
-- TD_DATA[7] => Location: PIN_F7, I/O Standard: 3.3-V LVTTL, Current Strength: Default
|
||
|
|
-- TD_HS => Location: PIN_E5, I/O Standard: 3.3-V LVTTL, Current Strength: Default
|
||
|
|
-- TD_VS => Location: PIN_E4, I/O Standard: 3.3-V LVTTL, Current Strength: Default
|
||
|
|
-- UART_RTS => Location: PIN_J13, I/O Standard: 3.3-V LVTTL, Current Strength: Default
|
||
|
|
-- UART_RXD => Location: PIN_G12, I/O Standard: 3.3-V LVTTL, Current Strength: Default
|
||
|
|
-- ~ALTERA_ASDO_DATA1~ => Location: PIN_F4, I/O Standard: 3.3-V LVTTL, Current Strength: Default
|
||
|
|
-- ~ALTERA_FLASH_nCE_nCSO~ => Location: PIN_E2, I/O Standard: 3.3-V LVTTL, Current Strength: Default
|
||
|
|
-- ~ALTERA_DCLK~ => Location: PIN_P3, I/O Standard: 3.3-V LVTTL, Current Strength: Default
|
||
|
|
-- ~ALTERA_DATA0~ => Location: PIN_N7, I/O Standard: 3.3-V LVTTL, Current Strength: Default
|
||
|
|
-- ~ALTERA_nCEO~ => Location: PIN_P28, I/O Standard: 2.5 V, Current Strength: 8mA
|
||
|
|
|
||
|
|
|
||
|
|
ARCHITECTURE structure OF hard_block IS
|
||
|
|
SIGNAL gnd : std_logic := '0';
|
||
|
|
SIGNAL vcc : std_logic := '1';
|
||
|
|
SIGNAL unknown : std_logic := 'X';
|
||
|
|
SIGNAL ww_devoe : std_logic;
|
||
|
|
SIGNAL ww_devclrn : std_logic;
|
||
|
|
SIGNAL ww_devpor : std_logic;
|
||
|
|
SIGNAL \AUD_ADCDAT~padout\ : std_logic;
|
||
|
|
SIGNAL \CLOCK2_50~padout\ : std_logic;
|
||
|
|
SIGNAL \CLOCK3_50~padout\ : std_logic;
|
||
|
|
SIGNAL \CLOCK_50~padout\ : std_logic;
|
||
|
|
SIGNAL \ENET0_INT_N~padout\ : std_logic;
|
||
|
|
SIGNAL \ENET0_LINK100~padout\ : std_logic;
|
||
|
|
SIGNAL \ENET0_MDIO~padout\ : std_logic;
|
||
|
|
SIGNAL \ENET0_RX_CLK~padout\ : std_logic;
|
||
|
|
SIGNAL \ENET0_RX_COL~padout\ : std_logic;
|
||
|
|
SIGNAL \ENET0_RX_CRS~padout\ : std_logic;
|
||
|
|
SIGNAL \ENET0_RX_DATA[0]~padout\ : std_logic;
|
||
|
|
SIGNAL \ENET0_RX_DATA[1]~padout\ : std_logic;
|
||
|
|
SIGNAL \ENET0_RX_DATA[2]~padout\ : std_logic;
|
||
|
|
SIGNAL \ENET0_RX_DATA[3]~padout\ : std_logic;
|
||
|
|
SIGNAL \ENET0_RX_DV~padout\ : std_logic;
|
||
|
|
SIGNAL \ENET0_RX_ER~padout\ : std_logic;
|
||
|
|
SIGNAL \ENET0_TX_CLK~padout\ : std_logic;
|
||
|
|
SIGNAL \ENET1_INT_N~padout\ : std_logic;
|
||
|
|
SIGNAL \ENET1_LINK100~padout\ : std_logic;
|
||
|
|
SIGNAL \ENET1_MDIO~padout\ : std_logic;
|
||
|
|
SIGNAL \ENET1_RX_CLK~padout\ : std_logic;
|
||
|
|
SIGNAL \ENET1_RX_COL~padout\ : std_logic;
|
||
|
|
SIGNAL \ENET1_RX_CRS~padout\ : std_logic;
|
||
|
|
SIGNAL \ENET1_RX_DATA[0]~padout\ : std_logic;
|
||
|
|
SIGNAL \ENET1_RX_DATA[1]~padout\ : std_logic;
|
||
|
|
SIGNAL \ENET1_RX_DATA[2]~padout\ : std_logic;
|
||
|
|
SIGNAL \ENET1_RX_DATA[3]~padout\ : std_logic;
|
||
|
|
SIGNAL \ENET1_RX_DV~padout\ : std_logic;
|
||
|
|
SIGNAL \ENET1_RX_ER~padout\ : std_logic;
|
||
|
|
SIGNAL \ENET1_TX_CLK~padout\ : std_logic;
|
||
|
|
SIGNAL \ENETCLK_25~padout\ : std_logic;
|
||
|
|
SIGNAL \FL_RY~padout\ : std_logic;
|
||
|
|
SIGNAL \HSMC_CLKIN0~padout\ : std_logic;
|
||
|
|
SIGNAL \IRDA_RXD~padout\ : std_logic;
|
||
|
|
SIGNAL \KEY[0]~padout\ : std_logic;
|
||
|
|
SIGNAL \KEY[1]~padout\ : std_logic;
|
||
|
|
SIGNAL \KEY[2]~padout\ : std_logic;
|
||
|
|
SIGNAL \KEY[3]~padout\ : std_logic;
|
||
|
|
SIGNAL \OTG_INT~padout\ : std_logic;
|
||
|
|
SIGNAL \SD_WP_N~padout\ : std_logic;
|
||
|
|
SIGNAL \SMA_CLKIN~padout\ : std_logic;
|
||
|
|
SIGNAL \TD_CLK27~padout\ : std_logic;
|
||
|
|
SIGNAL \TD_DATA[0]~padout\ : std_logic;
|
||
|
|
SIGNAL \TD_DATA[1]~padout\ : std_logic;
|
||
|
|
SIGNAL \TD_DATA[2]~padout\ : std_logic;
|
||
|
|
SIGNAL \TD_DATA[3]~padout\ : std_logic;
|
||
|
|
SIGNAL \TD_DATA[4]~padout\ : std_logic;
|
||
|
|
SIGNAL \TD_DATA[5]~padout\ : std_logic;
|
||
|
|
SIGNAL \TD_DATA[6]~padout\ : std_logic;
|
||
|
|
SIGNAL \TD_DATA[7]~padout\ : std_logic;
|
||
|
|
SIGNAL \TD_HS~padout\ : std_logic;
|
||
|
|
SIGNAL \TD_VS~padout\ : std_logic;
|
||
|
|
SIGNAL \UART_RTS~padout\ : std_logic;
|
||
|
|
SIGNAL \UART_RXD~padout\ : std_logic;
|
||
|
|
SIGNAL \~ALTERA_ASDO_DATA1~~padout\ : std_logic;
|
||
|
|
SIGNAL \~ALTERA_FLASH_nCE_nCSO~~padout\ : std_logic;
|
||
|
|
SIGNAL \~ALTERA_DATA0~~padout\ : std_logic;
|
||
|
|
SIGNAL \AUD_ADCDAT~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \CLOCK2_50~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \CLOCK3_50~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \CLOCK_50~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \ENET0_INT_N~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \ENET0_LINK100~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \ENET0_MDIO~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \ENET0_RX_CLK~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \ENET0_RX_COL~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \ENET0_RX_CRS~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \ENET0_RX_DATA[0]~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \ENET0_RX_DATA[1]~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \ENET0_RX_DATA[2]~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \ENET0_RX_DATA[3]~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \ENET0_RX_DV~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \ENET0_RX_ER~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \ENET0_TX_CLK~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \ENET1_INT_N~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \ENET1_LINK100~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \ENET1_MDIO~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \ENET1_RX_CLK~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \ENET1_RX_COL~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \ENET1_RX_CRS~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \ENET1_RX_DATA[0]~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \ENET1_RX_DATA[1]~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \ENET1_RX_DATA[2]~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \ENET1_RX_DATA[3]~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \ENET1_RX_DV~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \ENET1_RX_ER~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \ENET1_TX_CLK~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \ENETCLK_25~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \FL_RY~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \HSMC_CLKIN0~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \IRDA_RXD~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \KEY[0]~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \KEY[1]~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \KEY[2]~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \KEY[3]~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \OTG_INT~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \SD_WP_N~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \SMA_CLKIN~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \SW[10]~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \SW[11]~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \SW[12]~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \SW[13]~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \SW[14]~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \SW[15]~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \SW[16]~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \SW[17]~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \SW[8]~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \SW[9]~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \TD_CLK27~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \TD_DATA[0]~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \TD_DATA[1]~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \TD_DATA[2]~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \TD_DATA[3]~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \TD_DATA[4]~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \TD_DATA[5]~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \TD_DATA[6]~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \TD_DATA[7]~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \TD_HS~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \TD_VS~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \UART_RTS~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \UART_RXD~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \~ALTERA_ASDO_DATA1~~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \~ALTERA_FLASH_nCE_nCSO~~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL \~ALTERA_DATA0~~ibuf_o\ : std_logic;
|
||
|
|
SIGNAL SW : std_logic_vector(7 DOWNTO 0);
|
||
|
|
|
||
|
|
BEGIN
|
||
|
|
|
||
|
|
ww_devoe <= devoe;
|
||
|
|
ww_devclrn <= devclrn;
|
||
|
|
ww_devpor <= devpor;
|
||
|
|
END structure;
|
||
|
|
|
||
|
|
|
||
|
|
LIBRARY CYCLONEIVE;
|
||
|
|
LIBRARY IEEE;
|
||
|
|
USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
|
||
|
|
USE IEEE.STD_LOGIC_1164.ALL;
|
||
|
|
|
||
|
|
ENTITY EqCmpDemo IS
|
||
|
|
PORT (
|
||
|
|
LEDG : OUT std_logic_vector(0 DOWNTO 0);
|
||
|
|
SW : IN std_logic_vector(7 DOWNTO 0)
|
||
|
|
);
|
||
|
|
END EqCmpDemo;
|
||
|
|
|
||
|
|
-- Design Ports Information
|
||
|
|
-- LEDG[0] => Location: PIN_E21, I/O Standard: 2.5 V, Current Strength: Default
|
||
|
|
-- SW[4] => Location: PIN_AB27, I/O Standard: 2.5 V, Current Strength: Default
|
||
|
|
-- SW[5] => Location: PIN_AC26, I/O Standard: 2.5 V, Current Strength: Default
|
||
|
|
-- SW[1] => Location: PIN_AC28, I/O Standard: 2.5 V, Current Strength: Default
|
||
|
|
-- SW[0] => Location: PIN_AB28, I/O Standard: 2.5 V, Current Strength: Default
|
||
|
|
-- SW[6] => Location: PIN_AD26, I/O Standard: 2.5 V, Current Strength: Default
|
||
|
|
-- SW[7] => Location: PIN_AB26, I/O Standard: 2.5 V, Current Strength: Default
|
||
|
|
-- SW[3] => Location: PIN_AD27, I/O Standard: 2.5 V, Current Strength: Default
|
||
|
|
-- SW[2] => Location: PIN_AC27, I/O Standard: 2.5 V, Current Strength: Default
|
||
|
|
|
||
|
|
|
||
|
|
ARCHITECTURE structure OF EqCmpDemo IS
|
||
|
|
SIGNAL gnd : std_logic := '0';
|
||
|
|
SIGNAL vcc : std_logic := '1';
|
||
|
|
SIGNAL unknown : std_logic := 'X';
|
||
|
|
SIGNAL devoe : std_logic := '1';
|
||
|
|
SIGNAL devclrn : std_logic := '1';
|
||
|
|
SIGNAL devpor : std_logic := '1';
|
||
|
|
SIGNAL ww_devoe : std_logic;
|
||
|
|
SIGNAL ww_devclrn : std_logic;
|
||
|
|
SIGNAL ww_devpor : std_logic;
|
||
|
|
SIGNAL ww_LEDG : std_logic_vector(0 DOWNTO 0);
|
||
|
|
SIGNAL ww_SW : std_logic_vector(7 DOWNTO 0);
|
||
|
|
SIGNAL \LEDG[0]~output_o\ : std_logic;
|
||
|
|
SIGNAL \SW[1]~input_o\ : std_logic;
|
||
|
|
SIGNAL \SW[0]~input_o\ : std_logic;
|
||
|
|
SIGNAL \SW[5]~input_o\ : std_logic;
|
||
|
|
SIGNAL \SW[4]~input_o\ : std_logic;
|
||
|
|
SIGNAL \inst|inst~0_combout\ : std_logic;
|
||
|
|
SIGNAL \SW[7]~input_o\ : std_logic;
|
||
|
|
SIGNAL \SW[6]~input_o\ : std_logic;
|
||
|
|
SIGNAL \SW[3]~input_o\ : std_logic;
|
||
|
|
SIGNAL \SW[2]~input_o\ : std_logic;
|
||
|
|
SIGNAL \inst|inst~1_combout\ : std_logic;
|
||
|
|
SIGNAL \inst|inst~combout\ : std_logic;
|
||
|
|
|
||
|
|
COMPONENT hard_block
|
||
|
|
PORT (
|
||
|
|
devoe : IN std_logic;
|
||
|
|
devclrn : IN std_logic;
|
||
|
|
devpor : IN std_logic);
|
||
|
|
END COMPONENT;
|
||
|
|
|
||
|
|
BEGIN
|
||
|
|
|
||
|
|
LEDG <= ww_LEDG;
|
||
|
|
ww_SW <= SW;
|
||
|
|
ww_devoe <= devoe;
|
||
|
|
ww_devclrn <= devclrn;
|
||
|
|
ww_devpor <= devpor;
|
||
|
|
auto_generated_inst : hard_block
|
||
|
|
PORT MAP (
|
||
|
|
devoe => ww_devoe,
|
||
|
|
devclrn => ww_devclrn,
|
||
|
|
devpor => ww_devpor);
|
||
|
|
|
||
|
|
-- Location: IOOBUF_X107_Y73_N9
|
||
|
|
\LEDG[0]~output\ : cycloneive_io_obuf
|
||
|
|
-- pragma translate_off
|
||
|
|
GENERIC MAP (
|
||
|
|
bus_hold => "false",
|
||
|
|
open_drain_output => "false")
|
||
|
|
-- pragma translate_on
|
||
|
|
PORT MAP (
|
||
|
|
i => \inst|inst~combout\,
|
||
|
|
devoe => ww_devoe,
|
||
|
|
o => \LEDG[0]~output_o\);
|
||
|
|
|
||
|
|
-- Location: IOIBUF_X115_Y14_N1
|
||
|
|
\SW[1]~input\ : cycloneive_io_ibuf
|
||
|
|
-- pragma translate_off
|
||
|
|
GENERIC MAP (
|
||
|
|
bus_hold => "false",
|
||
|
|
simulate_z_as => "z")
|
||
|
|
-- pragma translate_on
|
||
|
|
PORT MAP (
|
||
|
|
i => ww_SW(1),
|
||
|
|
o => \SW[1]~input_o\);
|
||
|
|
|
||
|
|
-- Location: IOIBUF_X115_Y17_N1
|
||
|
|
\SW[0]~input\ : cycloneive_io_ibuf
|
||
|
|
-- pragma translate_off
|
||
|
|
GENERIC MAP (
|
||
|
|
bus_hold => "false",
|
||
|
|
simulate_z_as => "z")
|
||
|
|
-- pragma translate_on
|
||
|
|
PORT MAP (
|
||
|
|
i => ww_SW(0),
|
||
|
|
o => \SW[0]~input_o\);
|
||
|
|
|
||
|
|
-- Location: IOIBUF_X115_Y11_N8
|
||
|
|
\SW[5]~input\ : cycloneive_io_ibuf
|
||
|
|
-- pragma translate_off
|
||
|
|
GENERIC MAP (
|
||
|
|
bus_hold => "false",
|
||
|
|
simulate_z_as => "z")
|
||
|
|
-- pragma translate_on
|
||
|
|
PORT MAP (
|
||
|
|
i => ww_SW(5),
|
||
|
|
o => \SW[5]~input_o\);
|
||
|
|
|
||
|
|
-- Location: IOIBUF_X115_Y18_N8
|
||
|
|
\SW[4]~input\ : cycloneive_io_ibuf
|
||
|
|
-- pragma translate_off
|
||
|
|
GENERIC MAP (
|
||
|
|
bus_hold => "false",
|
||
|
|
simulate_z_as => "z")
|
||
|
|
-- pragma translate_on
|
||
|
|
PORT MAP (
|
||
|
|
i => ww_SW(4),
|
||
|
|
o => \SW[4]~input_o\);
|
||
|
|
|
||
|
|
-- Location: LCCOMB_X114_Y15_N24
|
||
|
|
\inst|inst~0\ : cycloneive_lcell_comb
|
||
|
|
-- Equation(s):
|
||
|
|
-- \inst|inst~0_combout\ = (\SW[1]~input_o\ & (\SW[5]~input_o\ & (\SW[0]~input_o\ $ (!\SW[4]~input_o\)))) # (!\SW[1]~input_o\ & (!\SW[5]~input_o\ & (\SW[0]~input_o\ $ (!\SW[4]~input_o\))))
|
||
|
|
|
||
|
|
-- pragma translate_off
|
||
|
|
GENERIC MAP (
|
||
|
|
lut_mask => "1000010000100001",
|
||
|
|
sum_lutc_input => "datac")
|
||
|
|
-- pragma translate_on
|
||
|
|
PORT MAP (
|
||
|
|
dataa => \SW[1]~input_o\,
|
||
|
|
datab => \SW[0]~input_o\,
|
||
|
|
datac => \SW[5]~input_o\,
|
||
|
|
datad => \SW[4]~input_o\,
|
||
|
|
combout => \inst|inst~0_combout\);
|
||
|
|
|
||
|
|
-- Location: IOIBUF_X115_Y15_N1
|
||
|
|
\SW[7]~input\ : cycloneive_io_ibuf
|
||
|
|
-- pragma translate_off
|
||
|
|
GENERIC MAP (
|
||
|
|
bus_hold => "false",
|
||
|
|
simulate_z_as => "z")
|
||
|
|
-- pragma translate_on
|
||
|
|
PORT MAP (
|
||
|
|
i => ww_SW(7),
|
||
|
|
o => \SW[7]~input_o\);
|
||
|
|
|
||
|
|
-- Location: IOIBUF_X115_Y10_N1
|
||
|
|
\SW[6]~input\ : cycloneive_io_ibuf
|
||
|
|
-- pragma translate_off
|
||
|
|
GENERIC MAP (
|
||
|
|
bus_hold => "false",
|
||
|
|
simulate_z_as => "z")
|
||
|
|
-- pragma translate_on
|
||
|
|
PORT MAP (
|
||
|
|
i => ww_SW(6),
|
||
|
|
o => \SW[6]~input_o\);
|
||
|
|
|
||
|
|
-- Location: IOIBUF_X115_Y13_N8
|
||
|
|
\SW[3]~input\ : cycloneive_io_ibuf
|
||
|
|
-- pragma translate_off
|
||
|
|
GENERIC MAP (
|
||
|
|
bus_hold => "false",
|
||
|
|
simulate_z_as => "z")
|
||
|
|
-- pragma translate_on
|
||
|
|
PORT MAP (
|
||
|
|
i => ww_SW(3),
|
||
|
|
o => \SW[3]~input_o\);
|
||
|
|
|
||
|
|
-- Location: IOIBUF_X115_Y15_N8
|
||
|
|
\SW[2]~input\ : cycloneive_io_ibuf
|
||
|
|
-- pragma translate_off
|
||
|
|
GENERIC MAP (
|
||
|
|
bus_hold => "false",
|
||
|
|
simulate_z_as => "z")
|
||
|
|
-- pragma translate_on
|
||
|
|
PORT MAP (
|
||
|
|
i => ww_SW(2),
|
||
|
|
o => \SW[2]~input_o\);
|
||
|
|
|
||
|
|
-- Location: LCCOMB_X114_Y15_N10
|
||
|
|
\inst|inst~1\ : cycloneive_lcell_comb
|
||
|
|
-- Equation(s):
|
||
|
|
-- \inst|inst~1_combout\ = (\SW[7]~input_o\ & (\SW[3]~input_o\ & (\SW[6]~input_o\ $ (!\SW[2]~input_o\)))) # (!\SW[7]~input_o\ & (!\SW[3]~input_o\ & (\SW[6]~input_o\ $ (!\SW[2]~input_o\))))
|
||
|
|
|
||
|
|
-- pragma translate_off
|
||
|
|
GENERIC MAP (
|
||
|
|
lut_mask => "1000010000100001",
|
||
|
|
sum_lutc_input => "datac")
|
||
|
|
-- pragma translate_on
|
||
|
|
PORT MAP (
|
||
|
|
dataa => \SW[7]~input_o\,
|
||
|
|
datab => \SW[6]~input_o\,
|
||
|
|
datac => \SW[3]~input_o\,
|
||
|
|
datad => \SW[2]~input_o\,
|
||
|
|
combout => \inst|inst~1_combout\);
|
||
|
|
|
||
|
|
-- Location: LCCOMB_X114_Y15_N28
|
||
|
|
\inst|inst\ : cycloneive_lcell_comb
|
||
|
|
-- Equation(s):
|
||
|
|
-- \inst|inst~combout\ = (\inst|inst~0_combout\ & \inst|inst~1_combout\)
|
||
|
|
|
||
|
|
-- pragma translate_off
|
||
|
|
GENERIC MAP (
|
||
|
|
lut_mask => "1100110000000000",
|
||
|
|
sum_lutc_input => "datac")
|
||
|
|
-- pragma translate_on
|
||
|
|
PORT MAP (
|
||
|
|
datab => \inst|inst~0_combout\,
|
||
|
|
datad => \inst|inst~1_combout\,
|
||
|
|
combout => \inst|inst~combout\);
|
||
|
|
|
||
|
|
ww_LEDG(0) <= \LEDG[0]~output_o\;
|
||
|
|
END structure;
|
||
|
|
|
||
|
|
|