uaveiro-leci/1ano/isd/quartus-projects/Teste/simulation/qsim/Waveform.vwf.vt

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// Copyright (C) 2020 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions
// and other software and tools, and any partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel FPGA IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Intel and sold by Intel or its authorized distributors. Please
// refer to the applicable agreement for further details, at
// https://fpgasoftware.intel.com/eula.
// *****************************************************************************
// This file contains a Verilog test bench with test vectors .The test vectors
// are exported from a vector file in the Quartus Waveform Editor and apply to
// the top level entity of the current Quartus project .The user can use this
// testbench to simulate his design using a third-party simulation tool .
// *****************************************************************************
// Generated on "12/02/2022 12:28:31"
// Verilog Test Bench (with test vectors) for design : Teste1
//
// Simulation tool : 3rd Party
//
`timescale 1 ps/ 1 ps
module Teste1_vlg_vec_tst();
// constants
// general purpose registers
reg [2:0] S;
reg X0;
reg X1;
reg X2;
reg X3;
reg X4;
reg X5;
reg X6;
reg X7;
// wires
wire Y;
// assign statements (if any)
Teste1 i1 (
// port map - connection between master ports and signals/registers
.S(S),
.X0(X0),
.X1(X1),
.X2(X2),
.X3(X3),
.X4(X4),
.X5(X5),
.X6(X6),
.X7(X7),
.Y(Y)
);
initial
begin
#1000000 $finish;
end
// S[ 2 ]
initial
begin
S[2] = 1'b0;
S[2] = #400000 1'b1;
S[2] = #400000 1'b0;
end
// S[ 1 ]
initial
begin
repeat(2)
begin
S[1] = 1'b0;
S[1] = #200000 1'b1;
# 200000;
end
S[1] = 1'b0;
end
// S[ 0 ]
always
begin
S[0] = 1'b0;
S[0] = #100000 1'b1;
#100000;
end
// X0
always
begin
X0 = 1'b0;
X0 = #3125 1'b1;
#3125;
end
// X1
always
begin
X1 = 1'b0;
X1 = #6250 1'b1;
#6250;
end
// X2
always
begin
X2 = 1'b0;
X2 = #12500 1'b1;
#12500;
end
// X3
always
begin
X3 = 1'b0;
X3 = #25000 1'b1;
#25000;
end
// X4
always
begin
X4 = 1'b0;
X4 = #50000 1'b1;
#50000;
end
// X5
always
begin
X5 = 1'b0;
X5 = #100000 1'b1;
#100000;
end
// X6
initial
begin
repeat(2)
begin
X6 = 1'b0;
X6 = #200000 1'b1;
# 200000;
end
X6 = 1'b0;
end
// X7
initial
begin
X7 = 1'b0;
X7 = #400000 1'b1;
X7 = #400000 1'b0;
end
endmodule