570 lines
16 KiB
Plaintext
570 lines
16 KiB
Plaintext
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// Copyright (C) 2020 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions
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// and other software and tools, and any partner logic
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Intel Program License
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// Subscription Agreement, the Intel Quartus Prime License Agreement,
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// the Intel FPGA IP License Agreement, or other applicable license
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// agreement, including, without limitation, that your use is for
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// the sole purpose of programming logic devices manufactured by
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// Intel and sold by Intel or its authorized distributors. Please
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// refer to the applicable agreement for further details, at
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// https://fpgasoftware.intel.com/eula.
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// VENDOR "Altera"
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// PROGRAM "Quartus Prime"
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// VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
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// DATE "11/18/2022 13:03:41"
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//
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// Device: Altera EP4CE6E22C6 Package TQFP144
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//
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//
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// This Verilog file should be used for ModelSim-Altera (Verilog) only
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//
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`timescale 1 ps/ 1 ps
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module Mux16_1 (
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pin_name1,
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Sel4,
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Sel3,
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Sel2,
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Sel1,
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I0,
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I1,
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I2,
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I3,
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I4,
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I5,
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I6,
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I7,
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I8,
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I9,
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I10,
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I11,
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I12,
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I13,
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I14,
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I15);
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output pin_name1;
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input Sel4;
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input Sel3;
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input Sel2;
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input Sel1;
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input I0;
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input I1;
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input I2;
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input I3;
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input I4;
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input I5;
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input I6;
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input I7;
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input I8;
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input I9;
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input I10;
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input I11;
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input I12;
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input I13;
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input I14;
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input I15;
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// Design Ports Information
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// pin_name1 => Location: PIN_76, I/O Standard: 2.5 V, Current Strength: Default
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// I10 => Location: PIN_46, I/O Standard: 2.5 V, Current Strength: Default
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// Sel2 => Location: PIN_80, I/O Standard: 2.5 V, Current Strength: Default
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// I9 => Location: PIN_65, I/O Standard: 2.5 V, Current Strength: Default
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// Sel1 => Location: PIN_112, I/O Standard: 2.5 V, Current Strength: Default
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// I8 => Location: PIN_68, I/O Standard: 2.5 V, Current Strength: Default
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// I11 => Location: PIN_87, I/O Standard: 2.5 V, Current Strength: Default
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// Sel4 => Location: PIN_121, I/O Standard: 2.5 V, Current Strength: Default
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// I5 => Location: PIN_85, I/O Standard: 2.5 V, Current Strength: Default
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// I6 => Location: PIN_86, I/O Standard: 2.5 V, Current Strength: Default
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// I4 => Location: PIN_69, I/O Standard: 2.5 V, Current Strength: Default
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// I7 => Location: PIN_88, I/O Standard: 2.5 V, Current Strength: Default
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// Sel3 => Location: PIN_89, I/O Standard: 2.5 V, Current Strength: Default
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// I2 => Location: PIN_74, I/O Standard: 2.5 V, Current Strength: Default
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// I1 => Location: PIN_90, I/O Standard: 2.5 V, Current Strength: Default
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// I0 => Location: PIN_91, I/O Standard: 2.5 V, Current Strength: Default
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// I3 => Location: PIN_84, I/O Standard: 2.5 V, Current Strength: Default
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// I13 => Location: PIN_66, I/O Standard: 2.5 V, Current Strength: Default
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// I14 => Location: PIN_120, I/O Standard: 2.5 V, Current Strength: Default
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// I12 => Location: PIN_83, I/O Standard: 2.5 V, Current Strength: Default
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// I15 => Location: PIN_77, I/O Standard: 2.5 V, Current Strength: Default
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wire gnd;
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wire vcc;
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wire unknown;
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assign gnd = 1'b0;
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assign vcc = 1'b1;
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assign unknown = 1'bx;
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tri1 devclrn;
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tri1 devpor;
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tri1 devoe;
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wire \pin_name1~output_o ;
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wire \I14~input_o ;
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wire \Sel2~input_o ;
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wire \Sel1~input_o ;
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wire \I12~input_o ;
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wire \inst14|inst2~7_combout ;
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wire \I13~input_o ;
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wire \I15~input_o ;
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wire \inst14|inst2~8_combout ;
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wire \I5~input_o ;
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wire \I6~input_o ;
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wire \I4~input_o ;
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wire \inst14|inst2~2_combout ;
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wire \I7~input_o ;
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wire \inst14|inst2~3_combout ;
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wire \Sel4~input_o ;
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wire \Sel3~input_o ;
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wire \I2~input_o ;
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wire \I1~input_o ;
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wire \I0~input_o ;
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wire \inst14|inst2~4_combout ;
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wire \I3~input_o ;
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wire \inst14|inst2~5_combout ;
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wire \inst14|inst2~6_combout ;
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wire \I10~input_o ;
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wire \I8~input_o ;
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wire \I9~input_o ;
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wire \inst14|inst2~0_combout ;
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wire \I11~input_o ;
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wire \inst14|inst2~1_combout ;
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wire \inst14|inst2~9_combout ;
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hard_block auto_generated_inst(
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.devpor(devpor),
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.devclrn(devclrn),
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.devoe(devoe));
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// Location: IOOBUF_X34_Y4_N23
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cycloneive_io_obuf \pin_name1~output (
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.i(\inst14|inst2~9_combout ),
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.oe(vcc),
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.seriesterminationcontrol(16'b0000000000000000),
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.devoe(devoe),
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.o(\pin_name1~output_o ),
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.obar());
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// synopsys translate_off
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defparam \pin_name1~output .bus_hold = "false";
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defparam \pin_name1~output .open_drain_output = "false";
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// synopsys translate_on
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// Location: IOIBUF_X23_Y24_N8
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cycloneive_io_ibuf \I14~input (
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.i(I14),
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.ibar(gnd),
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.o(\I14~input_o ));
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// synopsys translate_off
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defparam \I14~input .bus_hold = "false";
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defparam \I14~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: IOIBUF_X34_Y7_N8
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cycloneive_io_ibuf \Sel2~input (
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.i(Sel2),
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.ibar(gnd),
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.o(\Sel2~input_o ));
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// synopsys translate_off
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defparam \Sel2~input .bus_hold = "false";
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defparam \Sel2~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: IOIBUF_X28_Y24_N1
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cycloneive_io_ibuf \Sel1~input (
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.i(Sel1),
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.ibar(gnd),
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.o(\Sel1~input_o ));
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// synopsys translate_off
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defparam \Sel1~input .bus_hold = "false";
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defparam \Sel1~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: IOIBUF_X34_Y9_N22
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cycloneive_io_ibuf \I12~input (
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.i(I12),
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.ibar(gnd),
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.o(\I12~input_o ));
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// synopsys translate_off
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defparam \I12~input .bus_hold = "false";
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defparam \I12~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: LCCOMB_X28_Y8_N12
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cycloneive_lcell_comb \inst14|inst2~7 (
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// Equation(s):
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// \inst14|inst2~7_combout = (\Sel2~input_o & ((\I14~input_o ) # ((\Sel1~input_o )))) # (!\Sel2~input_o & (((!\Sel1~input_o & \I12~input_o ))))
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.dataa(\I14~input_o ),
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.datab(\Sel2~input_o ),
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.datac(\Sel1~input_o ),
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.datad(\I12~input_o ),
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.cin(gnd),
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.combout(\inst14|inst2~7_combout ),
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.cout());
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// synopsys translate_off
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defparam \inst14|inst2~7 .lut_mask = 16'hCBC8;
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defparam \inst14|inst2~7 .sum_lutc_input = "datac";
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// synopsys translate_on
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// Location: IOIBUF_X28_Y0_N1
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cycloneive_io_ibuf \I13~input (
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.i(I13),
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.ibar(gnd),
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.o(\I13~input_o ));
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// synopsys translate_off
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defparam \I13~input .bus_hold = "false";
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defparam \I13~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: IOIBUF_X34_Y4_N15
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cycloneive_io_ibuf \I15~input (
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.i(I15),
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.ibar(gnd),
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.o(\I15~input_o ));
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// synopsys translate_off
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defparam \I15~input .bus_hold = "false";
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defparam \I15~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: LCCOMB_X28_Y8_N6
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cycloneive_lcell_comb \inst14|inst2~8 (
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// Equation(s):
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// \inst14|inst2~8_combout = (\inst14|inst2~7_combout & (((\I15~input_o )) # (!\Sel1~input_o ))) # (!\inst14|inst2~7_combout & (\Sel1~input_o & (\I13~input_o )))
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.dataa(\inst14|inst2~7_combout ),
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.datab(\Sel1~input_o ),
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.datac(\I13~input_o ),
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.datad(\I15~input_o ),
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.cin(gnd),
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.combout(\inst14|inst2~8_combout ),
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.cout());
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// synopsys translate_off
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defparam \inst14|inst2~8 .lut_mask = 16'hEA62;
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defparam \inst14|inst2~8 .sum_lutc_input = "datac";
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// synopsys translate_on
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// Location: IOIBUF_X34_Y9_N8
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cycloneive_io_ibuf \I5~input (
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.i(I5),
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.ibar(gnd),
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.o(\I5~input_o ));
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// synopsys translate_off
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defparam \I5~input .bus_hold = "false";
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defparam \I5~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: IOIBUF_X34_Y9_N1
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cycloneive_io_ibuf \I6~input (
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.i(I6),
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.ibar(gnd),
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.o(\I6~input_o ));
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// synopsys translate_off
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defparam \I6~input .bus_hold = "false";
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defparam \I6~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: IOIBUF_X30_Y0_N1
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cycloneive_io_ibuf \I4~input (
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.i(I4),
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.ibar(gnd),
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.o(\I4~input_o ));
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// synopsys translate_off
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defparam \I4~input .bus_hold = "false";
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defparam \I4~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: LCCOMB_X28_Y8_N20
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cycloneive_lcell_comb \inst14|inst2~2 (
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// Equation(s):
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// \inst14|inst2~2_combout = (\Sel1~input_o & (((\Sel2~input_o )))) # (!\Sel1~input_o & ((\Sel2~input_o & (\I6~input_o )) # (!\Sel2~input_o & ((\I4~input_o )))))
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.dataa(\I6~input_o ),
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.datab(\I4~input_o ),
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.datac(\Sel1~input_o ),
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.datad(\Sel2~input_o ),
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.cin(gnd),
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.combout(\inst14|inst2~2_combout ),
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.cout());
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// synopsys translate_off
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defparam \inst14|inst2~2 .lut_mask = 16'hFA0C;
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defparam \inst14|inst2~2 .sum_lutc_input = "datac";
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// synopsys translate_on
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// Location: IOIBUF_X34_Y12_N22
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cycloneive_io_ibuf \I7~input (
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.i(I7),
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.ibar(gnd),
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.o(\I7~input_o ));
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// synopsys translate_off
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defparam \I7~input .bus_hold = "false";
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defparam \I7~input .simulate_z_as = "z";
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// synopsys translate_on
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// Location: LCCOMB_X28_Y8_N22
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cycloneive_lcell_comb \inst14|inst2~3 (
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// Equation(s):
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// \inst14|inst2~3_combout = (\inst14|inst2~2_combout & (((\I7~input_o ) # (!\Sel1~input_o )))) # (!\inst14|inst2~2_combout & (\I5~input_o & (\Sel1~input_o )))
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.dataa(\I5~input_o ),
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.datab(\inst14|inst2~2_combout ),
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.datac(\Sel1~input_o ),
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.datad(\I7~input_o ),
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.cin(gnd),
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.combout(\inst14|inst2~3_combout ),
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.cout());
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// synopsys translate_off
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defparam \inst14|inst2~3 .lut_mask = 16'hEC2C;
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defparam \inst14|inst2~3 .sum_lutc_input = "datac";
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// synopsys translate_on
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// Location: IOIBUF_X23_Y24_N15
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cycloneive_io_ibuf \Sel4~input (
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.i(Sel4),
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.ibar(gnd),
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.o(\Sel4~input_o ));
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// synopsys translate_off
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defparam \Sel4~input .bus_hold = "false";
|
||
|
|
defparam \Sel4~input .simulate_z_as = "z";
|
||
|
|
// synopsys translate_on
|
||
|
|
|
||
|
|
// Location: IOIBUF_X34_Y12_N15
|
||
|
|
cycloneive_io_ibuf \Sel3~input (
|
||
|
|
.i(Sel3),
|
||
|
|
.ibar(gnd),
|
||
|
|
.o(\Sel3~input_o ));
|
||
|
|
// synopsys translate_off
|
||
|
|
defparam \Sel3~input .bus_hold = "false";
|
||
|
|
defparam \Sel3~input .simulate_z_as = "z";
|
||
|
|
// synopsys translate_on
|
||
|
|
|
||
|
|
// Location: IOIBUF_X34_Y2_N15
|
||
|
|
cycloneive_io_ibuf \I2~input (
|
||
|
|
.i(I2),
|
||
|
|
.ibar(gnd),
|
||
|
|
.o(\I2~input_o ));
|
||
|
|
// synopsys translate_off
|
||
|
|
defparam \I2~input .bus_hold = "false";
|
||
|
|
defparam \I2~input .simulate_z_as = "z";
|
||
|
|
// synopsys translate_on
|
||
|
|
|
||
|
|
// Location: IOIBUF_X34_Y12_N8
|
||
|
|
cycloneive_io_ibuf \I1~input (
|
||
|
|
.i(I1),
|
||
|
|
.ibar(gnd),
|
||
|
|
.o(\I1~input_o ));
|
||
|
|
// synopsys translate_off
|
||
|
|
defparam \I1~input .bus_hold = "false";
|
||
|
|
defparam \I1~input .simulate_z_as = "z";
|
||
|
|
// synopsys translate_on
|
||
|
|
|
||
|
|
// Location: IOIBUF_X34_Y12_N1
|
||
|
|
cycloneive_io_ibuf \I0~input (
|
||
|
|
.i(I0),
|
||
|
|
.ibar(gnd),
|
||
|
|
.o(\I0~input_o ));
|
||
|
|
// synopsys translate_off
|
||
|
|
defparam \I0~input .bus_hold = "false";
|
||
|
|
defparam \I0~input .simulate_z_as = "z";
|
||
|
|
// synopsys translate_on
|
||
|
|
|
||
|
|
// Location: LCCOMB_X33_Y8_N8
|
||
|
|
cycloneive_lcell_comb \inst14|inst2~4 (
|
||
|
|
// Equation(s):
|
||
|
|
// \inst14|inst2~4_combout = (\Sel2~input_o & (((\Sel1~input_o )))) # (!\Sel2~input_o & ((\Sel1~input_o & (\I1~input_o )) # (!\Sel1~input_o & ((\I0~input_o )))))
|
||
|
|
|
||
|
|
.dataa(\I1~input_o ),
|
||
|
|
.datab(\Sel2~input_o ),
|
||
|
|
.datac(\Sel1~input_o ),
|
||
|
|
.datad(\I0~input_o ),
|
||
|
|
.cin(gnd),
|
||
|
|
.combout(\inst14|inst2~4_combout ),
|
||
|
|
.cout());
|
||
|
|
// synopsys translate_off
|
||
|
|
defparam \inst14|inst2~4 .lut_mask = 16'hE3E0;
|
||
|
|
defparam \inst14|inst2~4 .sum_lutc_input = "datac";
|
||
|
|
// synopsys translate_on
|
||
|
|
|
||
|
|
// Location: IOIBUF_X34_Y9_N15
|
||
|
|
cycloneive_io_ibuf \I3~input (
|
||
|
|
.i(I3),
|
||
|
|
.ibar(gnd),
|
||
|
|
.o(\I3~input_o ));
|
||
|
|
// synopsys translate_off
|
||
|
|
defparam \I3~input .bus_hold = "false";
|
||
|
|
defparam \I3~input .simulate_z_as = "z";
|
||
|
|
// synopsys translate_on
|
||
|
|
|
||
|
|
// Location: LCCOMB_X28_Y8_N24
|
||
|
|
cycloneive_lcell_comb \inst14|inst2~5 (
|
||
|
|
// Equation(s):
|
||
|
|
// \inst14|inst2~5_combout = (\Sel2~input_o & ((\inst14|inst2~4_combout & ((\I3~input_o ))) # (!\inst14|inst2~4_combout & (\I2~input_o )))) # (!\Sel2~input_o & (((\inst14|inst2~4_combout ))))
|
||
|
|
|
||
|
|
.dataa(\I2~input_o ),
|
||
|
|
.datab(\Sel2~input_o ),
|
||
|
|
.datac(\inst14|inst2~4_combout ),
|
||
|
|
.datad(\I3~input_o ),
|
||
|
|
.cin(gnd),
|
||
|
|
.combout(\inst14|inst2~5_combout ),
|
||
|
|
.cout());
|
||
|
|
// synopsys translate_off
|
||
|
|
defparam \inst14|inst2~5 .lut_mask = 16'hF838;
|
||
|
|
defparam \inst14|inst2~5 .sum_lutc_input = "datac";
|
||
|
|
// synopsys translate_on
|
||
|
|
|
||
|
|
// Location: LCCOMB_X28_Y8_N18
|
||
|
|
cycloneive_lcell_comb \inst14|inst2~6 (
|
||
|
|
// Equation(s):
|
||
|
|
// \inst14|inst2~6_combout = (\Sel4~input_o & (((\Sel3~input_o )))) # (!\Sel4~input_o & ((\Sel3~input_o & (\inst14|inst2~3_combout )) # (!\Sel3~input_o & ((\inst14|inst2~5_combout )))))
|
||
|
|
|
||
|
|
.dataa(\inst14|inst2~3_combout ),
|
||
|
|
.datab(\Sel4~input_o ),
|
||
|
|
.datac(\Sel3~input_o ),
|
||
|
|
.datad(\inst14|inst2~5_combout ),
|
||
|
|
.cin(gnd),
|
||
|
|
.combout(\inst14|inst2~6_combout ),
|
||
|
|
.cout());
|
||
|
|
// synopsys translate_off
|
||
|
|
defparam \inst14|inst2~6 .lut_mask = 16'hE3E0;
|
||
|
|
defparam \inst14|inst2~6 .sum_lutc_input = "datac";
|
||
|
|
// synopsys translate_on
|
||
|
|
|
||
|
|
// Location: IOIBUF_X7_Y0_N1
|
||
|
|
cycloneive_io_ibuf \I10~input (
|
||
|
|
.i(I10),
|
||
|
|
.ibar(gnd),
|
||
|
|
.o(\I10~input_o ));
|
||
|
|
// synopsys translate_off
|
||
|
|
defparam \I10~input .bus_hold = "false";
|
||
|
|
defparam \I10~input .simulate_z_as = "z";
|
||
|
|
// synopsys translate_on
|
||
|
|
|
||
|
|
// Location: IOIBUF_X30_Y0_N8
|
||
|
|
cycloneive_io_ibuf \I8~input (
|
||
|
|
.i(I8),
|
||
|
|
.ibar(gnd),
|
||
|
|
.o(\I8~input_o ));
|
||
|
|
// synopsys translate_off
|
||
|
|
defparam \I8~input .bus_hold = "false";
|
||
|
|
defparam \I8~input .simulate_z_as = "z";
|
||
|
|
// synopsys translate_on
|
||
|
|
|
||
|
|
// Location: IOIBUF_X28_Y0_N22
|
||
|
|
cycloneive_io_ibuf \I9~input (
|
||
|
|
.i(I9),
|
||
|
|
.ibar(gnd),
|
||
|
|
.o(\I9~input_o ));
|
||
|
|
// synopsys translate_off
|
||
|
|
defparam \I9~input .bus_hold = "false";
|
||
|
|
defparam \I9~input .simulate_z_as = "z";
|
||
|
|
// synopsys translate_on
|
||
|
|
|
||
|
|
// Location: LCCOMB_X28_Y8_N0
|
||
|
|
cycloneive_lcell_comb \inst14|inst2~0 (
|
||
|
|
// Equation(s):
|
||
|
|
// \inst14|inst2~0_combout = (\Sel1~input_o & (((\I9~input_o ) # (\Sel2~input_o )))) # (!\Sel1~input_o & (\I8~input_o & ((!\Sel2~input_o ))))
|
||
|
|
|
||
|
|
.dataa(\I8~input_o ),
|
||
|
|
.datab(\Sel1~input_o ),
|
||
|
|
.datac(\I9~input_o ),
|
||
|
|
.datad(\Sel2~input_o ),
|
||
|
|
.cin(gnd),
|
||
|
|
.combout(\inst14|inst2~0_combout ),
|
||
|
|
.cout());
|
||
|
|
// synopsys translate_off
|
||
|
|
defparam \inst14|inst2~0 .lut_mask = 16'hCCE2;
|
||
|
|
defparam \inst14|inst2~0 .sum_lutc_input = "datac";
|
||
|
|
// synopsys translate_on
|
||
|
|
|
||
|
|
// Location: IOIBUF_X34_Y10_N8
|
||
|
|
cycloneive_io_ibuf \I11~input (
|
||
|
|
.i(I11),
|
||
|
|
.ibar(gnd),
|
||
|
|
.o(\I11~input_o ));
|
||
|
|
// synopsys translate_off
|
||
|
|
defparam \I11~input .bus_hold = "false";
|
||
|
|
defparam \I11~input .simulate_z_as = "z";
|
||
|
|
// synopsys translate_on
|
||
|
|
|
||
|
|
// Location: LCCOMB_X28_Y8_N10
|
||
|
|
cycloneive_lcell_comb \inst14|inst2~1 (
|
||
|
|
// Equation(s):
|
||
|
|
// \inst14|inst2~1_combout = (\inst14|inst2~0_combout & (((\I11~input_o ) # (!\Sel2~input_o )))) # (!\inst14|inst2~0_combout & (\I10~input_o & ((\Sel2~input_o ))))
|
||
|
|
|
||
|
|
.dataa(\I10~input_o ),
|
||
|
|
.datab(\inst14|inst2~0_combout ),
|
||
|
|
.datac(\I11~input_o ),
|
||
|
|
.datad(\Sel2~input_o ),
|
||
|
|
.cin(gnd),
|
||
|
|
.combout(\inst14|inst2~1_combout ),
|
||
|
|
.cout());
|
||
|
|
// synopsys translate_off
|
||
|
|
defparam \inst14|inst2~1 .lut_mask = 16'hE2CC;
|
||
|
|
defparam \inst14|inst2~1 .sum_lutc_input = "datac";
|
||
|
|
// synopsys translate_on
|
||
|
|
|
||
|
|
// Location: LCCOMB_X28_Y8_N8
|
||
|
|
cycloneive_lcell_comb \inst14|inst2~9 (
|
||
|
|
// Equation(s):
|
||
|
|
// \inst14|inst2~9_combout = (\inst14|inst2~6_combout & ((\inst14|inst2~8_combout ) # ((!\Sel4~input_o )))) # (!\inst14|inst2~6_combout & (((\Sel4~input_o & \inst14|inst2~1_combout ))))
|
||
|
|
|
||
|
|
.dataa(\inst14|inst2~8_combout ),
|
||
|
|
.datab(\inst14|inst2~6_combout ),
|
||
|
|
.datac(\Sel4~input_o ),
|
||
|
|
.datad(\inst14|inst2~1_combout ),
|
||
|
|
.cin(gnd),
|
||
|
|
.combout(\inst14|inst2~9_combout ),
|
||
|
|
.cout());
|
||
|
|
// synopsys translate_off
|
||
|
|
defparam \inst14|inst2~9 .lut_mask = 16'hBC8C;
|
||
|
|
defparam \inst14|inst2~9 .sum_lutc_input = "datac";
|
||
|
|
// synopsys translate_on
|
||
|
|
|
||
|
|
assign pin_name1 = \pin_name1~output_o ;
|
||
|
|
|
||
|
|
endmodule
|
||
|
|
|
||
|
|
module hard_block (
|
||
|
|
|
||
|
|
devpor,
|
||
|
|
devclrn,
|
||
|
|
devoe);
|
||
|
|
|
||
|
|
// Design Ports Information
|
||
|
|
// ~ALTERA_ASDO_DATA1~ => Location: PIN_6, I/O Standard: 2.5 V, Current Strength: Default
|
||
|
|
// ~ALTERA_FLASH_nCE_nCSO~ => Location: PIN_8, I/O Standard: 2.5 V, Current Strength: Default
|
||
|
|
// ~ALTERA_DCLK~ => Location: PIN_12, I/O Standard: 2.5 V, Current Strength: Default
|
||
|
|
// ~ALTERA_DATA0~ => Location: PIN_13, I/O Standard: 2.5 V, Current Strength: Default
|
||
|
|
// ~ALTERA_nCEO~ => Location: PIN_101, I/O Standard: 2.5 V, Current Strength: 8mA
|
||
|
|
|
||
|
|
input devpor;
|
||
|
|
input devclrn;
|
||
|
|
input devoe;
|
||
|
|
|
||
|
|
wire gnd;
|
||
|
|
wire vcc;
|
||
|
|
wire unknown;
|
||
|
|
|
||
|
|
assign gnd = 1'b0;
|
||
|
|
assign vcc = 1'b1;
|
||
|
|
assign unknown = 1'bx;
|
||
|
|
|
||
|
|
wire \~ALTERA_ASDO_DATA1~~padout ;
|
||
|
|
wire \~ALTERA_FLASH_nCE_nCSO~~padout ;
|
||
|
|
wire \~ALTERA_DATA0~~padout ;
|
||
|
|
wire \~ALTERA_ASDO_DATA1~~ibuf_o ;
|
||
|
|
wire \~ALTERA_FLASH_nCE_nCSO~~ibuf_o ;
|
||
|
|
wire \~ALTERA_DATA0~~ibuf_o ;
|
||
|
|
|
||
|
|
|
||
|
|
endmodule
|