42 lines
880 B
VHDL
42 lines
880 B
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.NUMERIC_STD.all;
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entity Counter is
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port
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(
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clk : in std_logic;
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reset : in std_logic;
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count : out std_logic_vector(3 downto 0)
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);
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end Counter;
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architecture Behavioral of Counter is
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signal up : std_logic := '1';
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signal s_count : unsigned(3 downto 0) := to_unsigned(0, 4);
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begin
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process(clk, reset)
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begin
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if (reset = '1') then
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s_count <= to_unsigned(0, 4);
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up <= '1';
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elsif (rising_edge(clk)) then
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if (up = '1') then
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if (std_logic_vector(s_count) = "1111") then
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s_count <= s_count - 1;
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up <= '0';
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else
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s_count <= s_count + 1;
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end if;
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else
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if (std_logic_vector(s_count) = "0000") then
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s_count <= s_count + 1;
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up <= '1';
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else
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s_count <= s_count - 1;
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end if;
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end if;
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end if;
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end process;
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count <= std_logic_vector(s_count);
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end Behavioral;
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