144 lines
12 KiB
Plaintext
144 lines
12 KiB
Plaintext
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vendor_name = ModelSim
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source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/ALU4.vhd
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source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/ALUDemo.bdf
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source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_b.vhd
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source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_p.vhd
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source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_b.vhd
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source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_p.vhd
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source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/megafunctions/lpm_divide.tdf
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source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/megafunctions/abs_divider.inc
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source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/megafunctions/sign_div_unsign.inc
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source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/megafunctions/aglobal201.inc
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source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/megafunctions/cbx.lst
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source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/db/lpm_divide_i9m.tdf
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source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/db/sign_div_unsign_7kh.tdf
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source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/db/alt_u_div_24f.tdf
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source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/db/add_sub_7pc.tdf
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source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/db/add_sub_8pc.tdf
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source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/megafunctions/lpm_mult.tdf
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source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/megafunctions/lpm_add_sub.inc
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source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/megafunctions/multcore.inc
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source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/megafunctions/bypassff.inc
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source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/megafunctions/altshift.inc
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source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/db/mult_j8t.tdf
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source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/db/lpm_divide_fhm.tdf
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design_name = hard_block
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design_name = ALU4
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instance = comp, \r[0]~output\, r[0]~output, ALU4, 1
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instance = comp, \r[1]~output\, r[1]~output, ALU4, 1
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instance = comp, \r[2]~output\, r[2]~output, ALU4, 1
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instance = comp, \r[3]~output\, r[3]~output, ALU4, 1
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instance = comp, \m[0]~output\, m[0]~output, ALU4, 1
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instance = comp, \m[1]~output\, m[1]~output, ALU4, 1
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instance = comp, \m[2]~output\, m[2]~output, ALU4, 1
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instance = comp, \m[3]~output\, m[3]~output, ALU4, 1
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instance = comp, \a[0]~input\, a[0]~input, ALU4, 1
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instance = comp, \b[1]~input\, b[1]~input, ALU4, 1
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instance = comp, \b[0]~input\, b[0]~input, ALU4, 1
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instance = comp, \Mult0|auto_generated|le3a[0]\, Mult0|auto_generated|le3a[0], ALU4, 1
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instance = comp, \Mult0|auto_generated|op_3~0\, Mult0|auto_generated|op_3~0, ALU4, 1
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instance = comp, \op[0]~input\, op[0]~input, ALU4, 1
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instance = comp, \Add0~0\, Add0~0, ALU4, 1
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instance = comp, \Add0~2\, Add0~2, ALU4, 1
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instance = comp, \Add0~3\, Add0~3, ALU4, 1
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instance = comp, \op[2]~input\, op[2]~input, ALU4, 1
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instance = comp, \op[1]~input\, op[1]~input, ALU4, 1
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instance = comp, \Mux3~4\, Mux3~4, ALU4, 1
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instance = comp, \Mux3~3\, Mux3~3, ALU4, 1
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instance = comp, \Mux3~5\, Mux3~5, ALU4, 1
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instance = comp, \b[2]~input\, b[2]~input, ALU4, 1
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instance = comp, \a[2]~input\, a[2]~input, ALU4, 1
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instance = comp, \Mod0|auto_generated|divider|divider|StageOut[5]~0\, Mod0|auto_generated|divider|divider|StageOut[5]~0, ALU4, 1
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instance = comp, \a[3]~input\, a[3]~input, ALU4, 1
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instance = comp, \b[3]~input\, b[3]~input, ALU4, 1
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instance = comp, \Mod0|auto_generated|divider|divider|StageOut[5]~1\, Mod0|auto_generated|divider|divider|StageOut[5]~1, ALU4, 1
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instance = comp, \Mod0|auto_generated|divider|divider|selnose[5]~0\, Mod0|auto_generated|divider|divider|selnose[5]~0, ALU4, 1
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instance = comp, \Mod0|auto_generated|divider|divider|StageOut[4]~2\, Mod0|auto_generated|divider|divider|StageOut[4]~2, ALU4, 1
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instance = comp, \a[1]~input\, a[1]~input, ALU4, 1
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instance = comp, \Div0|auto_generated|divider|divider|add_sub_2_result_int[0]~0\, Div0|auto_generated|divider|divider|add_sub_2_result_int[0]~0, ALU4, 1
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instance = comp, \Div0|auto_generated|divider|divider|add_sub_2_result_int[1]~2\, Div0|auto_generated|divider|divider|add_sub_2_result_int[1]~2, ALU4, 1
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instance = comp, \Div0|auto_generated|divider|divider|add_sub_2_result_int[2]~4\, Div0|auto_generated|divider|divider|add_sub_2_result_int[2]~4, ALU4, 1
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instance = comp, \Div0|auto_generated|divider|divider|add_sub_2_result_int[3]~6\, Div0|auto_generated|divider|divider|add_sub_2_result_int[3]~6, ALU4, 1
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instance = comp, \Div0|auto_generated|divider|divider|StageOut[10]~0\, Div0|auto_generated|divider|divider|StageOut[10]~0, ALU4, 1
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instance = comp, \Div0|auto_generated|divider|divider|StageOut[9]~1\, Div0|auto_generated|divider|divider|StageOut[9]~1, ALU4, 1
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instance = comp, \Div0|auto_generated|divider|divider|StageOut[8]~2\, Div0|auto_generated|divider|divider|StageOut[8]~2, ALU4, 1
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instance = comp, \Div0|auto_generated|divider|divider|add_sub_3_result_int[0]~1\, Div0|auto_generated|divider|divider|add_sub_3_result_int[0]~1, ALU4, 1
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instance = comp, \Div0|auto_generated|divider|divider|add_sub_3_result_int[1]~3\, Div0|auto_generated|divider|divider|add_sub_3_result_int[1]~3, ALU4, 1
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instance = comp, \Div0|auto_generated|divider|divider|add_sub_3_result_int[2]~5\, Div0|auto_generated|divider|divider|add_sub_3_result_int[2]~5, ALU4, 1
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instance = comp, \Div0|auto_generated|divider|divider|add_sub_3_result_int[3]~7\, Div0|auto_generated|divider|divider|add_sub_3_result_int[3]~7, ALU4, 1
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instance = comp, \Div0|auto_generated|divider|divider|add_sub_3_result_int[4]~8\, Div0|auto_generated|divider|divider|add_sub_3_result_int[4]~8, ALU4, 1
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instance = comp, \Mod0|auto_generated|divider|divider|add_sub_3_result_int[0]~0\, Mod0|auto_generated|divider|divider|add_sub_3_result_int[0]~0, ALU4, 1
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instance = comp, \Mod0|auto_generated|divider|divider|add_sub_2_result_int[0]~0\, Mod0|auto_generated|divider|divider|add_sub_2_result_int[0]~0, ALU4, 1
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instance = comp, \Mod0|auto_generated|divider|divider|add_sub_2_result_int[1]~2\, Mod0|auto_generated|divider|divider|add_sub_2_result_int[1]~2, ALU4, 1
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instance = comp, \Mod0|auto_generated|divider|divider|add_sub_2_result_int[2]~4\, Mod0|auto_generated|divider|divider|add_sub_2_result_int[2]~4, ALU4, 1
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instance = comp, \Mod0|auto_generated|divider|divider|add_sub_2_result_int[3]~6\, Mod0|auto_generated|divider|divider|add_sub_2_result_int[3]~6, ALU4, 1
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instance = comp, \Mod0|auto_generated|divider|divider|StageOut[10]~3\, Mod0|auto_generated|divider|divider|StageOut[10]~3, ALU4, 1
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instance = comp, \Mod0|auto_generated|divider|divider|StageOut[9]~4\, Mod0|auto_generated|divider|divider|StageOut[9]~4, ALU4, 1
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instance = comp, \Mod0|auto_generated|divider|divider|StageOut[8]~5\, Mod0|auto_generated|divider|divider|StageOut[8]~5, ALU4, 1
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instance = comp, \Mod0|auto_generated|divider|divider|add_sub_3_result_int[1]~2\, Mod0|auto_generated|divider|divider|add_sub_3_result_int[1]~2, ALU4, 1
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instance = comp, \Mod0|auto_generated|divider|divider|add_sub_3_result_int[2]~4\, Mod0|auto_generated|divider|divider|add_sub_3_result_int[2]~4, ALU4, 1
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instance = comp, \Mod0|auto_generated|divider|divider|add_sub_3_result_int[3]~6\, Mod0|auto_generated|divider|divider|add_sub_3_result_int[3]~6, ALU4, 1
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instance = comp, \Mod0|auto_generated|divider|divider|add_sub_3_result_int[4]~8\, Mod0|auto_generated|divider|divider|add_sub_3_result_int[4]~8, ALU4, 1
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instance = comp, \Mux3~0\, Mux3~0, ALU4, 1
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instance = comp, \Mux3~1\, Mux3~1, ALU4, 1
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instance = comp, \Mux3~2\, Mux3~2, ALU4, 1
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instance = comp, \Mux3~6\, Mux3~6, ALU4, 1
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instance = comp, \Mult0|auto_generated|le3a[1]\, Mult0|auto_generated|le3a[1], ALU4, 1
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instance = comp, \Mult0|auto_generated|op_3~2\, Mult0|auto_generated|op_3~2, ALU4, 1
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instance = comp, \Mux2~2\, Mux2~2, ALU4, 1
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instance = comp, \Mod0|auto_generated|divider|divider|StageOut[13]~6\, Mod0|auto_generated|divider|divider|StageOut[13]~6, ALU4, 1
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instance = comp, \Mux2~3\, Mux2~3, ALU4, 1
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instance = comp, \Add0~5\, Add0~5, ALU4, 1
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instance = comp, \Add0~6\, Add0~6, ALU4, 1
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instance = comp, \Mux2~0\, Mux2~0, ALU4, 1
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instance = comp, \Div0|auto_generated|divider|divider|selnose[10]\, Div0|auto_generated|divider|divider|selnose[10], ALU4, 1
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instance = comp, \Mux2~1\, Mux2~1, ALU4, 1
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instance = comp, \Mux1~2\, Mux1~2, ALU4, 1
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instance = comp, \Mod0|auto_generated|divider|divider|StageOut[14]~7\, Mod0|auto_generated|divider|divider|StageOut[14]~7, ALU4, 1
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instance = comp, \Mux1~3\, Mux1~3, ALU4, 1
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instance = comp, \Mod0|auto_generated|divider|divider|selnose[5]~1\, Mod0|auto_generated|divider|divider|selnose[5]~1, ALU4, 1
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instance = comp, \Mult0|auto_generated|le4a[0]\, Mult0|auto_generated|le4a[0], ALU4, 1
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instance = comp, \Mult0|auto_generated|le3a[2]\, Mult0|auto_generated|le3a[2], ALU4, 1
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instance = comp, \Mult0|auto_generated|le4a[5]\, Mult0|auto_generated|le4a[5], ALU4, 1
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instance = comp, \Mult0|auto_generated|op_1~0\, Mult0|auto_generated|op_1~0, ALU4, 1
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instance = comp, \Mult0|auto_generated|op_3~4\, Mult0|auto_generated|op_3~4, ALU4, 1
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instance = comp, \Add0~8\, Add0~8, ALU4, 1
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instance = comp, \Add0~9\, Add0~9, ALU4, 1
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instance = comp, \Mux1~0\, Mux1~0, ALU4, 1
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instance = comp, \Mux1~1\, Mux1~1, ALU4, 1
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instance = comp, \Mult0|auto_generated|le3a[3]\, Mult0|auto_generated|le3a[3], ALU4, 1
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instance = comp, \Mult0|auto_generated|op_1~2\, Mult0|auto_generated|op_1~2, ALU4, 1
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instance = comp, \Mult0|auto_generated|cs2a[1]~0\, Mult0|auto_generated|cs2a[1]~0, ALU4, 1
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instance = comp, \Mult0|auto_generated|le4a[1]\, Mult0|auto_generated|le4a[1], ALU4, 1
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instance = comp, \Mult0|auto_generated|op_3~6\, Mult0|auto_generated|op_3~6, ALU4, 1
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instance = comp, \Mod0|auto_generated|divider|divider|StageOut[15]~8\, Mod0|auto_generated|divider|divider|StageOut[15]~8, ALU4, 1
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instance = comp, \Mux0~2\, Mux0~2, ALU4, 1
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instance = comp, \Mux0~3\, Mux0~3, ALU4, 1
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instance = comp, \Add0~11\, Add0~11, ALU4, 1
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instance = comp, \Add0~12\, Add0~12, ALU4, 1
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instance = comp, \Mux0~0\, Mux0~0, ALU4, 1
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instance = comp, \Mod0|auto_generated|divider|divider|selnose[0]~2\, Mod0|auto_generated|divider|divider|selnose[0]~2, ALU4, 1
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instance = comp, \Mod0|auto_generated|divider|divider|selnose[0]\, Mod0|auto_generated|divider|divider|selnose[0], ALU4, 1
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instance = comp, \Mux0~1\, Mux0~1, ALU4, 1
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instance = comp, \Mult0|auto_generated|le3a[4]\, Mult0|auto_generated|le3a[4], ALU4, 1
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instance = comp, \Mult0|auto_generated|le4a[2]\, Mult0|auto_generated|le4a[2], ALU4, 1
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instance = comp, \Mult0|auto_generated|op_1~4\, Mult0|auto_generated|op_1~4, ALU4, 1
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instance = comp, \Mult0|auto_generated|le5a[0]\, Mult0|auto_generated|le5a[0], ALU4, 1
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instance = comp, \Mult0|auto_generated|op_3~8\, Mult0|auto_generated|op_3~8, ALU4, 1
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instance = comp, \m~8\, m~8, ALU4, 1
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instance = comp, \Mult0|auto_generated|le5a[1]\, Mult0|auto_generated|le5a[1], ALU4, 1
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instance = comp, \Mult0|auto_generated|le4a[3]\, Mult0|auto_generated|le4a[3], ALU4, 1
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instance = comp, \Mult0|auto_generated|op_1~6\, Mult0|auto_generated|op_1~6, ALU4, 1
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instance = comp, \Mult0|auto_generated|le3a[5]\, Mult0|auto_generated|le3a[5], ALU4, 1
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instance = comp, \Mult0|auto_generated|op_3~10\, Mult0|auto_generated|op_3~10, ALU4, 1
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instance = comp, \m~9\, m~9, ALU4, 1
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instance = comp, \Mult0|auto_generated|le4a[4]\, Mult0|auto_generated|le4a[4], ALU4, 1
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instance = comp, \Mult0|auto_generated|le5a[2]\, Mult0|auto_generated|le5a[2], ALU4, 1
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instance = comp, \Mult0|auto_generated|op_1~8\, Mult0|auto_generated|op_1~8, ALU4, 1
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instance = comp, \Mult0|auto_generated|op_3~12\, Mult0|auto_generated|op_3~12, ALU4, 1
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instance = comp, \m~10\, m~10, ALU4, 1
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instance = comp, \Mult0|auto_generated|le5a[3]\, Mult0|auto_generated|le5a[3], ALU4, 1
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instance = comp, \Mult0|auto_generated|op_1~10\, Mult0|auto_generated|op_1~10, ALU4, 1
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instance = comp, \Mult0|auto_generated|op_3~14\, Mult0|auto_generated|op_3~14, ALU4, 1
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instance = comp, \m~11\, m~11, ALU4, 1
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