28 lines
495 B
VHDL
28 lines
495 B
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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entity pulse_gen is
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generic (MAX : positive := 50_000_000);
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port
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(
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clk : in STD_LOGIC;
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pulse : out STD_LOGIC
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);
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end pulse_gen;
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architecture Behavioral of pulse_gen is
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signal s_cnt : natural range 0 to MAX-1;
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begin
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process(clk)
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begin
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if (rising_edge(clk)) then
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pulse <= '0';
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s_cnt <= s_cnt + 1;
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if (s_cnt = MAX-1) then
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s_cnt <= 0;
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pulse <= '1';
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end if;
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end if;
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end process;
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end Behavioral;
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