43 lines
672 B
VHDL
43 lines
672 B
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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entity FlipFlopD is
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port
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(
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clk : in std_logic;
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d : in std_logic;
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set : in std_logic;
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rst : in std_logic;
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q : out std_logic
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);
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end FlipFlopD;
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architecture BehavS of FlipFlopD is
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begin
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process (clk)
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begin
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if (rising_edge(clk)) then
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if (rst = '1') then
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q <= '0';
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elsif (set = '1') then
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q <= '1';
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else
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q <= d;
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end if;
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end if;
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end process;
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end BehavS;
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architecture BehavAs of FlipFlopD is
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begin
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process (clk, set, rst)
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begin
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if (rst = '1') then
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q <= '0';
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elsif (set = '1') then
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q <= '1';
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elsif (rising_edge(clk)) then
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q <= d;
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end if;
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end process;
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end BehavAs;
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