47 lines
861 B
VHDL
47 lines
861 B
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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entity Debouncers is
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port
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(
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clock : in std_logic;
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reset_btn : in std_logic;
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start_stop_btn : in std_logic;
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time_adjust_btn : in std_logic;
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reset_out : out std_logic;
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start_stop_out : out std_logic;
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time_adjust_out : out std_logic
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);
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end Debouncers;
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architecture Debounce of Debouncers is
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begin
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reset_debouncer : entity work.Debouncer(Behavioral)
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port map
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(
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refClk => clock,
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dirtyIn => reset_btn,
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pulsedOut => reset_out
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);
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timeAdjust_debouncer : entity work.Debouncer(Behavioral)
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port map
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(
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refClk => clock,
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dirtyIn => time_adjust_btn,
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pulsedOut => time_adjust_out
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);
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startStop_debouncer : entity work.Debouncer(Behavioral)
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port map
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(
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refClk => clock,
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dirtyIn => start_stop_btn,
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pulsedOut => start_stop_out
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);
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end Debounce;
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