20 lines
497 B
VHDL
20 lines
497 B
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.NUMERIC_STD.all;
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entity BinToDec is
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port
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(
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binIn : in std_logic_vector(6 downto 0);
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decOut0 : out std_logic_vector(3 downto 0);
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decOut1 : out std_logic_vector(3 downto 0)
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);
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end BinToDec;
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architecture Behavioral of BinToDec is
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signal s_binIn : unsigned(6 downto 0);
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begin
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s_binIn <= unsigned(binIn);
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decOut0 <= std_logic_vector(s_binIn rem 10)(3 downto 0);
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decOut1 <= std_logic_vector(s_binIn / 10)(3 downto 0);
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end Behavioral;
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