39 lines
825 B
VHDL
39 lines
825 B
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.NUMERIC_STD.all;
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entity PulseGeneratorN is
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generic(numberSteps : positive := 8;
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out0CompVal : natural := 2;
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out1CompVal : natural := 4);
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port(clkIn : in std_logic;
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pulseOut0 : out std_logic;
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pulseOut1 : out std_logic);
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end PulseGeneratorN;
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architecture Behavioral of PulseGeneratorN is
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subtype TCounter is natural range 0 to (numberSteps - 1);
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signal s_counter : TCounter;
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begin
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count_proc : process(clkIn)
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begin
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if (rising_edge(clkIn)) then
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if (s_counter >= (numberSteps - 1)) then
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s_counter <= 0;
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else
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s_counter <= s_counter + 1;
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end if;
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end if;
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end process;
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pulseOut0 <= '1' when ((s_counter rem out0CompVal) = 0) else
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'0';
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pulseOut1 <= '1' when (s_counter < out1CompVal) else
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'0';
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end Behavioral;
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