29 lines
604 B
VHDL
29 lines
604 B
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.NUMERIC_STD.all;
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entity AddSub4 is
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port
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(
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sub : in std_logic;
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a, b : in std_logic_vector(3 downto 0);
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cout : out std_logic;
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s : out std_logic_vector(3 downto 0)
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);
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end AddSub4;
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architecture Structural of AddSub4 is
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signal s_b: std_logic_vector(3 downto 0);
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begin
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-- Mux
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sub_mux : s_b <= b when sub = '0' else
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not b;
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-- out_mux : cout <= s_cout when sub='0' else
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-- not s_cout;
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Adder : entity work.Adder4(Structural) port map
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(
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cin => sub, a => a, b => s_b, cout => cout, s => s
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);
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end Structural;
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