44 lines
1.8 KiB
Plaintext
44 lines
1.8 KiB
Plaintext
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# do Mux4_1Demo.do
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# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
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# Start time: 22:35:04 on Mar 07,2023
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# vcom -work work Mux4_1Demo.vho
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# -- Loading package STANDARD
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# -- Loading package TEXTIO
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# -- Loading package std_logic_1164
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# -- Loading package VITAL_Timing
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# -- Loading package VITAL_Primitives
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# -- Loading package cycloneive_atom_pack
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# -- Loading package cycloneive_components
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# -- Compiling entity Mux4_1
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# -- Compiling architecture structure of Mux4_1
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# End time: 22:35:05 on Mar 07,2023, Elapsed time: 0:00:01
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# Errors: 0, Warnings: 0
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# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
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# Start time: 22:35:05 on Mar 07,2023
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# vcom -work work Mux4_1.vwf.vht
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# -- Loading package STANDARD
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# -- Loading package TEXTIO
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# -- Loading package std_logic_1164
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# -- Compiling entity Mux4_1_vhd_vec_tst
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# -- Compiling architecture Mux4_1_arch of Mux4_1_vhd_vec_tst
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# End time: 22:35:05 on Mar 07,2023, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.Mux4_1_vhd_vec_tst
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# Start time: 22:35:05 on Mar 07,2023
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# Loading std.standard
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# Loading std.textio(body)
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# Loading ieee.std_logic_1164(body)
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# Loading work.mux4_1_vhd_vec_tst(mux4_1_arch)
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# Loading ieee.vital_timing(body)
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# Loading ieee.vital_primitives(body)
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# Loading cycloneive.cycloneive_atom_pack(body)
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# Loading cycloneive.cycloneive_components
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# Loading work.mux4_1(structure)
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# Loading ieee.std_logic_arith(body)
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# Loading cycloneive.cycloneive_io_obuf(arch)
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# Loading cycloneive.cycloneive_io_ibuf(arch)
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# Loading cycloneive.cycloneive_lcell_comb(vital_lcell_comb)
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# after#29
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# End time: 22:35:05 on Mar 07,2023, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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