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uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemoVHDL/simulation/modelsim/DisplayDemoVHDL.vho

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[LSD] DisplayDemo using VHDL finished
2023-03-08 20:58:26 +00:00
-- Copyright (C) 2020 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and any partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details, at
-- https://fpgasoftware.intel.com/eula.
-- VENDOR "Altera"
-- PROGRAM "Quartus Prime"
-- VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
-- DATE "03/08/2023 20:54:26"
--
-- Device: Altera EP4CE115F29C7 Package FBGA780
--
--
-- This VHDL file should be used for ModelSim-Altera (VHDL) only
--
LIBRARY CYCLONEIVE;
LIBRARY IEEE;
USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY hard_block IS
PORT (
devoe : IN std_logic;
devclrn : IN std_logic;
devpor : IN std_logic
);
END hard_block;
-- Design Ports Information
-- ~ALTERA_ASDO_DATA1~ => Location: PIN_F4, I/O Standard: 2.5 V, Current Strength: Default
-- ~ALTERA_FLASH_nCE_nCSO~ => Location: PIN_E2, I/O Standard: 2.5 V, Current Strength: Default
-- ~ALTERA_DCLK~ => Location: PIN_P3, I/O Standard: 2.5 V, Current Strength: Default
-- ~ALTERA_DATA0~ => Location: PIN_N7, I/O Standard: 2.5 V, Current Strength: Default
-- ~ALTERA_nCEO~ => Location: PIN_P28, I/O Standard: 2.5 V, Current Strength: 8mA
ARCHITECTURE structure OF hard_block IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL unknown : std_logic := 'X';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL \~ALTERA_ASDO_DATA1~~padout\ : std_logic;
SIGNAL \~ALTERA_FLASH_nCE_nCSO~~padout\ : std_logic;
SIGNAL \~ALTERA_DATA0~~padout\ : std_logic;
SIGNAL \~ALTERA_ASDO_DATA1~~ibuf_o\ : std_logic;
SIGNAL \~ALTERA_FLASH_nCE_nCSO~~ibuf_o\ : std_logic;
SIGNAL \~ALTERA_DATA0~~ibuf_o\ : std_logic;
BEGIN
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;
END structure;
LIBRARY CYCLONEIVE;
LIBRARY IEEE;
USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY DisplayDemoVHDL IS
PORT (
SW : IN std_logic_vector(3 DOWNTO 0);
KEY : IN std_logic_vector(1 DOWNTO 0);
LEDG : OUT std_logic_vector(3 DOWNTO 0);
LEDR : OUT std_logic_vector(6 DOWNTO 0);
HEX0 : OUT std_logic_vector(6 DOWNTO 0)
);
END DisplayDemoVHDL;
-- Design Ports Information
-- KEY[1] => Location: PIN_M21, I/O Standard: 2.5 V, Current Strength: Default
-- LEDG[0] => Location: PIN_E21, I/O Standard: 2.5 V, Current Strength: Default
-- LEDG[1] => Location: PIN_E22, I/O Standard: 2.5 V, Current Strength: Default
-- LEDG[2] => Location: PIN_E25, I/O Standard: 2.5 V, Current Strength: Default
-- LEDG[3] => Location: PIN_E24, I/O Standard: 2.5 V, Current Strength: Default
-- LEDR[0] => Location: PIN_G19, I/O Standard: 2.5 V, Current Strength: Default
-- LEDR[1] => Location: PIN_F19, I/O Standard: 2.5 V, Current Strength: Default
-- LEDR[2] => Location: PIN_E19, I/O Standard: 2.5 V, Current Strength: Default
-- LEDR[3] => Location: PIN_F21, I/O Standard: 2.5 V, Current Strength: Default
-- LEDR[4] => Location: PIN_F18, I/O Standard: 2.5 V, Current Strength: Default
-- LEDR[5] => Location: PIN_E18, I/O Standard: 2.5 V, Current Strength: Default
-- LEDR[6] => Location: PIN_J19, I/O Standard: 2.5 V, Current Strength: Default
-- HEX0[0] => Location: PIN_G18, I/O Standard: 2.5 V, Current Strength: Default
-- HEX0[1] => Location: PIN_F22, I/O Standard: 2.5 V, Current Strength: Default
-- HEX0[2] => Location: PIN_E17, I/O Standard: 2.5 V, Current Strength: Default
-- HEX0[3] => Location: PIN_L26, I/O Standard: 2.5 V, Current Strength: Default
-- HEX0[4] => Location: PIN_L25, I/O Standard: 2.5 V, Current Strength: Default
-- HEX0[5] => Location: PIN_J22, I/O Standard: 2.5 V, Current Strength: Default
-- HEX0[6] => Location: PIN_H22, I/O Standard: 2.5 V, Current Strength: Default
-- SW[0] => Location: PIN_AB28, I/O Standard: 2.5 V, Current Strength: Default
-- SW[1] => Location: PIN_AC28, I/O Standard: 2.5 V, Current Strength: Default
-- SW[2] => Location: PIN_AC27, I/O Standard: 2.5 V, Current Strength: Default
-- SW[3] => Location: PIN_AD27, I/O Standard: 2.5 V, Current Strength: Default
-- KEY[0] => Location: PIN_M23, I/O Standard: 2.5 V, Current Strength: Default
ARCHITECTURE structure OF DisplayDemoVHDL IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL unknown : std_logic := 'X';
SIGNAL devoe : std_logic := '1';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_SW : std_logic_vector(3 DOWNTO 0);
SIGNAL ww_KEY : std_logic_vector(1 DOWNTO 0);
SIGNAL ww_LEDG : std_logic_vector(3 DOWNTO 0);
SIGNAL ww_LEDR : std_logic_vector(6 DOWNTO 0);
SIGNAL ww_HEX0 : std_logic_vector(6 DOWNTO 0);
SIGNAL \KEY[1]~input_o\ : std_logic;
SIGNAL \LEDG[0]~output_o\ : std_logic;
SIGNAL \LEDG[1]~output_o\ : std_logic;
SIGNAL \LEDG[2]~output_o\ : std_logic;
SIGNAL \LEDG[3]~output_o\ : std_logic;
SIGNAL \LEDR[0]~output_o\ : std_logic;
SIGNAL \LEDR[1]~output_o\ : std_logic;
SIGNAL \LEDR[2]~output_o\ : std_logic;
SIGNAL \LEDR[3]~output_o\ : std_logic;
SIGNAL \LEDR[4]~output_o\ : std_logic;
SIGNAL \LEDR[5]~output_o\ : std_logic;
SIGNAL \LEDR[6]~output_o\ : std_logic;
SIGNAL \HEX0[0]~output_o\ : std_logic;
SIGNAL \HEX0[1]~output_o\ : std_logic;
SIGNAL \HEX0[2]~output_o\ : std_logic;
SIGNAL \HEX0[3]~output_o\ : std_logic;
SIGNAL \HEX0[4]~output_o\ : std_logic;
SIGNAL \HEX0[5]~output_o\ : std_logic;
SIGNAL \HEX0[6]~output_o\ : std_logic;
SIGNAL \SW[0]~input_o\ : std_logic;
SIGNAL \SW[1]~input_o\ : std_logic;
SIGNAL \SW[2]~input_o\ : std_logic;
SIGNAL \SW[3]~input_o\ : std_logic;
SIGNAL \KEY[0]~input_o\ : std_logic;
SIGNAL \system_core|decOut_n~6_combout\ : std_logic;
SIGNAL \system_core|decOut_n~7_combout\ : std_logic;
SIGNAL \system_core|decOut_n~8_combout\ : std_logic;
SIGNAL \system_core|decOut_n~9_combout\ : std_logic;
SIGNAL \system_core|decOut_n~10_combout\ : std_logic;
SIGNAL \system_core|decOut_n~11_combout\ : std_logic;
SIGNAL \system_core|decOut_n[3]~2_combout\ : std_logic;
SIGNAL \system_core|decOut_n[3]~16_combout\ : std_logic;
SIGNAL \system_core|decOut_n~12_combout\ : std_logic;
SIGNAL \system_core|decOut_n~13_combout\ : std_logic;
SIGNAL \system_core|decOut_n~14_combout\ : std_logic;
SIGNAL \system_core|decOut_n~15_combout\ : std_logic;
SIGNAL \system_core|decOut_n[6]~5_combout\ : std_logic;
SIGNAL \system_core|decOut_n[6]~17_combout\ : std_logic;
COMPONENT hard_block
PORT (
devoe : IN std_logic;
devclrn : IN std_logic;
devpor : IN std_logic);
END COMPONENT;
BEGIN
ww_SW <= SW;
ww_KEY <= KEY;
LEDG <= ww_LEDG;
LEDR <= ww_LEDR;
HEX0 <= ww_HEX0;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;
auto_generated_inst : hard_block
PORT MAP (
devoe => ww_devoe,
devclrn => ww_devclrn,
devpor => ww_devpor);
-- Location: IOOBUF_X107_Y73_N9
\LEDG[0]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false")
-- pragma translate_on
PORT MAP (
i => \SW[0]~input_o\,
devoe => ww_devoe,
o => \LEDG[0]~output_o\);
-- Location: IOOBUF_X111_Y73_N9
\LEDG[1]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false")
-- pragma translate_on
PORT MAP (
i => \SW[1]~input_o\,
devoe => ww_devoe,
o => \LEDG[1]~output_o\);
-- Location: IOOBUF_X83_Y73_N2
\LEDG[2]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false")
-- pragma translate_on
PORT MAP (
i => \SW[2]~input_o\,
devoe => ww_devoe,
o => \LEDG[2]~output_o\);
-- Location: IOOBUF_X85_Y73_N23
\LEDG[3]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false")
-- pragma translate_on
PORT MAP (
i => \SW[3]~input_o\,
devoe => ww_devoe,
o => \LEDG[3]~output_o\);
-- Location: IOOBUF_X69_Y73_N16
\LEDR[0]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false")
-- pragma translate_on
PORT MAP (
i => \system_core|decOut_n~7_combout\,
devoe => ww_devoe,
o => \LEDR[0]~output_o\);
-- Location: IOOBUF_X94_Y73_N2
\LEDR[1]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false")
-- pragma translate_on
PORT MAP (
i => \system_core|decOut_n~9_combout\,
devoe => ww_devoe,
o => \LEDR[1]~output_o\);
-- Location: IOOBUF_X94_Y73_N9
\LEDR[2]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false")
-- pragma translate_on
PORT MAP (
i => \system_core|decOut_n~11_combout\,
devoe => ww_devoe,
o => \LEDR[2]~output_o\);
-- Location: IOOBUF_X107_Y73_N16
\LEDR[3]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false")
-- pragma translate_on
PORT MAP (
i => \system_core|decOut_n[3]~16_combout\,
devoe => ww_devoe,
o => \LEDR[3]~output_o\);
-- Location: IOOBUF_X87_Y73_N16
\LEDR[4]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false")
-- pragma translate_on
PORT MAP (
i => \system_core|decOut_n~13_combout\,
devoe => ww_devoe,
o => \LEDR[4]~output_o\);
-- Location: IOOBUF_X87_Y73_N9
\LEDR[5]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false")
-- pragma translate_on
PORT MAP (
i => \system_core|decOut_n~15_combout\,
devoe => ww_devoe,
o => \LEDR[5]~output_o\);
-- Location: IOOBUF_X72_Y73_N9
\LEDR[6]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false")
-- pragma translate_on
PORT MAP (
i => \system_core|decOut_n[6]~17_combout\,
devoe => ww_devoe,
o => \LEDR[6]~output_o\);
-- Location: IOOBUF_X69_Y73_N23
\HEX0[0]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false")
-- pragma translate_on
PORT MAP (
i => \system_core|decOut_n~7_combout\,
devoe => ww_devoe,
o => \HEX0[0]~output_o\);
-- Location: IOOBUF_X107_Y73_N23
\HEX0[1]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false")
-- pragma translate_on
PORT MAP (
i => \system_core|decOut_n~9_combout\,
devoe => ww_devoe,
o => \HEX0[1]~output_o\);
-- Location: IOOBUF_X67_Y73_N23
\HEX0[2]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false")
-- pragma translate_on
PORT MAP (
i => \system_core|decOut_n~11_combout\,
devoe => ww_devoe,
o => \HEX0[2]~output_o\);
-- Location: IOOBUF_X115_Y50_N2
\HEX0[3]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false")
-- pragma translate_on
PORT MAP (
i => \system_core|decOut_n[3]~16_combout\,
devoe => ww_devoe,
o => \HEX0[3]~output_o\);
-- Location: IOOBUF_X115_Y54_N16
\HEX0[4]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false")
-- pragma translate_on
PORT MAP (
i => \system_core|decOut_n~13_combout\,
devoe => ww_devoe,
o => \HEX0[4]~output_o\);
-- Location: IOOBUF_X115_Y67_N16
\HEX0[5]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false")
-- pragma translate_on
PORT MAP (
i => \system_core|decOut_n~15_combout\,
devoe => ww_devoe,
o => \HEX0[5]~output_o\);
-- Location: IOOBUF_X115_Y69_N2
\HEX0[6]~output\ : cycloneive_io_obuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
open_drain_output => "false")
-- pragma translate_on
PORT MAP (
i => \system_core|decOut_n[6]~17_combout\,
devoe => ww_devoe,
o => \HEX0[6]~output_o\);
-- Location: IOIBUF_X115_Y17_N1
\SW[0]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_SW(0),
o => \SW[0]~input_o\);
-- Location: IOIBUF_X115_Y14_N1
\SW[1]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_SW(1),
o => \SW[1]~input_o\);
-- Location: IOIBUF_X115_Y15_N8
\SW[2]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_SW(2),
o => \SW[2]~input_o\);
-- Location: IOIBUF_X115_Y13_N8
\SW[3]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_SW(3),
o => \SW[3]~input_o\);
-- Location: IOIBUF_X115_Y40_N8
\KEY[0]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_KEY(0),
o => \KEY[0]~input_o\);
-- Location: LCCOMB_X107_Y72_N24
\system_core|decOut_n~6\ : cycloneive_lcell_comb
-- Equation(s):
-- \system_core|decOut_n~6_combout\ = (\SW[3]~input_o\ & (\SW[0]~input_o\ & (\SW[1]~input_o\ $ (\SW[2]~input_o\)))) # (!\SW[3]~input_o\ & (!\SW[1]~input_o\ & (\SW[0]~input_o\ $ (\SW[2]~input_o\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "0000100110000100",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \SW[3]~input_o\,
datab => \SW[0]~input_o\,
datac => \SW[1]~input_o\,
datad => \SW[2]~input_o\,
combout => \system_core|decOut_n~6_combout\);
-- Location: LCCOMB_X107_Y72_N26
\system_core|decOut_n~7\ : cycloneive_lcell_comb
-- Equation(s):
-- \system_core|decOut_n~7_combout\ = (\KEY[0]~input_o\) # (\system_core|decOut_n~6_combout\)
-- pragma translate_off
GENERIC MAP (
lut_mask => "1111111111110000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
datac => \KEY[0]~input_o\,
datad => \system_core|decOut_n~6_combout\,
combout => \system_core|decOut_n~7_combout\);
-- Location: LCCOMB_X107_Y72_N20
\system_core|decOut_n~8\ : cycloneive_lcell_comb
-- Equation(s):
-- \system_core|decOut_n~8_combout\ = (\SW[3]~input_o\ & ((\SW[0]~input_o\ & (\SW[1]~input_o\)) # (!\SW[0]~input_o\ & ((\SW[2]~input_o\))))) # (!\SW[3]~input_o\ & (\SW[2]~input_o\ & (\SW[0]~input_o\ $ (\SW[1]~input_o\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1011011010000000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \SW[3]~input_o\,
datab => \SW[0]~input_o\,
datac => \SW[1]~input_o\,
datad => \SW[2]~input_o\,
combout => \system_core|decOut_n~8_combout\);
-- Location: LCCOMB_X107_Y72_N22
\system_core|decOut_n~9\ : cycloneive_lcell_comb
-- Equation(s):
-- \system_core|decOut_n~9_combout\ = (\KEY[0]~input_o\) # (\system_core|decOut_n~8_combout\)
-- pragma translate_off
GENERIC MAP (
lut_mask => "1111111111110000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
datac => \KEY[0]~input_o\,
datad => \system_core|decOut_n~8_combout\,
combout => \system_core|decOut_n~9_combout\);
-- Location: LCCOMB_X107_Y72_N16
\system_core|decOut_n~10\ : cycloneive_lcell_comb
-- Equation(s):
-- \system_core|decOut_n~10_combout\ = (\SW[3]~input_o\ & (\SW[0]~input_o\ & !\SW[1]~input_o\)) # (!\SW[3]~input_o\ & (!\SW[0]~input_o\ & \SW[1]~input_o\))
-- pragma translate_off
GENERIC MAP (
lut_mask => "0001100000011000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \SW[3]~input_o\,
datab => \SW[0]~input_o\,
datac => \SW[1]~input_o\,
combout => \system_core|decOut_n~10_combout\);
-- Location: LCCOMB_X107_Y72_N18
\system_core|decOut_n~11\ : cycloneive_lcell_comb
-- Equation(s):
-- \system_core|decOut_n~11_combout\ = (\KEY[0]~input_o\) # ((\SW[3]~input_o\ & (!\system_core|decOut_n~10_combout\ & \SW[2]~input_o\)) # (!\SW[3]~input_o\ & (\system_core|decOut_n~10_combout\ & !\SW[2]~input_o\)))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1111001011110100",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \SW[3]~input_o\,
datab => \system_core|decOut_n~10_combout\,
datac => \KEY[0]~input_o\,
datad => \SW[2]~input_o\,
combout => \system_core|decOut_n~11_combout\);
-- Location: LCCOMB_X107_Y72_N12
\system_core|decOut_n[3]~2\ : cycloneive_lcell_comb
-- Equation(s):
-- \system_core|decOut_n[3]~2_combout\ = (\SW[1]~input_o\ & ((\SW[0]~input_o\ & ((\SW[2]~input_o\))) # (!\SW[0]~input_o\ & (\SW[3]~input_o\ & !\SW[2]~input_o\)))) # (!\SW[1]~input_o\ & (!\SW[3]~input_o\ & (\SW[0]~input_o\ $ (\SW[2]~input_o\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "1100000100100100",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \SW[3]~input_o\,
datab => \SW[0]~input_o\,
datac => \SW[1]~input_o\,
datad => \SW[2]~input_o\,
combout => \system_core|decOut_n[3]~2_combout\);
-- Location: LCCOMB_X107_Y72_N14
\system_core|decOut_n[3]~16\ : cycloneive_lcell_comb
-- Equation(s):
-- \system_core|decOut_n[3]~16_combout\ = (\KEY[0]~input_o\) # (\system_core|decOut_n[3]~2_combout\)
-- pragma translate_off
GENERIC MAP (
lut_mask => "1111111111110000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
datac => \KEY[0]~input_o\,
datad => \system_core|decOut_n[3]~2_combout\,
combout => \system_core|decOut_n[3]~16_combout\);
-- Location: LCCOMB_X107_Y72_N28
\system_core|decOut_n~12\ : cycloneive_lcell_comb
-- Equation(s):
-- \system_core|decOut_n~12_combout\ = (\SW[1]~input_o\ & (!\SW[3]~input_o\ & (\SW[0]~input_o\))) # (!\SW[1]~input_o\ & ((\SW[2]~input_o\ & (!\SW[3]~input_o\)) # (!\SW[2]~input_o\ & ((\SW[0]~input_o\)))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "0100010101001100",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \SW[3]~input_o\,
datab => \SW[0]~input_o\,
datac => \SW[1]~input_o\,
datad => \SW[2]~input_o\,
combout => \system_core|decOut_n~12_combout\);
-- Location: LCCOMB_X107_Y72_N30
\system_core|decOut_n~13\ : cycloneive_lcell_comb
-- Equation(s):
-- \system_core|decOut_n~13_combout\ = (\KEY[0]~input_o\) # (\system_core|decOut_n~12_combout\)
-- pragma translate_off
GENERIC MAP (
lut_mask => "1111111111110000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
datac => \KEY[0]~input_o\,
datad => \system_core|decOut_n~12_combout\,
combout => \system_core|decOut_n~13_combout\);
-- Location: LCCOMB_X107_Y72_N8
\system_core|decOut_n~14\ : cycloneive_lcell_comb
-- Equation(s):
-- \system_core|decOut_n~14_combout\ = (\SW[0]~input_o\ & (\SW[3]~input_o\ $ (((\SW[1]~input_o\) # (!\SW[2]~input_o\))))) # (!\SW[0]~input_o\ & (!\SW[3]~input_o\ & (\SW[1]~input_o\ & !\SW[2]~input_o\)))
-- pragma translate_off
GENERIC MAP (
lut_mask => "0100100001010100",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \SW[3]~input_o\,
datab => \SW[0]~input_o\,
datac => \SW[1]~input_o\,
datad => \SW[2]~input_o\,
combout => \system_core|decOut_n~14_combout\);
-- Location: LCCOMB_X107_Y72_N2
\system_core|decOut_n~15\ : cycloneive_lcell_comb
-- Equation(s):
-- \system_core|decOut_n~15_combout\ = (\system_core|decOut_n~14_combout\) # (\KEY[0]~input_o\)
-- pragma translate_off
GENERIC MAP (
lut_mask => "1111110011111100",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
datab => \system_core|decOut_n~14_combout\,
datac => \KEY[0]~input_o\,
combout => \system_core|decOut_n~15_combout\);
-- Location: LCCOMB_X107_Y72_N0
\system_core|decOut_n[6]~5\ : cycloneive_lcell_comb
-- Equation(s):
-- \system_core|decOut_n[6]~5_combout\ = (\SW[0]~input_o\ & (!\SW[3]~input_o\ & (\SW[1]~input_o\ $ (!\SW[2]~input_o\)))) # (!\SW[0]~input_o\ & (!\SW[1]~input_o\ & (\SW[3]~input_o\ $ (!\SW[2]~input_o\))))
-- pragma translate_off
GENERIC MAP (
lut_mask => "0100001000000101",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
dataa => \SW[3]~input_o\,
datab => \SW[0]~input_o\,
datac => \SW[1]~input_o\,
datad => \SW[2]~input_o\,
combout => \system_core|decOut_n[6]~5_combout\);
-- Location: LCCOMB_X107_Y72_N10
\system_core|decOut_n[6]~17\ : cycloneive_lcell_comb
-- Equation(s):
-- \system_core|decOut_n[6]~17_combout\ = (\KEY[0]~input_o\) # (\system_core|decOut_n[6]~5_combout\)
-- pragma translate_off
GENERIC MAP (
lut_mask => "1111111111110000",
sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
datac => \KEY[0]~input_o\,
datad => \system_core|decOut_n[6]~5_combout\,
combout => \system_core|decOut_n[6]~17_combout\);
-- Location: IOIBUF_X115_Y53_N15
\KEY[1]~input\ : cycloneive_io_ibuf
-- pragma translate_off
GENERIC MAP (
bus_hold => "false",
simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
i => ww_KEY(1),
o => \KEY[1]~input_o\);
ww_LEDG(0) <= \LEDG[0]~output_o\;
ww_LEDG(1) <= \LEDG[1]~output_o\;
ww_LEDG(2) <= \LEDG[2]~output_o\;
ww_LEDG(3) <= \LEDG[3]~output_o\;
ww_LEDR(0) <= \LEDR[0]~output_o\;
ww_LEDR(1) <= \LEDR[1]~output_o\;
ww_LEDR(2) <= \LEDR[2]~output_o\;
ww_LEDR(3) <= \LEDR[3]~output_o\;
ww_LEDR(4) <= \LEDR[4]~output_o\;
ww_LEDR(5) <= \LEDR[5]~output_o\;
ww_LEDR(6) <= \LEDR[6]~output_o\;
ww_HEX0(0) <= \HEX0[0]~output_o\;
ww_HEX0(1) <= \HEX0[1]~output_o\;
ww_HEX0(2) <= \HEX0[2]~output_o\;
ww_HEX0(3) <= \HEX0[3]~output_o\;
ww_HEX0(4) <= \HEX0[4]~output_o\;
ww_HEX0(5) <= \HEX0[5]~output_o\;
ww_HEX0(6) <= \HEX0[6]~output_o\;
END structure;